JP5235372B2 - Pulse generator - Google Patents

Description

  The present invention relates to a pulse generator. In particular, the present invention relates to a pulse generator capable of seamlessly changing pulse generation conditions.

  Conventionally, a pulse generator that generates and outputs a pulse signal at a predetermined cycle is used. This type of pulse generator is used to supply an output pulse signal to a load circuit such as an inverter circuit.

  A block diagram of a conventional pulse generator 300 is shown in FIG. The pulse generator 300 supplies the synchronization signal Sy and the output pulse signal So to a load circuit 400 such as an inverter circuit.

  The pulse generator 300 includes an oscillator 360 that supplies a pulse signal having a predetermined frequency as a reference clock, a pulse generation counter 310 that receives a pulse signal generated by the oscillator 360 and counts up, and a count value and a period of the pulse generation counter 310. A digital comparator 320 that clears the pulse generation counter 310 based on the period value Th set in the value setting register 321 and causes the pulse generation counter 310 to generate the synchronization signal Sy in the period.

  Further, the pulse generator 300 compares the count value of the pulse generation counter 310 with the front end timing value Tf set in the front end timing value setting register 331 for each cycle, and sets the output pulse signal at the front end timing. Similarly to the digital comparator 333 that outputs a signal to be increased, the count value of the pulse generation counter 310 is compared with the rear end timing value Tb set in the rear end timing value setting register 334, and the output pulse is output at the rear end timing. A digital comparator 336 that outputs a signal that causes the signal to fall, and an output pulse generation means 337 that generates an output pulse signal So based on the signals output from the digital comparators 333 and 336 are provided.

  In FIG. 8, each of the synchronization signal Sy and the output pulse signal So output from the pulse generator 300 is supplied to the load circuit 400.

  Next, how the pulse generator 300 shown in FIG. 8 generates the output pulse signal So will be described with reference to the timing chart shown in FIG. 9, (a) shows the waveform of the synchronization signal Sy generated by the pulse generation counter 310, (b) shows the count value Cp of the pulse generation counter 310, and (c) shows the output pulse generation circuit 337. Shows an output pulse signal So generated by.

  The count value Cp in (b) is cleared to zero with the rise of the synchronization signal Sy in (a) at time t1. The pulse generation counter 310 then counts up, and the count value Cp is cleared to zero again with the rise of the synchronization signal Sy. The predetermined time interval at which the count value Cp is cleared is the periodic value Th of the periodic signal Sy.

  The delay time value Tr from the time t1 of (c) to the rise of the output pulse signal So is determined by the front end timing value Tf. The pulse width Pw of the output pulse signal So in (c) is determined by the difference between the rear end timing value Tb and the front end timing value Tf. In this way, the output pulse signal So of (c) is generated between the times t2 and t3. The output pulse signal So is repeatedly generated every period as shown in (c).

  As a method of changing the cycle value of the output pulse signal So described above, for example, a method of changing the cycle value Th stored in the cycle value setting register 321 or a stable signal in a wide range of frequencies can be seamlessly (seamlessly). From the viewpoint of generation, there is a method using a direct digital synthesizer (DDS) as the oscillator.

  In the pulse generator 300, in order to change the delay time value Tr or the pulse width Pw of the output pulse signal So, the parameters of the pulse generation conditions such as the period value Th, the front end timing value Tf, or the rear end timing value Tb are changed. Just do it. However, depending on the timing of changing these parameters, an unnecessary output pulse signal So ′ may be generated as shown in FIG. 10C, and the seamless frequency change may not be performed.

  FIG. 10 is a timing diagram illustrating a case where the pulse generation conditions are changed. (A) to (c) in FIG. 10 show the same as (a) to (c) in FIG. 9, but the pulse generation conditions are changed between times t3 and t4. Yes.

  In the example shown in FIG. 10, the parameters of the pulse generation condition are changed such that the front end timing value Tf is Tf ′ and the rear end timing value Tb is Tb ′. Since the parameter change is performed between time t3 and t4, an unnecessary output pulse signal So ′ is generated along with the output pulse signal So based on the changed pulse generation condition.

  As a technique for avoiding the generation of the unnecessary output pulse signal, the pulse generation condition may be changed at the same timing as the synchronization signal. However, if the pulse generation condition cannot always be changed in the same cycle as the synchronization signal, when using a synchronization signal having a very long cycle value, for example, when 1000 seconds is erroneously set as the cycle value, There is a problem that the pulse generation conditions cannot be changed until the period elapses, and the operability is deteriorated.

  Furthermore, since the pulse generator may generate and stop the output pulse signal based on a command signal from the outside of the device, the output pulse signal is generated and stopped based on the command signal outside the device. Is controlled, it is difficult to change the pulse generation condition in the same cycle as the synchronization signal.

  SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a pulse generator capable of seamlessly changing pulse generation conditions even when generating and stopping an output pulse signal based on a command signal from the outside of the apparatus. .

  In order to solve the above-described problems, a pulse generator according to the present invention includes a first count unit that counts the number of pulses of a predetermined frequency pulse signal, a count value of the first count unit, and a set cycle value. Based on the first count means, the synchronization signal generation means for generating a synchronization signal in the cycle, the count value and the front and rear end timing values set for each cycle, Generation means for generating an output pulse signal having a pulse generation condition determined based on the update command signal, and an update signal generation means for generating an update signal for updating the pulse generation condition of the output pulse signal based on an input of the update command signal And control means for controlling the update signal generating means, wherein the control means is smaller than the update control time value for which the period value is set. In this case, the update signal is generated in synchronization with the synchronization signal of the next input, and when the period value is larger than the update control time value, the update signal is generated in synchronization with the input of the update command. It is characterized by that.

  According to the above-described pulse generator according to the present invention, even when the output pulse signal is generated and stopped based on a command signal from the outside of the device, the pulse generation conditions can be changed seamlessly.

  Hereinafter, a preferred embodiment of a pulse generator according to the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a pulse generator according to the present invention.

  As shown in FIG. 1, the pulse generator 100 according to the present embodiment includes a first count unit 10 that counts the number of pulses of a predetermined frequency pulse signal, and a count value Cp of the first count unit 10 and a set cycle value. Based on Th, the first count means 10 is cleared, and the first count means 10 generates the synchronization signal Sy in the cycle, and the front end timing set with the count value Cp for each period. The pulse generation means 30 for generating the output pulse signal So having a pulse generation condition determined based on the value Tf and the trailing edge timing value Tb, and the pulse generation condition for the output pulse signal So based on the input of the update command signal S3 An update signal generating means 40 for generating an update signal S2 to be updated, and a control means 50 for controlling the update signal generating means 40 are provided. There.

  As shown in FIG. 1, the pulse generator 100 of the present embodiment is supplied with the synchronization signal Sy generated by the synchronization signal generation unit 20 and the output pulse signal So generated by the pulse generation unit 30 to the load circuit 200. The An example of the load circuit 200 is an inverter circuit.

  In the pulse generator 100 of the present embodiment, the first count unit 10 is controlled to start or stop counting the number of pulses by a command signal. This command signal may be supplied from the outside of the pulse generator 100 or supplied from the inside of the apparatus.

  The synchronization signal Sy generated by the synchronization signal generation means 20 is used as a reference for specifying the cycle of the input output pulse signal So in the load circuit 200 to which the output pulse signal So is supplied. In the pulse generator 100 of the present embodiment, this synchronization signal Sy is used as a synchronization signal for each component.

  The control means 50 includes at least a CPU, a ROM, a RAM, a display unit, and an operation input unit (not shown), and controls the update signal generation unit 40 according to a program stored in advance. The CPU of the control unit 50 may also control other components of the pulse generator 100.

  When the cycle value Th is smaller than the set update control time value Ti, the control means 50 generates the update signal S2 in synchronization with the synchronization signal of the next input, and the cycle value Th is the update control time value. If it is greater than Ti, the update signal S2 is generated in synchronization with the input of the update command S3.

  The update control time value Ti is a time value arbitrarily determined by a user or the like. Even if the command signal is supplied from the outside of the pulse generator 100, the pulse generator 100 of the present embodiment synchronizes with the periodic signal Sy by performing the process using the update control time Ti. This makes it possible to change the pulse generation conditions.

  Hereinafter, an example of the above-described pulse generator 100 of the present embodiment will be described with reference to the drawings. FIG. 2 is a block diagram showing an embodiment of the pulse generator 100 of FIG.

As shown in FIG. 2, the pulse generator 100 according to the present embodiment includes an oscillator 60 that supplies a pulse signal having a predetermined frequency as a reference clock. As the oscillator 60, for example, a crystal oscillator can be used. The oscillator 60 outputs a pulse signal of the reference clock to the pulse generation counter 10 and the control means 50.
Hereinafter, other components of the pulse generator 100 will be described in detail.

First, the pulse generation counter 10 as the first counting means will be described below.
In the pulse generation counter 10 of the present embodiment, as shown in FIG. 2, the start or stop of counting the number of pulses is controlled by a command signal Se from the outside of the pulse generator 100. The pulse generation counter 10 starts counting when the count start command signal Se is input (the command signal Se is in the H state), outputs the count value Cp to the synchronization signal generation means 20 and the pulse generation means 30, and outputs an output pulse signal. So is generated. On the other hand, in a state where the command signal Se is not input (a state where the command signal Se is L), the pulse generation counter 10 stops counting and does not generate the output pulse signal So.

  The pulse generation counter 10 counts the number of pulses of the pulse signal that is the reference clock output from the oscillator 60 and outputs the count value Cp to the synchronization signal generation means 20. The pulse generation counter 10 receives a clear signal CL output from a synchronization signal generation means 20 described later, and the count value Cp is cleared. The pulse generation counter 10 is preferably a synchronous counter. In this embodiment, a synchronous up counter is used.

  The pulse generation counter 10 outputs a synchronization signal Sy having a predetermined cycle to the update signal generation means 40 and the control means 50. Further, the pulse generation counter 10 outputs the synchronization signal Sy to the load circuit 200.

  The pulse generation counter 10 can be configured using a known circuit. The clear signal CL output from the synchronization signal generation means 20 can be input to the clear terminal of the pulse generation counter circuit, for example.

Next, the synchronization signal generating means 20 will be described below.
As shown in FIG. 2, the synchronization signal generation unit 20 includes a first period value setting register 21, a second period value setting register 22, and a synchronization signal generation comparator 23.

  The first cycle value setting register 21 stores the cycle value Th of the synchronization signal Sy generated by the pulse generation counter 10. This cycle value Th is set in the first cycle value setting register 21 by the control means 50 described later. The first cycle value setting register 21 outputs the set cycle value Th to the second cycle value setting register 22. This period value Th is the period value of the output pulse signal So output from the pulse generator 100.

  The second cycle value setting register 22 stores the cycle value Th output from the first cycle value setting register 21 when an update signal S2 generated by an update signal generation means 40 described later is input. The second cycle value setting register 22 outputs the set cycle value Th to the synchronization signal generation comparator 23.

  The synchronization signal generation comparator 23 inputs the count value Cp output from the pulse generation counter 10 to one input unit. Also, the cycle value Th output from the second cycle value setting register 22 is input to the other input unit.

  The synchronization signal generation comparator 23 compares the input count value Cp with the cycle value Th set in the second cycle value setting register 22, and the count value Cp and the count value Cp match the cycle value Th. Or if it is greater than the period value Th, a clear signal CL for clearing the count value Cp of the pulse generation counter 10 is output to the pulse generation counter 10.

  The synchronization signal generating means 20 can be configured using a known circuit. For example, the first cycle value setting register 21 and the second cycle value setting register 22 can be configured using a memory. The synchronization signal generation comparator 23 can be configured using a digital comparator.

Next, the pulse generation means 30 will be described below.
As shown in FIG. 2, the pulse generation means 30 includes a first front end timing value setting register 31, a second front end timing value setting register 32, a front end timing generation comparator 33, and a first rear end timing value setting. It comprises a register 34, a second rear end timing value setting register 35, a rear end timing generation comparator 36, and an output pulse generation means 37.

  The first front end timing value setting register 31 stores the front end timing value Tf of the output pulse signal So. This front end timing value Tf is set in the first front end timing value setting register 31 by the control means 50 described later. The first front end timing value setting register 31 outputs the set front end timing value Tf to the second front end timing value setting register 32.

  The second front end timing value setting register 32 stores a front end timing value Tf output from the first front end timing value setting register 31 when an update signal S2 generated by an update signal generating unit 40 described later is input. The second front end timing value setting register 32 outputs the set front end timing value Tf to the front end timing generation comparator 33.

  The front end timing generation comparator 33 inputs the count value Cp output from the pulse generation counter 10 to one input unit. Further, the front end timing value Tf output from the second front end timing value setting register 32 is input to the other input unit.

  The front end timing generation comparator 33 compares the input count value Cp with the front end timing value Tf set in the second front end timing value setting register 32, and whether the count value Cp matches the front end timing value Tf. Alternatively, if it is larger than the front end timing value Tf, a signal for raising the output pulse signal at the front end timing is output to the output pulse generating means 37.

  Each of the first rear end timing value setting register 34 and the second rear end timing value setting register 35 stores the rear end timing value Tb of the output pulse signal So, and the first front end timing value described above. The configuration is the same as the setting register 31 or the second front end timing value setting register 32.

  The rear end timing generation comparator 36 is configured in the same manner as the front end timing generation comparator 33 described above except that a signal that causes the output pulse signal to fall at the rear end timing is output to the output pulse generation unit 37. .

  The output pulse generation means 37 receives the signal for raising the output pulse signal at the front end timing and the signal for lowering the output pulse signal at the rear end timing, generates the output pulse signal So, and outputs it to the load circuit 200. .

  In the pulse generator 30 of the pulse generator 100 of the present embodiment, as described above, from the first period value setting register 21, the first front end timing value setting register 31, and the first rear end timing value setting register 34, And a second register group including a second period value setting register 22, a second front end timing value setting register 32, and a second rear end timing value setting register 35.

  Then, the pulse generation means 30 receives the update signal S2 for changing the pulse generation condition of the output pulse signal So, and only the data stored in the first register group for the first time is the data in the second register group. Is updated to generate the output pulse signal So.

  The pulse generation means 30 can be configured using a known circuit. For example, each register 22 can be configured using a memory. Each comparator can be configured using a digital comparator.

  Next, the control means 50 will be described below.

Control means 50 inputs a frequency divider 5 1 to divide by inputting a predetermined periodic pulse signal generator 60 outputs a pulse signal divider 5 1 obtained by dividing the frequency output, and the divider pulse Second count means 52 (hereinafter also referred to as an inhibit counter 52) that outputs a count value Ci obtained by counting the signal, and an update control signal that will be described later with a set update control time value Ti (hereinafter also referred to as an inhibit time value Ti). An update control time setting register 54 (hereinafter also referred to as an inhibit time value setting register 54) output to the generation means 53 and a count value Ci are input to one input unit, and an inhibit time value Ti is input to the other input unit. When the count value Ci is greater than the inhibit time value Ti, the update control signal S1 (hereinafter also referred to as the inhibit signal S1) is output. An update control signal generating means 53, a display unit 56 for displaying the pulse generation conditions, the CPU55 for controlling the above components, in constructed.

  Hereinafter, each component of the control means 50 is demonstrated.

  The frequency divider 51 receives a predetermined period pulse signal that is a reference clock output from the oscillator 60, and outputs the divided pulse signal to the inhibit counter 52. The frequency division ratio of the frequency divider 51 is preferably set as appropriate based on the value of the inhibit time value Ti or the like. From this viewpoint, it is preferable to use a programmable frequency divider as the frequency divider 51.

  The inhibit counter 52 receives and counts the pulse signal output from the oscillator 60 via the frequency divider 51, and the count value Ci is cleared by the input of the synchronization signal Sy. The inhibit counter 52 outputs the count value Ci to one input unit of the update control signal generation unit 53.

  The inhibit counter 52 counts the pulse signal only when the inhibit signal S1 output from the update control signal generation means 53 is input (when the inhibit signal Si is in the H state), and does not input the inhibit signal S1 ( When the inhibit signal Si is L), the count is stopped and the count value Ci at that time is held.

  The inhibit counter 52 is preferably a synchronous counter. In this embodiment, a synchronous up counter is used. The synchronization signal Sy output from the pulse generation counter 10 can be input to, for example, the clear (CL) terminal of the inhibit counter circuit. The inhibit signal S1 output from the update control signal generating means 53 can be input to the negative enable (* EN) terminal of the inhibit counter circuit.

  The inhibit time value setting register 54 stores the inhibit time value Ti and outputs the set inhibit time value Ti to the other input section of the update control signal generating means 53. The inhibit time value setting register 54 is set with the inhibit time value Ti by the CPU 55.

  The inhibit time value Ti is preferably larger than the cycle value Th, and is preferably smaller than the time during which the user can wait until the update is completed after instructing the CPU 55 to update the pulse generation condition. That is, when the frequency of the synchronization signal Sy is several MHz or more, the inhibit time value Ti may be a time value that is sufficiently short that it cannot be distinguished by the user's sense.

  The update control signal generation means 53 outputs the inhibit signal S1 to the update signal generation means 40 and the inhibit counter 52 when the count value Ci is larger than the inhibit time value Ti. The update control signal generation unit 53 can be configured using, for example, a digital comparator.

The number of bits included in the inhibit counter 52, the minute and divider 5 1 division ratio is preferably determined based on the relationship between the maximum generation period value capable of generating a pulse generating counter 10. For example, the pulse generation counter 10 can generate up to a maximum cycle value of 1000 seconds. Also, the frequency division ratio of the frequency divider 5 1 and 1,000,000, the oscillation frequency of the oscillator 60 and 100 MHz. In this case, if the inhibit time value Ti is selected as 10, the inhibit counter 52 counts up to 0.1 second, so this inhibit time value is a time value that is sufficiently short that it cannot be discerned by the user. After the user instructs the CPU 55 to update the pulse generation condition, it is sufficiently shorter than the time that the user can wait until the update is completed.

Usually, since the cycle value Th of the synchronization signal Sy is at most 10 ⁻³ seconds, the inhibit time value Ti corresponding to 0.1 seconds is larger than the cycle value of the synchronization signal Sy. In this case, since the inhibit counter 52 inputs the synchronization signal Sy at a period of 10 ⁻³ seconds at the longest, the count value Ci is always cleared before counting up to 0.1 seconds, so the update control signal The generation means 53 does not output the inhibit signal S1.

  The CPU 55 controls each component of the control unit 50. Further, the CPU 55 generates an update command signal S3 in response to a request from the user or the like, and outputs it to the update signal generating means 40.

  Further, the CPU 55 of this embodiment controls the synchronization signal generation unit 20 and the pulse generation unit 30. When the CPU 55 outputs the update command signal S3, first, after outputting the parameters of the pulse generation conditions to the synchronization signal generation means 20 and the pulse generation means 30, the update command signal S3 is generated and the update signal generation means Output to 40.

  Further, the control means 50 has a display unit 56. The display unit 56 displays processing states of the control means 50 and the pulse generator 100, such as parameters of pulse generation conditions. The parameters of the pulse generation condition include a cycle value Th, a delay time value Tr, a pulse width Pw, a front end timing value Tf, a rear end timing value Tb, and the like. The delay time value Tr and the pulse width Pw can also be set using the front end timing value Tf or the rear end timing value Tb.

  In this embodiment, after the user instructs the CPU to change the parameters of the pulse generation conditions, the pulse generation conditions are being updated on the display unit 56 until the change of the parameters is completed. Is displayed.

  Specifically, the CPU 55 outputs the update command S3 to the update signal generation means 40, and then pulses the display unit 56 while the update signal generation means 40 generates the update history signal S4 and outputs it to the CPU 55. Displays that the generation condition is being updated. That is, when the update history signal S4 is no longer input from the update signal generating means 40, the CPU 55 determines that the update of the pulse generation condition has been completed. Alternatively, the update signal S2 output from the update signal generation circuit 40 may be input to the CPU 55 as an interrupt signal, and this interrupt signal may be used to cause the CPU 55 to recognize that the update of the pulse generation condition has been completed.

  Examples of the display indicating that the pulse generation condition is being updated include changing the background color of a parameter or displaying an icon.

Next, the update signal generating means 40 will be further described below.
When the update command generator 40 receives the update command signal S3 from the CPU 55 and does not receive the inhibit signal S1 from the update control signal generator 53, the update signal generator 40 updates until the next input synchronization signal Sy is received. The generation of the signal S1 is suspended, and the update signal S2 is generated in synchronization with the synchronization signal Sy of the next input.

  The update signal generating means 40 has an update signal setting register (not shown), and when the update command S3 is input, the setting of the update signal setting register is set to a high (H) state. Then, after generating the update signal S2, the setting of the update signal setting register is changed to a low (L) state. That is, the update signal generator 40 is allowed to input the update command signal S3 output from the CPU 55 only after the update signal generator 40 generates the update signal S2.

  Further, the update signal generation means 40 generates the update history signal S4 and outputs it to the CPU 55 when the setting of the update signal setting register is in the high (H) state (the update history signal S4 is in the H state). The update signal generating means 40 does not output the update history signal S4 to the CPU 55 when the setting of the update signal setting register is in the low (L) state (the update history signal S4 is in the L state).

  On the other hand, when the update command signal S3 from the CPU 55 is input, the update signal generation means 40 immediately generates the update signal S2 if the inhibit signal S1 from the update control signal generation means 53 is input.

  As described above, the update control signal generation unit 53 of the control unit 50 determines that the count value Ci of the inhibit counter 52 is greater than the inhibit time value Ti from the input of the update command signal S3 to the input of the next synchronization signal Sy. Inhibit signal S1 is output. Therefore, when the inhibit time value Ti is output, the control means 50 allows the update signal generating means 40 to input the update command signal S3 and immediately generates the update signal S2. That is, the update signal generating means 40 does not wait for the next input synchronization signal Sy.

  Next, an example of the operation of the above-described pulse generator 100 of the present embodiment will be described below with reference to the timing chart shown in FIG.

  In FIG. 3, (a) shows the synchronization signal Sy, (b) shows the update command signal S3, (c) shows the update history signal S4, and (d) shows the count value of the inhibit counter 52. Ci indicates (e) indicates the inhibit signal S1, and (f) indicates the update signal S2. Further, (d) also shows an inhibit time value Ti.

(1) When the cycle value Th of the synchronization signal Sy is smaller than the inhibit time value Ti In the left part of (d), the cycle value Th of the synchronization signal Sy is smaller than the inhibit time value Ti. Before the value Ci exceeds the inhibit time value Ti, the count value Ci is cleared by the synchronization signal Sy. Therefore, as shown in (e), the inhibit signal S1 is not output.

  Here, as shown in (b), when the CPU 55 outputs the update command signal S3 at time t1, as shown in (c), the update signal generating means 40 outputs the update history signal S4, and (f) As shown in FIG. 4, after the update signal S2 is suspended until the next input synchronization signal Sy is received, the update signal S2 is generated in synchronization with the next input synchronization signal Sy at time t2. Then, as shown in (c), the update signal generator 40 stops outputting the update history signal S4. Further, as shown in (d), the count value Ci of the inhibit counter 52 is cleared in synchronization with the synchronization signal Sy.

(2) When the cycle value Th of the synchronization signal Sy is greater than the inhibit time value Ti In the right part of (d), the cycle value Th of the synchronization signal Sy is greater than the inhibit time value Ti, so After the count value Ci of the counter 52 exceeds the inhibit time value Ti, the inhibit counter 52 stops counting the pulse signal, and then the count value Ci is held at a constant value. Then, as shown in (e), the update control signal generation means 53 outputs the inhibit signal S1 at time t4.

  Here, as shown in (b), when the CPU 55 has already generated the update command signal S3 at time t3 past the time T4, as shown in (c), the update signal generating means 40 After the update history signal S4 is output, the generation of the update signal S2 is suspended as shown in (f) until the next input synchronization signal Sy is received or the inhibit signal S1 is output.

  Then, as shown in (e), when the update control signal generating means 53 outputs the inhibit signal S1 at time t4, as shown in (f), the update signal generating means 40 waits for the synchronization signal Sy. Instead, the update signal S2 is generated immediately. Then, as shown in (c), the update signal generator 40 stops outputting the update history signal S4. On the other hand, as shown in (d), the count value Ci of the inhibit counter 52 continues to hold a constant value thereafter, and is cleared in synchronization with the synchronization signal Sy of the next input. Then, as shown in (e), the update control signal generation means 53 stops outputting the inhibit signal S1.

  As shown in (b), when the CPU 55 outputs the update command signal S3 at time t5 after time t4, as shown in (c), the update signal generating means 40 While outputting S4, as shown in (f), the update signal S2 is generated immediately.

Next, an example of the operation of this embodiment will be described below with reference to the state transition diagram shown in FIG.
The pulse generator 100 of the present embodiment has the following four states.
(1) “State 0 (zero)”: a state in which the pulse generation counter 10 has stopped counting the pulse signal and has not generated the output pulse signal So.
(2) “State 1”: a state in which the output pulse signal So is being generated but the parameters of the pulse generation conditions are not updated.
(3) “State 2”: State in which the output pulse signal So is being generated and the pulse generation condition parameter is being updated, but before the count value Ci has passed the inhibit time value Ti.
(4) “State 3”: State after the output pulse signal So is being generated and the count value Ci has passed the inhibit time value Ti.

(1) State 0 (zero)
Since the pulse generator 100 does not receive an external command signal Se (Se = L), the pulse generation counter 10 stops counting and does not generate the output pulse signal So. When the pulse generator 100 receives the command signal Se (Se = H), the state transitions from the state 0 to the state 1.

(2) State 1
When the pulse generator 100 transitions from the state 0 to the state 1, the pulse generation counter 10 starts counting and generates the output pulse signal So. In the state 1, even if the synchronization signal Sy is generated, the state counter does not change and the inhibit counter 52 is only cleared. In the state 1, when the CPU 55 generates the update command signal S3, the pulse generator 100 generates the update history signal S4 (S4 = H) and transitions from the state 1 to the state 2. In addition, the pulse generator 100 displays a display in which the parameter of the pulse generation condition is being updated on the display unit 56.

  On the other hand, when the count value Ci exceeds the inhibit time value Ti in the state 1, the update control signal generation unit 53 outputs the inhibit signal S1 (S1 = H), and the pulse generator 100 changes from the state 1 to the state 3 Transition.

  In state 2, when the synchronization signal Sy is generated, in the pulse generator 100, the update signal generator 40 generates the update signal S2 and updates the parameters of the pulse generation condition. After completing the parameter update, the pulse generation device 100 stops the output of the update history signal S4 (S4 = L) and returns the display during the update of the display unit 56 to the original state. Transition to. In state 2, even if the CPU 55 repeatedly generates an update command signal, the state of the pulse generator 100 does not transition.

  In state 2, if the count value Ci exceeds the inhibit time value Ti before the synchronization signal Sy is generated, the pulse generator 100 performs the following processing and then changes from state 2 to state 3. Transition. When the count value Ci exceeds the inhibit time value Ti, the pulse generator 100 first generates the inhibit signal S1 (S1 = H) and also generates the update signal S2 and updates the parameters of the pulse generation condition Thereafter, the output of the update history signal S4 is stopped (S4 = L), and the display during update on the display unit 56 is restored. In state 2, when the synchronization signal Sy and the inhibit signal S1 are generated at the same time, the pulse generator 100 generates the update signal S2 and updates the parameter of the pulse generation condition.

  In the state 3, when the CPU 55 generates the update command signal S3, the pulse generator 100 performs the following process without performing a state transition. When the CPU 55 generates the update command signal S3, the pulse generator 100 generates the update history signal S4 (S4 = H) without waiting for the generation of the next input synchronization signal Sy, and causes the display unit 56 to generate a pulse generation condition. Is updated, the update signal S2 is generated, the parameter of the pulse generation condition is updated, the output of the update history signal S4 is stopped (S4 = L), and the display unit 56 is updated. Restore the display inside.

In state 3, when the synchronization signal Sy is generated, the pulse generator 100 clears the count value Ci of the inhibit counter 52 and stops outputting the inhibit signal S1 (S1 = L). Further, when the generation of the synchronization signal Sy and the update command signal S3 are generated at the same time, the pulse generator 100 generates the update signal S2 at the same time as the transition from the state 3 to the state 1, and the parameter of the pulse generation condition Update.
Note that the pulse generator 100 does not transition from the state 3 to the state 2.

  In any state, when the command signal Se from the outside of the device is no longer input (Se = L), the pulse generator 100 stops generating the output pulse signal So and transitions to the state 0. However, if the parameter is being updated in the state 2, the update signal S2 is generated and the display unit 56 displays that the parameter is being updated. Also, in the state 3, when the generation of the update command signal S3 and the change of the command signal Se from H to L occur at the same time, the update signal S2 is generated simultaneously with the transition from the state 3 to the state 0. At the same time, the display unit 56 displays that is being updated.

  Next, the operation of the display unit 56 of the pulse generator 100 of the present embodiment will be described below with reference to FIGS. Here, a case where the display unit 56 is a CRT will be described. FIG. 5 is a flowchart for explaining the operation of the display unit 56 of the pulse generator 100. FIG. 6 is a diagram illustrating the display on the display unit 56 of the pulse generator 100.

  First, in step S101 in FIG. 5, the user operates the operation input unit of the pulse generator 100 to update the front end timing value Tf in order to change the parameter of the pulse generation condition.

  Next, in step S102, the CPU 55 generates a change command signal S3 and outputs it to the update signal generating means 40. The update signal generation means 40 generates an update history signal S4 and outputs it to the CPU 55.

  Next, in step S <b> 103, the CPU 55 displays on the display unit 56 that the parameters for the pulse generation conditions are being updated. Specifically, the CPU 55 can change the background color of the parameter of the pulse generation condition displayed on the display unit 56 or display an icon.

  Next, in step S104, the CPU 55 determines whether or not the update history signal S4 is input from the update signal generator 40. If the update history signal S4 is input from the update signal generating means 40, the process returns to S104. On the other hand, if the update history signal S4 has not been input from the update signal generating means 40, the CPU 55 determines that the update of the parameter of the pulse generation condition has been completed, and proceeds to step S105.

Next, in step S105, the CPU 55 restores the display on the display unit 56.
This completes the operation of the display unit 56 of the pulse generator 100 indicating that the pulse generation condition is being changed.

  Next, an example displayed on the display unit 56 in step S103 of FIG. 5 will be described below with reference to FIG.

  Fig.6 (a) shows the display of the display part 56 in the state before changing pulse generation conditions. The display unit 56 displays a cycle value Th, a delay time value Tr, and a pulse width Pw.

  Next, FIG.6 (b) shows the display of the display part 56 of the state which is changing the pulse generation conditions. In the example of FIG. 5, since only the front end timing value Tf is changed, the delay time value Tr is being changed from 20.000 ms before the change to 60.000 ms, and the background color of this delay time value is changed. And an icon 57 is displayed.

  Next, FIG.6 (c) shows the display of the display part 56 of the state which the change of pulse generation conditions was completed. The delay time value Tr is updated from 20.000 ms before the change to 60.000 ms. Also, the icon disappears.

  According to the pulse generator 300 of this embodiment described above, even when the output pulse signal So is generated and stopped based on the command signal Se from the outside of the apparatus, the pulse generation conditions can be changed seamlessly. Specifically, when the cycle value Th of the synchronization signal Sy is smaller than the inhibit time value Ti, the pulse generation condition is updated in synchronization with the synchronization signal Sy of the next input after the generation of the change command signal S3. Does not generate unnecessary pulses. When the period value Th of the synchronization signal Sy is larger than the inhibit time value Ti, the pulse generation condition is updated simultaneously with the generation of the change command signal S3. Therefore, even when a relatively long cycle value is set, the pulse generation conditions are updated quickly, so that the operability is excellent.

  In addition, during the update of the pulse generation condition, the display unit 56 displays that the update is in progress, so that the user can clearly recognize that the pulse generation device 100 is in the state of updating the pulse generation condition. For example, in the pulse generator 100, when the user changes the parameter of the pulse generation condition in the state where the inhibit time value Ti is set to a relatively long time in order to handle a relatively long cycle value Th, the change is made. However, it takes a considerable amount of time to complete, but the display of updating is made on the display unit 56, so that the user can grasp the update state.

  Next, another example according to the embodiment of the present invention will be described below with reference to FIG. For points that are not particularly described, the description in detail regarding the above-described embodiments is applied as appropriate. Moreover, in FIG. 7, the same code | symbol is attached | subjected to the same component as FIGS.

  In the pulse generator 100 of this embodiment, as shown in FIG. 7, the control means 50 includes a logic means 70 that outputs a logical sum of the update signal S2 ′ and the forced update signal S5. When the cycle value Th is smaller than the set inhibit time value Ti, the control unit 50 generates the update signal S2 in synchronization with the synchronization signal Sy of the next input, and when the cycle value Th is greater than the inhibit time value Ti. The update signal S2 is updated based on the forced update signal S5.

  In this embodiment, a command signal Si to the pulse generation counter 10 is output from the CPU 55 inside the pulse generator 100. In this embodiment, since the CPU 55 knows the generation state of the output pulse signal So, only the CPU 55 generates an update command signal S3 that updates the pulse generation condition in synchronization with the synchronization signal Sy. The signal S3 can be output to the update signal generator 40. For this reason, this embodiment does not include the inhibit counter, the inhibit time value setting register, the update control signal generation means, and the frequency divider that the above-described embodiments have. That is, the control means 50 is constituted by the CPU 55.

  In this embodiment, a logic means 70 is provided. In the logic means 70, the update signal S2 ′ output from the update signal generating means 40 is input to one input section, and the forced update signal S5 output from the CPU 55 is input to the other input section. The logic means 70 outputs the result of the logical sum of the update signal S2 ′ and the forced update signal S5 to the synchronization signal generation means 20 and the pulse generation means 30 as the update signal S2.

  When the period value Th is smaller than the inhibit time value Ti, the CPU 55 generates only the update command signal S3. In this case, the update signal generation means 40 having received the update command signal S3 generates the update signal S2 ′ in synchronization with the next input synchronization signal sy and outputs it to the logic means 70.

  On the other hand, when the cycle value Th is larger than the inhibit time value Ti, the CPU 55 generates a forced update signal S5 and outputs it to the logic means 70.

  Therefore, the logic means 70 that has received the update signal S2 ′ or the forced update signal S5 immediately generates the update signal S2, so that the pulse generation conditions are updated quickly.

  Other configurations are the same as those in the above-described embodiment.

  According to the pulse generator 100 of this embodiment described above, the command signal Si to the pulse generator counter 10 is output from the control means 50 inside the pulse generator 100, so that the control means 50 can be configured easily. Manufacturing costs are reduced. In addition, the pulse generation conditions can be changed seamlessly.

  The pulse generator of the present invention is not limited to the above-described embodiments or examples, and can be appropriately changed without departing from the spirit of the present invention.

  For example, in the above-described embodiment or example, the first counter unit is an up counter, but may be a down counter. In this case, if the synchronization signal is generated and output when the count value becomes zero, the synchronization signal generation means can be configured without providing the synchronization signal generation comparator.

It is a block diagram which shows one Embodiment of the pulse generator which concerns on this invention. It is a block diagram which shows one Example of the pulse generator of FIG. FIG. 3 is a timing chart for explaining the operation of the pulse generator of FIG. It is a state transition diagram explaining operation | movement of the pulse generator of FIG. It is a flowchart explaining operation | movement of the display part of the pulse generator of FIG. It is a figure explaining the example of a display of the display part of the pulse generator of FIG. It is a block diagram which shows the other Example of this invention. It is a block diagram which shows the pulse generator by a prior art example. FIG. 9 is a timing chart for explaining an output pulse signal generated by the pulse generator shown in FIG. 8. It is a timing diagram explaining the case where the pulse generator shown in FIG. 8 changed the pulse generation conditions.

Explanation of symbols

100 Pulse generator 10 First count means (pulse generation counter)
20 synchronization signal generating means 21 first period value setting register 22 second period value setting register 23 synchronization signal generating comparator 30 pulse generating means 31 first front end timing value setting register 32 second front end timing value setting register 33 front end Timing generation comparator 34 First rear end timing value setting register 35 Second rear end timing value setting register 36 Rear end timing generation comparator 37 Output pulse generation means 40 Update signal generation means 50 Control means 51 Frequency divider 52 Second Count means (inhibit counter)
53 Update control signal generation means 54 Inhibit time value setting register 55 CPU
56 Display Unit 60 Oscillator 70 Logic Means (OR Logic Circuit)
200 Load circuit Se External command signal Si Internal command signal Sy Synchronization signal So Output pulse signal S1 Inhibit signal S2 Update signal S3 Update command signal S4 Update history signal S5 Forced update command signal Cp Count value of first count means (pulse generation counter) Ci Count value of second counting means (inhibit counter) Ti Update control time value (inhibit time) value Th Period value Tf Front end timing value Tb Rear end timing value

Claims (6)

First counting means for counting the number of pulses of the predetermined frequency pulse signal;
Synchronization signal generating means for clearing the first counting means based on the count value of the first counting means and the set cycle value, and causing the first counting means to generate a synchronization signal in the cycle;
Pulse generation means for generating an output pulse signal having a pulse generation condition determined based on the count value and the set front end and rear end timing values for each cycle;
Update signal generating means for generating an update signal for updating the pulse generation condition of the output pulse signal based on an input of an update command signal;
Control means for controlling the update signal generating means,
The control means counts the predetermined frequency pulse signal and is cleared by the input of the synchronization signal, and the second count means from the input of the update command signal to the input of the next synchronization signal Update control signal generation means for outputting an update control signal when the count value is greater than the update control time value, and permits the input of the update command signal when the update control signal is output Then, the update signal generating means causes the update signal to be generated . The control means includes
A second counting means for counting the predetermined frequency pulse signal and being cleared by the input of the synchronization signal;
Update control signal generation means for outputting an update control signal when the count value of the second count means is greater than the update control time value between the input of the update command signal and the input of the next synchronization signal. And
2. The pulse generation device according to claim 1, wherein when the update control signal is output, the update command signal is allowed to be input and the update signal generation means generates the update signal.   3. The pulse generator according to claim 2, wherein the first counting means is controlled to start or stop counting the number of pulses by a command signal, and the command signal is supplied from outside the device.   4. The pulse generation device according to claim 2, wherein the second counting unit counts a pulse signal obtained by dividing the predetermined frequency pulse signal. 5. The pulse generation means includes
First period value setting means for storing the period value; first front end timing value setting means for storing the front end timing value; and first rear end timing value setting means for storing the rear end timing value; ,
Second period value setting means for receiving the update signal and storing the period value stored in the first period value setting means; and front end timing stored in the first front end timing value setting means Second front end timing value setting means for storing a value, and second rear end timing value setting means for storing a rear end timing value stored in the first rear end timing value setting means. And
The period value stored in the second period value setting means, the front end timing value stored in the second front end timing value setting means, and the rear end timing value stored in the second rear end timing value setting means pulse generator according to claim 1, any one of 4 and generates an output pulse signal having a pulse generation condition determined based on and. The update signal generation means generates an update history signal from the time when the update command signal is input until the pulse generation condition is updated,
Wherein while the update history signal occurs, the pulse according to any one of claims 1 5, characterized in that the pulse generating condition and a display unit for displaying that the updating Generator.

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