JP2000101347A - Oscillation control circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an oscillation control circuit, where the waiting time for stable oscillation of an oscillation circuit is shortened when a standby mode is released in a microcomputer having oscillation circuits with different oscillation frequencies, in which these circuits are used by switching. SOLUTION: This oscillation control circuit is provided with an oscillation circuit 1 that generates a clock in the usual operating mode, an oscillation circuit 2 that generates a clock in the standby mode, a selector 4 that selects a clock signal CLK1 or CLK2 and outputs the selected clock signal, a clock control circuit 3 that controls the selection of the selector 4 to control operation start/stop of the oscillation circuit 1, an edge detection circuit 5 that detects the edge of the clock signal CLK2 generated by the oscillation circuit 2 just after oscillation of the oscillation circuit 1 is restarted, a transfer gate 6, and a capacitor 7. The trailing edge of the clock signal CLK2, given to the oscillation circuit 1 just after the oscillation of the oscillation circuit 1, is restarted gives an opportunity for oscillation through the action of capacitive coupling in an oscillation transient state of the oscillation circuit 1 so as to give on opportunity to promote growth of oscillation.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an oscillation control circuit, and more particularly to an oscillation control circuit for a microcomputer provided with a plurality of oscillation circuits having different oscillation frequencies to reduce the oscillation stabilization wait time when switching between oscillation circuits.

[0002]

2. Description of the Related Art A microcomputer having a power saving mode (standby mode) is provided with two oscillating circuits having different frequencies, and switches to a clock signal from an oscillating circuit having a lower frequency than in a normal operation in a standby mode. After the standby mode is released,
2. Description of the Related Art There is known an oscillation control that is driven by a clock from an oscillation circuit for normal operation. In this case, when the standby mode is released, the clock of the normal operation frequency cannot be supplied to the CPU until the oscillation circuit of the normal operation frequency stably oscillates after the start of the oscillation.

As an oscillation circuit for shortening the oscillation stabilization wait time from the start of oscillation to stable oscillation, increasing the gain of the inverter of the oscillation circuit accelerates oscillation growth and shortens the oscillation wait time. Conventionally, a method of achieving the above has been generally used.

However, there is a problem that increasing the gain of the inverter increases power consumption.

[0005]

In order to solve this problem, for example, Japanese Unexamined Patent Application Publication No. 9-93040 discloses that a self-excited oscillation circuit is provided as an auxiliary to a crystal oscillation circuit. There has been proposed an oscillation control circuit that supplies a clock to accelerate oscillation and shorten the oscillation stabilization wait time.

As shown in FIG. 5, a clock generated from the self-excited oscillation circuit 53 is applied to the crystal oscillation circuit 52 from the start of the oscillation until the average oscillation stabilization time of the crystal oscillator 64 is counted. The crystal oscillation circuit 52 continues to be supplied.
Promotes oscillation.

However, when applying to a circuit having an oscillation circuit of a different frequency, supplying a continuous clock from the auxiliary oscillation circuit at the start of oscillation is not necessarily to promote the oscillation of the oscillation circuit. No.

For example, as shown at time A in FIG. 6, when the oscillation circuit of a high frequency changes from low to high and the oscillation circuit of a low frequency changes from high to low, the effect of preventing the oscillation growth is obtained. Occurs.

Further, a timer (1) 55 for counting and outputting a clock generated in the crystal oscillation circuit 52.
And a timer (2) 56 for counting and outputting a clock generated in the self-excited oscillation circuit 53, and a determination circuit 60 for determining whether the oscillation operation of the crystal oscillation circuit 52 is stabilized.
However, there is also a problem that the circuit scale becomes large.

Therefore, the present invention has been made in view of the above-mentioned problems, and an object of the present invention is to provide a microcomputer having oscillation circuits of different oscillation frequencies, which can be used by switching between them, with a simple configuration. CPU
An oscillation control circuit for shortening the oscillation stabilization wait time of the oscillation circuit when the standby mode is released.

[0011]

An oscillation control circuit according to the present invention for achieving the above object has first and second oscillation circuits having different oscillation frequencies.
A second oscillating circuit, wherein when the first oscillating circuit stops oscillating and the second oscillating circuit is in an oscillating state, the second oscillating circuit receives the oscillation start signal of the first oscillating circuit, One transition edge of a rising or falling signal of an oscillation output signal from the circuit is supplied to the first oscillation circuit by capacitive coupling via a capacitor, and the first oscillation circuit in a transient state triggers oscillation. To promote oscillation growth.

Further, the present invention includes first and second oscillation circuits having different oscillation frequencies from each other, wherein the first oscillation circuit stops oscillating and the first oscillation circuit oscillates when the second oscillation circuit is in an oscillation state. Receiving the oscillation start signal of the oscillation circuit, outputs the oscillation output from the second oscillation circuit and outputs a control signal including the rising edge of the oscillation output or one of the rising edge transition timings during the active period. An edge detection means, wherein an output of the second oscillation circuit is connected to an input terminal of the first oscillation circuit via a capacitor and a first switch, and receives a control signal output by the edge detection means The first switch is turned on, and during that time, one of the rising and falling edges of the oscillation output from the second oscillation circuit is caused by capacitive coupling via the capacitor. Serial supplied to the first oscillator circuit may be configured so as to facilitate the oscillation growth gives an opportunity of oscillation in said first oscillation circuit in a transient state.

[0013]

Embodiments of the present invention will be described. The present invention provides an oscillation circuit in a microcomputer including two oscillation circuits having different frequencies and switching between clocks generated from the two oscillation circuits in accordance with an operation mode (normal operation mode and standby mode) of a CPU. A circuit for promoting the oscillation growth when the CPU returns from the standby mode to the normal operation mode and the relatively high-frequency oscillation circuit stopped during the standby mode resumes the oscillation. It is a thing.

In the preferred embodiment of the present invention, referring to FIG. 1, a first clock (CLK1) in a normal operation mode is generated, oscillation is stopped in a standby mode, and the standby mode is released to release a normal clock. A first oscillation circuit (1) that resumes oscillation when the operation mode returns, and a second oscillation circuit (2) that generates a second clock (CLK2) lower in frequency than the first clock in the standby mode. A selector (4) for switching the first and second clock signals from the first and second oscillation circuits (2) by an input switching control signal and supplying the same to the CPU (10);
And a clock that outputs a switching control signal to the selector (4) in response to the standby mode release notification signal from the CPU (10) and outputs an oscillation start signal instructing the first oscillation circuit (1) to start oscillation. The control circuit (3) and the second clock from the second oscillation circuit (2) are inputted, and the CPU
Upon receiving the standby release notification signal from (10),
An edge detection circuit that detects a rising edge or one edge of a rising edge of a second clock and outputs a control signal (S2), wherein the control signal (S2) is provided in an on-period (active period). An edge detection circuit (5) for outputting a pulse signal including one of the rising edge or the rising edge of the clock of the second clock; the output terminal of the second oscillation circuit (2) and the output terminal of the first oscillation circuit (1); A transfer gate (6) and a capacitor (7) are connected in series between the input terminal and the input terminal, and a control terminal of the transfer gate (6) has a control signal ( S2) is input, and when the standby mode is released, the second transfer gate (6) is turned on by receiving the control signal output from the edge detection circuit (5). One edge of the rise or fall of the second clock from Fukairo (2),
Supplied to the input terminal of the first oscillation circuit (1) by capacitive coupling via the capacitor (7), the first oscillation circuit (1) in a transient state is triggered to oscillate to promote oscillation growth.

According to another embodiment of the present invention, referring to FIG. 3, a circuit between an oscillation start signal output terminal of a clock control circuit (3) and an input terminal of a first oscillation circuit (1) is provided. A delay circuit (12), a transfer gate (6), and a capacitor (7) connected in series to the control gate of the transfer gate (6). A pulse signal output from the edge detection circuit (5) is supplied to a control terminal of the transfer gate (6). The transfer gate (6) which is inputted and turned on in response to a pulse signal output from the edge detection circuit (5) when the standby mode is released.
From the clock control circuit (3) via the oscillation start signal (S
One of the rising edge and the falling edge obtained by delaying 1) by the delay circuit (12) is supplied to the first oscillation circuit (1) by capacitive coupling via the capacitor (7), and the first oscillation circuit is in a transient state. The first oscillation circuit (1) is stimulated to oscillate to promote oscillation growth.

Referring to FIG. 1, when the CPU (10) is in the normal operation mode, a relatively high-frequency oscillation circuit (1) for generating a clock signal CLK1 to be supplied to the CPU (10); A relatively low frequency oscillation circuit (2) for generating a clock signal CLK2 to be supplied to peripheral circuits when the device is in a standby mode;
And a clock control circuit (3) for controlling the switching of the clock signal CLK2 and controlling the start / stop of the operation of the oscillation circuit (1), and a clock control circuit (3) which receives the clock signal CLK1 and the clock signal CLK2 and receives the clock signal CLK1 and the clock signal CLK2. And a selector (4) for selecting one of them according to the switching control signal and outputting the selected clock to the CPU as a clock CLK, and further comprising a clock generated by the oscillation circuit (2) when the oscillation of the oscillation circuit (1) is restarted. An edge detection circuit (5) for detecting one of a falling edge and a rising edge of the signal CLK2, a transfer gate (6), and a capacitor (7) are provided. Oscillation circuit (1)
The falling edge (or the rising edge) of the clock signal CLK2 applied to the oscillation circuit (1) immediately after the oscillation restarts due to the action of the capacitive coupling in the oscillation transient state of the oscillation circuit (1). To promote oscillation growth. Therefore, the oscillation stabilization wait time of the oscillation circuit (1) when the CPU switches from the standby mode to the normal operation mode can be reduced, and the operation of the microcomputer can be started earlier. Hereinafter, description will be made in accordance with embodiments.

[0017]

FIG. 1 is a block diagram showing a configuration of an oscillation control circuit according to an embodiment of the present invention. Referring to FIG.
An oscillating circuit 1 for generating a clock signal CLK1 for the CPU, an oscillating circuit 2 for generating a clock signal CLK2 to be supplied to peripheral circuits during standby of the CPU, switching between the clock signal CLK1 and the clock signal CLK2, and starting / stopping operation of the oscillating circuit 1 A clock control circuit 3 for controlling the clock signal, a clock selector 4, and an edge detection circuit 5 for detecting the falling edge (or rising edge) of the clock signal CLK2 generated by the oscillation circuit 2 when the oscillation circuit 1 starts oscillating. , An X1 terminal of the oscillation circuit 1, and an N-channel transfer gate 6 and a capacitor 7 which are inserted in series between the output terminals of the oscillation circuit 2.

FIG. 4 is a diagram showing an example of the configuration of the oscillation circuit 1 shown in FIG. Referring to FIG. 4, the transmission circuit 1
The input and the output are respectively connected between X1 and X2 terminals connected to both ends of the crystal unit 8, and the stop signal S1
A tri-state type inverter circuit 21 for inputting a signal obtained by inverting the output signal from the inverter circuit 23 as an output enable signal to a control terminal, a feedback resistor 22 and an N-channel transfer gate 2 connected in series between terminals X1 and X2.
4, an N-channel transfer gate 25 for controlling on / off connection of the output of the tri-state type inverter circuit 21 to the power supply VDD, and the clock signal C
Inverter circuit 2 for waveform shaping output as LK1
6, a signal obtained by inverting the stop signal S1 by the inverter circuit 23 is input to the gate of the N-channel transfer gate 24.
The switch signal S1 is input to the gate of No. 5.

When the stop signal S1 is at a low level, N
A tri-state inverter in which the channel transfer gate 25 is turned off and an inverted signal of the stop signal S1 is input to the gate, and the N-channel transfer gate 24 is turned on and an inverted signal of the stop signal S1 is input to the control terminal. The circuit 21 is in an output enable state, and has a configuration in which an inverter circuit 21 and a feedback resistor 22 are connected in parallel between the terminals of the crystal oscillator 8 to perform an oscillating operation. The signal inverted by the circuit 26 is output as CLK1.

On the other hand, when the stop signal S1 is at the high level, the N-channel transfer gate 25 is turned on, an inverted signal of the stop signal S1 is input to the gate, the N-channel transfer gate 24 is turned off, and the stop signal S1 is turned off. The output of the tri-state type inverter circuit 21 for inputting the inverted signal to the control terminal is in a high impedance state, the power supply voltage (High level) which is a fixed potential is input to the input of the inverter circuit 26, and output via the inverter 26. CLK1 is fixed at the low level.

The clock control circuit 3 in FIG.
A circuit that changes the logic level of the stop signal S1 in synchronization with the rise of the clock signal CLK2 in response to an interrupt signal for releasing the standby mode of U10, and a circuit that generates the switching signal S3 that switches between the clock signal CLK1 and the clock signal CLK2. And Since the clock control circuit 3 can be configured using a known circuit configuration, a detailed configuration thereof is omitted.

The edge detecting circuit 5 receives an interrupt signal for releasing the CPU standby mode, rises while the clock signal CLK2 is at the high level, and
A signal S2 which becomes a low level at the fall of the signal 2 is output.

FIG. 2 is a timing chart showing an operation when the oscillation circuit 1 starts oscillating after the CPU 10 returns from the standby state in one embodiment of the present invention.

The operation of one embodiment of the present invention will be described with reference to FIGS. When the CPU 10 is in a standby mode (a state in which the CPU 110 is stopped and only the peripheral circuit 11 is operating), the operation of the oscillation circuit 1 is started /
The stop signal S1 for controlling the stop is at the high level, the oscillation circuit 1 stops the oscillation, and the peripheral circuit 11 operates by the clock signal CLK2 generated from the oscillation circuit 2 having a relatively low frequency.

When the standby mode is released by an interrupt and the stop signal S1 goes low, the oscillation circuit 1 having a relatively high frequency resumes oscillation (at time T).
0). At the same time when the stop signal S1 changes from the High level to the Low level, the edge detection circuit 5 that has received the interrupt for canceling the standby mode outputs the clock signal C1.
While LK2 is at the High level, the enable signal S2
Is changed from the Low level to the High level (at time T
1) In response to the fall of the clock signal CLK2, a low level is output again (time T2).

The transfer gate 6 is turned on while the enable signal S2 is at the high level, and transmits the clock signal CLK2 to the X1 terminal of the oscillation circuit 1.

That is, only the falling edge of the clock signal CLK2 is transmitted to the oscillation circuit 1 (see the arrow in FIG. 2), and the action of capacitive coupling by the capacitor 7 triggers oscillation in the transient state of the oscillation circuit 1. To promote its oscillation growth.

As a result, the oscillation stabilization wait time of the oscillation circuit 1 is reduced from Ta in the related art to Tb in one embodiment of the present invention.

Although the case where the edge of the clock signal CLK2 generated from the auxiliary oscillation circuit 2 is transmitted to the X1 terminal of the oscillation circuit 1 is connected, the edge is transmitted to the X2 terminal of the oscillation circuit 1. Of course, the same effect can be obtained.

After oscillation of the oscillation circuit 1 is stabilized (that is, T
b), the clock control circuit 3 sets the selection control signal S3 to H
The selector 4 switches the clock signal from the high level to the low level, and the CPU is supplied with the high-frequency clock signal CLK1.

FIG. 3 is a diagram showing the configuration of the second embodiment of the present invention. According to the second embodiment of the present invention, instead of transmitting the falling edge of the clock CLK2 used in the standby mode to the X terminal of the oscillation circuit 1, the falling edge of the stop signal S1 output from the clock control circuit 3 is used. , And is transmitted to the oscillation circuit 1 by the delay circuit 12. That is, the transfer gate 6 and the capacitor 7 are inserted in series between the delay circuit 12 for delaying the stop signal S1 output from the clock control circuit 3 and the X terminal of the oscillation circuit 1, and the transfer gate 6 The enable signal S2 from the edge detection circuit 5 is input to the control terminal.

The edge detecting circuit 5 receives an interrupt signal for releasing the CPU standby mode, and receives a clock signal CL.
K2 rises during the high level, and outputs a signal S2 that goes low at the falling edge of CLK2. The transfer gate 6 is turned on while the signal S2 is at the high level, and the stop signal S1 is supplied to the delay circuit 1 during this period.
Only the falling edge delayed by 2 is transmitted to the oscillating circuit 1, and the action of capacitive coupling by the capacitor 7 triggers oscillation in the transient state of the oscillating circuit 1 to promote its oscillating growth. Can be

[0033]

As described above, according to the present invention,
In a microcomputer including two oscillation circuits having different oscillation frequencies, the oscillation of the oscillation circuit when the CPU is released from the standby mode can be accelerated, and the oscillation stabilization wait time can be shortened.

The reason is that, in the present invention, when the standby mode is released, the first oscillation circuit immediately starts oscillating again.
The falling edge (or the rising edge) of the clock signal from the second oscillation circuit given to the oscillation circuit of (1) is triggered by the action of the capacitive coupling in the oscillation transition state of the first oscillation circuit. Give
This is because the oscillation growth is configured to be promoted.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a first embodiment of the present invention.

FIG. 2 is a timing chart for explaining the operation of the first embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration of a second exemplary embodiment of the present invention.

FIG. 4 is a diagram illustrating an example of a configuration of an oscillation circuit 1 according to an embodiment of the present invention.

FIG. 5 is a block diagram showing a configuration of a conventional oscillation control circuit.

FIG. 6 is a timing chart for explaining a problem of the conventional oscillation control circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1, 2 Oscillation circuit 3 Clock control circuit 4 Selector 5 Edge detection circuit 6 Transfer gate 7 Capacitor 8, 9, 64 Crystal oscillator 10 CPU 11 Peripheral circuit 12 Delay circuit 21 Tristate inverter 22 Feedback resistor 23 Inverter 24, 25 Transfer gate 26 Inverter 51, 58 SR flip-flop 52 Crystal oscillation circuit 53 Self-excited oscillation circuit 54 Reset circuit 55, 56 Timer 57, 59 AND-type logic gate 60 Judgment circuit 62 Clock switching circuit 63 Tristate buffer

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[Procedure amendment]

[Submission date] October 26, 1998 (1998.10.
26)

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Claim 3

[Correction method] Change

[Correction contents]

[Procedure amendment 2]

[Document name to be amended] Statement

[Correction target item name] Claim 4

[Correction method] Change

[Correction contents]

[Procedure amendment 3]

[Document name to be amended] Statement

[Correction target item name] 0012

[Correction method] Change

[Correction contents]

Further, the present invention includes first and second oscillation circuits having different oscillation frequencies from each other, wherein the first oscillation circuit stops oscillating and the first oscillation circuit oscillates when the second oscillation circuit is in an oscillation state. when receiving the oscillation start signal of the oscillation circuit, a control signal including the second input one of the transition edge timing of rising under the rising or falling of emitting drawer forces the oscillation output from the oscillation circuit during the active period An edge detection means for outputting the output signal, wherein an output of the second oscillation circuit is connected to an input terminal of the first oscillation circuit via a capacitor and a first switch, and outputs a control signal output by the edge detection means. In response, the first switch is turned on, and during that time, one of the rising and falling edges of the oscillation output from the second oscillation circuit is caused by capacitive coupling via the capacitor. Serial supplied to the first oscillator circuit may be configured so as to facilitate the oscillation growth gives an opportunity of oscillation in said first oscillation circuit in a transient state.

[Procedure amendment 4]

[Document name to be amended] Statement

[Correction target item name] 0014

[Correction method] Change

[Correction contents]

In the preferred embodiment of the present invention, referring to FIG. 1, a first clock (CLK1) in a normal operation mode is generated, oscillation is stopped in a standby mode, and the standby mode is released to release a normal clock. A first oscillation circuit (1) that resumes oscillation when the operation mode returns, and a second oscillation circuit (2) that generates a second clock (CLK2) lower in frequency than the first clock in the standby mode. A selector (4) for switching the first and second clock signals from the first and second oscillation circuits (2) by an input switching control signal and supplying the same to the CPU (10);
And a clock that outputs a switching control signal to the selector (4) in response to the standby mode release notification signal from the CPU (10) and outputs an oscillation start signal instructing the first oscillation circuit (1) to start oscillation. The control circuit (3) and the second clock from the second oscillation circuit (2) are inputted, and the CPU
Upon receiving the standby release notification signal from (10),
A edge detection circuit for outputting a detection to the control signal (S2) a second rising or falling of the one edge of the clock, as the control signal (S2), in the ON period (active period), an edge detecting circuit (5) for outputting a pulse signal containing one of the transition edge timing of rising rising or falling of the second clock, the output end of the first oscillation circuit of the second oscillation circuit (2) A transfer gate (6) and a capacitor (7) are connected in series between the input terminal of (1) and a capacitor (7). The control terminal of the transfer gate (6) is output from the edge detection circuit (5). When the standby mode is released, the control signal output from the edge detection circuit (5) is input through the transfer gate (6) which is turned on when the standby mode is released. One edge of the rise or fall of the second clock from Fukairo (2),
Supplied to the input terminal of the first oscillation circuit (1) by capacitive coupling via the capacitor (7), the first oscillation circuit (1) in a transient state is triggered to oscillate to promote oscillation growth.

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5B079 AA07 BA02 BA15 BB01 BC01 DD02 DD17 5J079 AA04 AB04 BA22 BA24 BA41 EA06 EA18 EA20 FA05 FA14 FB03 FB04 FB22 FB40 FB48 GA05 GA09 GA11 KA01

Claims (7)

[Claims] A first oscillating circuit having an oscillating frequency different from each other, wherein when the first oscillating circuit is in an oscillation stop state and the second oscillating circuit is in an oscillating state, the first oscillation is performed. In response to the oscillation start signal of the circuit, one of the rising edge and the falling edge of the oscillation output signal from the second oscillation circuit is supplied to the first oscillation circuit by capacitive coupling via a capacitor, and the transient An oscillation control circuit, wherein an oscillation trigger is given to the first oscillation circuit in a state to promote oscillation growth. 2. The method according to claim 1, further comprising first and second oscillation circuits having different oscillation frequencies from each other, wherein the first oscillation is performed when the first oscillation circuit is in the oscillation stop state and the second oscillation circuit is in the oscillation state. Edge detection for receiving an oscillation output from the second oscillation circuit when receiving an oscillation start signal of the circuit, and outputting a signal including one of transition edges of rising and falling of the oscillation output in an active period. An output of the second oscillation circuit is connected to an input terminal of the first oscillation circuit via a capacitor and a first switch; Is turned on, and during that time, one of the rising and falling transition edges of the oscillation output from the second oscillation circuit is caused by the first coupling by the capacitive coupling via the capacitor. Oscillation control circuit is supplied to the circuit and promotes the oscillation growth gives an opportunity of oscillation in said first oscillation circuit in a transient state, characterized in that. 3. A first clock for generating a first clock for a normal operation mode, stopping oscillation in a standby mode, canceling the standby mode and restarting the oscillation when returning to the normal operation mode. An oscillating circuit; a second oscillating circuit for generating a second clock having a lower frequency than the first clock in a standby mode; and first and second clock signals from the first and second oscillating circuits. And a selector for switching the first oscillation circuit to supply the same to the CPU by the input switching control signal, controlling the start and stop of the oscillation of the first oscillation circuit, and receiving the standby mode release notification signal from the CPU. A clock control circuit for instructing the oscillation circuit to start oscillating and outputting the switching control signal to the selector; and a second clock from the second oscillation circuit as an input. ,
Upon receipt of a standby release notification signal from the CPU, one rising edge or one rising edge of the second clock is detected, and one rising edge of the second clock or one rising edge of the rising edge is activated. An edge detection circuit that outputs a control signal included in a period; a transfer gate and a capacitor connected in series between an output terminal of the second oscillation circuit and an input terminal of the first oscillation circuit; The control signal output from the edge detection circuit is input to a control terminal of the transfer gate, and the transfer gate is turned on in response to the control signal output from the edge detection circuit when the standby mode is released. Through one of the rising and falling of the second clock from the second oscillation circuit Is supplied to the first oscillation circuit by capacitive coupling via the capacitor, and triggers oscillation of the first oscillation circuit in a transient state to promote oscillation growth. Oscillation control circuit. 4. A first clock for generating a first clock for a normal operation mode, stopping oscillation in a standby mode, canceling the standby mode and restarting the oscillation when returning to the normal operation mode. An oscillating circuit; a second oscillating circuit for generating a second clock having a lower frequency than the first clock in a standby mode; and first and second clock signals from the first and second oscillating circuits. And a selector for switching the first oscillation circuit to start and stop the oscillation by the input switching control signal, and controlling the oscillation start and stop of the first oscillation circuit. A clock control circuit that instructs the first oscillation circuit to start oscillation and outputs the switching control signal to the selector; and a second clock from the second oscillation circuit, When receiving the standby release notification signal from the CPU,
An edge detection circuit that detects a rising edge or one rising edge of the second clock and outputs a control signal including an active period including one rising edge or the rising edge of the second clock; An oscillation start signal output terminal of the control circuit;
A delay circuit, a transfer gate, and a capacitor connected in series between the input terminal of the oscillation circuit and a control terminal of the transfer gate, wherein the control signal output from the edge detection circuit is provided at a control terminal of the transfer gate. When the standby mode is released, the oscillation start signal is delayed by the delay circuit from the clock control circuit through the transfer gate that is turned on in response to the control signal output from the edge detection circuit, One of the falling transition edges is supplied to the first oscillation circuit by capacitive coupling via the capacitor, and triggers oscillation of the first oscillation circuit in a transient state to promote oscillation growth. An oscillation control circuit characterized by the above. 5. The first and second oscillating circuits include first and second oscillating circuits.
Both ends of the crystal unit are connected between the input terminals of
An input terminal and an output terminal of the inverter circuit, a crystal oscillation circuit in which a feedback resistor and a second switch are connected in parallel. When the oscillation start signal is off, the second switch is turned off and the inverter circuit is also turned off. The oscillation control circuit according to any one of claims 1 to 3, wherein: 6. A third switch is provided between an output of the inverter and a fixed potential. When the oscillation start signal is off, the third switch is turned on, the inverter is turned off, and the output of the inverter is turned off. The oscillation control circuit according to claim 5, wherein the oscillation control circuit has a fixed potential. 7. A microcomputer comprising the oscillation control circuit according to claim 1.