JP2842824B2 - PWM signal generator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a PWM signal generator, and more particularly to a PRM signal generator used for motor control.

[0002]

2. Description of the Related Art Conventional PWM (Pulse Width Modulatio)
n) Prior to the signal generator, an application example in which a motor is rotated using a two-phase PWM signal to obtain a desired rotation angle will be described. FIG. 12 shows a configuration example of the motor in this case.
It is shown in FIG. In FIG. 12A, a magnet is attached to two coils A and B wound orthogonally so as to be orthogonal to the axial direction of the two coils, and the magnet is attached to the axis of both coils. It is configured to rotate about. Therefore, the magnet is rotated by the magnetic field of the coils A and B, and stops at a predetermined rotation angle. On the other hand, the strength of the magnetic field is the effective value of the current flowing through the coil,
That is, it is known that the duty is proportional to the duty of the PWM signal. For example, in order to stop the magnet at the rotation angle θ, the strengths of the magnetic fields A and B are set as shown in FIG. The effective value of the two-phase PWM signal may be set by the following relational expression.

The effective value of the PWM signal A = M × sin θ (1) The effective value of the PWM signal B = M × cos θ (2) (M: effective value) In order to obtain the desired rotation angle θ, it is necessary to satisfy the above relational expressions (1) and (2).
It is necessary to generate a phase PWM signal.

FIG. 6 is a block diagram showing an example of the configuration of a conventional PWM signal generator. As shown in FIG.
This conventional example (referred to as conventional example (1)) includes a counter 102 that counts by inputting a clock 101, a master register 103a and a slave register 103b,
A compare register A103 for storing a comparison value with the counter 102; a comparator A105 for comparing the count value of the counter 102 with the value of the compare register A103 to generate a match signal; and a match signal output from the comparator A105. Control circuit A110 for inputting an overflow signal of the counter 102 and controlling the PWM signal waveform
And is provided. The compare register A10
3 is composed of the master register 103a and the slave register 103b, as described above.
Data transfer from the master register to the slave register is performed in synchronization with the overflow signal 02.
FIGS. 8A, 8B, 8C and 8D are operation timing diagrams in the conventional example.

Next, the operation of the conventional example will be described with reference to FIGS. For the sake of simplicity, in the configuration in FIG. 6, both the counter 102 and the compare register A103 have an 8-bit configuration, and the counter 102 periodically counts a value from 0 to 255 (see FIG. 6). 8 (a)), and the value of M is set in advance in the compare register A103.

The clock 101 is input to the counter 102 and counted, and the count value of the counter 102 is 25.
When one more count is performed from the state of 5, the counter 102
Outputs an overflow signal and the count value is 0.
(See FIG. 8A). On the other hand, the output control circuit A11
At 0, the output level is set to "1" in response to the input of the overflow signal output from the counter 102 (see FIG. 8B). When the count value of the counter 102 matches M stored in the compare register A103, the comparator A105 outputs a match signal 11
5 is output and input to the output control circuit 110. In response to the input of the coincidence signal, the output control circuit 110 clears the output to “0” (FIG. 8A,
(B)). By repeating such an operation, the output control circuit A110 is output from the output terminal 113.
Through a PWM of duty ratio of M / 256 continuously
A signal is output (see FIG. 8B).

Next, regarding the rewriting operation in the compare register A103 corresponding to a value of N smaller than M from M, a case where rewriting is performed within a period in which the count value of the counter 102 exists between N and M Shall be considered. After the count value of the counter 102 exceeds the count value N, the compare register A
The value of 103 is changed to N, but the value stored in the compare register A103 is changed from M to N only in the master register 103a. That is, rewriting in the compare register A103 is performed (FIG. 8D).
reference). Thereafter, when the count value of the counter 102 advances to the value of M, since the value of the slave register 103a is M, the comparator 105 generates and outputs a coincidence signal 115, and receives the input of the coincidence signal 115. The output from the output control circuit A110 is cleared to "0" (see FIG. 8B). When the count value further advances and the count 102 overflows, an overflow signal is output from the counter 102, and in response to this, the output of the output control circuit A110 is set to "1" (FIG. 8B). reference). At the same time, due to the overflow signal, the master register 103a outputs
The value of the stored value N is transferred to the slave register 103b (see FIGS. 8C and 8D).

As described above, compare register A10
3 with the master register 103a and the slave register A1
In the case of the conventional example (1) in which the stored value is transferred from the master register 103a to the slave register a103b when the counter 102 overflows or underflows, the pair of the compare register A103 and the comparator A105 is If there is one, a stable PWM signal can be generated.

Generally, in a PWM signal generator,
When a plurality of compare registers, comparators, and output control circuits are provided, the bit length that can be processed by the central processing unit is fixed, and the comparison values of all the compare registers may not be updated at the same time. Can be For example, in a central processing unit, data processing is performed with an 8-bit length, and a compare register having a bit width of 8 bits has 2 bits.
In the case of a configuration in which the number is provided, the central processing unit needs to update the comparison value of the compare register by performing the rewriting process twice.

FIG. 7 shows a comparison register, a comparator and an output control circuit for outputting a two-phase PWM signal.
Another conventional example configured as a set (referred to as conventional example (2))
FIG. As shown in FIG. 7, in this conventional example, a counter 102 for counting by inputting a predetermined reference clock signal 101, a master register 103a
And a slave register 103b.
A compare register A103 for storing a comparison value with 2;
Master register 104a and slave register 104
b and a compare register B104 for storing a comparison value with the counter 102, and comparing the count value of the counter 102 with the value of the compare register A103 to find a match signal 1
15; a comparator B 106 for comparing the count value of the counter 102 with the value of the compare register B 104 to generate a coincidence signal 116;
The match signal 115 output from the counter 105 and the counter 10
2 and an output control circuit A110 for inputting the overflow signal and controlling the PWM signal waveform, and a comparator B105.
The output control circuit B111 that receives the coincidence signal 116 output from the counter 102 and the overflow signal of the counter 102 to control the PWM signal waveform, the readout circuit 113 that reads out the value of the counter 106, and the central processing unit 109 It is configured with. The compare register A103
And the compare register B104, as described above,
The master register and the slave register are each configured, and data transfer from the master register to the slave register is performed in synchronization with an overflow signal of the counter 102. 9 (a), (b),
(C), (d), (e), (f), and (g) are operation timing diagrams showing states of malfunctions in the operation occurring in the above-described conventional example.

To simplify the description of the conventional example, FIG.
In the configuration of the conventional example (2) shown in FIG. 2, M ₁ and the compare register B10 are previously stored in the compare register a103.
4, the stored value of M ₂ is set, and the output control circuit A
110 duty of the PWM signal of M _1/256 is outputted periodically from, from the output control circuit B 111 M ₂ /
It is assumed that a PWM signal having a duty ratio of 256 is output periodically. In order to change the PWM signal waveform, the stored value of the compare register is rewritten. When the stored value of the compare register is rewritten without considering the count value of the counter, the compare register A103 and the compare register B104 are rewritten. During rewriting, overflow may occur in the counter 102. At this time, before an overflow occurs in the counter 102, the compare register A10
The case where the stored value of 3 is rewritten from M ₁ to N ₁ and the stored value of the compare register B 104 is rewritten from M ₂ to N ₂ after the counter 102 overflows will be described.

First, after the value of the master register 103a of the compare register A103 is rewritten,
In 2, an overflow occurs, and data transfer from the master register 103 a to the slave register 103 b is performed. The value of the master registers 103a compare register A103 is already rewritten to N _1, the slave register 10 of the compare register A103
The 3b, stored value N ₁ is the value is changed are transferred. However, in the compare register B104, since the value of the master register 104a has not yet been rewritten, the same M ₂
Is transferred, and the value stored in the slave register 104b is not changed. Therefore, as described above, the PW immediately after the counter 102 overflows when the rewriting of the compare register A103 is performed.
The M signals from the output terminal 113, Deyu set in after the change - of N _1/256 is a duty ratio Deyu - Ti ratio - is No. waveform is output, also from the output terminal 114, set in the pre-change M ₂ /
A signal waveform having a duty ratio of 256 is output. Therefore, the relationship between the two-phase PWM signal waveforms is an undesirable combination.

Next, as other conventional examples, for example,
As an example of a PWM signal generator for transferring data from a master register of a compare register to a slave register by using a periodic signal output from a timer, Japanese Patent Laid-Open No.
2. Description of the Related Art A PWM signal generator disclosed in Japanese Patent Application No. -228102 is known.

FIG. 11 shows the above-mentioned JP-A-3-228102.
FIG. 1 is a block diagram illustrating a configuration of a PWM signal generation device disclosed in Japanese Patent Application Publication No. H10-115,004. As shown in FIG. 11, in this conventional example (referred to as conventional example (3)), a timer register 302,
An interval timer 301 including a period register 303 and a timer calculator 304, and a parallel comparison type associative memory 305 including an output time master register group 306, an output time slave register group 307, an output control master register group 308, and an output control slave register group 309. , Comparator group 310, copy permission circuit 311, output control circuit 3
12 and a control register 313. As a correspondence between FIG. 11 and FIG. 7, the interval timer 301 corresponds to the counter 102 in the conventional example (2) shown in FIG. 7, and the output time master register group 306 included in the parallel comparison type associative memory 305 is Conventional example (2)
Compare register A103 and compare register B
At 104, each of the included master registers 10
3a and the master register 104a, and the comparator group 310 is similarly the comparator A10 of the conventional example (2).
5 and the comparator B106, and the output control circuit 312
Corresponds to the output control circuit A110 and the output control circuit A111 of the conventional example (2).

Referring to FIG. 11, an interval timer 30
In step 1, the timer clock signal S1 is input and a count operation from 0 to the value set in the cycle register 303 is performed. Each time the timer value returns to 0, a predetermined cycle signal S2 is generated. The output is output to the copy permission circuit 311. In response to the input of the periodic signal S2, the copy permitting circuit 311 outputs the periodic signal S2.
2 is generated each time the number of times specified by the control register 313 occurs, and the content of the output time timer register group 306 is periodically transferred to the output time slave register group 307 by this copy signal S3. You. The output time register group, the output control register group, and the comparator group form a set. When the output time slave register included in the output time slave register group 307 and the value of the interval timer 120 match, the corresponding comparator group 310 Are output from the comparators included in the output control slave registers included in the output control slave register group 309. The value of the output control slave register corresponding to the coincidence signal input is input to the output control circuit 312, and the output signal is changed from the output control circuit 312 according to the value and output as a PWM signal. If the control register 313 permits the generation of an interrupt, the control register 313 outputs an interrupt signal S5 in synchronization with the copy permission signal S3. Slave register group 307
Is used for rewriting the parallel-type associative memory 304 after the data transfer.

[0016]

As described above, the PW
In an application example of the M signal generator in an industrial application field, the rotation angle θ that the magnet intends to direct is two-phase PW
It is determined by the duty ratio of the M signal. In the case of the conventional example (2) shown in FIG. 7, if the stored value of the compare register is rewritten before or after the counter overflows in the operation timing chart of FIG. Is not normal (see FIGS. 9 (b) and 9 (c)), and a "loss" or "blur" occurs in the rotation of the motor because the magnet tries to rotate in an unexpected direction. Is caused. As described above, in the application of the PWM signal generator, the operation of which is controlled by the relationship between the duty ratios of the two outputs, a defect occurs in the operation due to the timing when each compare register is changed. In addition, it is possible to avoid the above problem by rewriting the compare register by software to avoid overflow of the counter.However, in this case, another problem occurs as described below. There is a disadvantage of doing so.

That is, FIG. 10 shows a conventional example (2).
If you try to avoid bugs with software,
It is a figure showing the processing procedure by a central processing unit. In the main processing 201 of FIG. 10, a request for changing the output is generated, and a routine for rewriting the compare register is started. In the central processing unit 109 (see FIG. 7),
A counter reading process is performed to check whether it is a timing that does not cause any problem even if the compare register is rewritten (step 206). With reference to the read value of the counter, before the counter overflows, It is determined whether or not the count value is such that the rewriting of the compare register can be completed (step 20).
7) If the count value can be rewritten, the rewriting process of the compare register A103 (step 20)
3) and the rewriting process of the compare register B104 (step 204) is performed, the process returns to the main process 201, and the routine process of rewriting the compare register ends. If it is determined in step 207 that the rewriting of the compare register cannot be completed before the counter overflows by referring to the read value of the counter, a wait process is performed (step 208). Returning to step 206, the counter is read again after a certain period of time has elapsed (step 206), and it is determined whether or not it is time to rewrite the compare register (step 2).
07). Hereinafter, as described above, steps 203 and 20 are performed.
4 or the processing procedure of step 208 is repeatedly performed.

As described above, in the case of the conventional example (2), when trying to avoid a defect by software, it is determined whether or not the value of the counter is a value suitable for rewriting the compare register. If it is determined that the compare register is not appropriate, it is necessary to delay the timing of rewriting the compare register. Therefore, there is a disadvantage that the processing amount in the central processing unit increases and the processing procedure is delayed.

In the central processing unit, by reading and confirming the count value of the counter, a circuit for reading the counter (the read circuit 11 in FIG. 7).
3) is required, and there is a disadvantage that the circuit scale increases. In particular, when the central processing unit 109 and the counter 102 operate in an asynchronous state, the reading of the counter needs to be synchronized with the reading timing, and the configuration of the reading circuit 113 of the counter is further complicated. And the circuit scale is further increased.

In the case of the conventional example (3) disclosed in Japanese Patent Laid-Open No. 3-228102, a new interrupt is generated by a signal for transferring data from the master register to the slave register, and the interrupt is generated. The above problem is avoided by rewriting the compare register after the occurrence of the interrupt, but the drawback that adding interrupt processing in this way results in an increase in the circuit scale related to the interrupt control function. is there.

Further, in the case of the prior art (3), an interrupt is generated by a signal obtained by dividing the period signal of the counter, and the number of times of the interrupt is reduced, so that the processing amount in the central processing unit is reduced. Although the increase is suppressed, a frequency divider for newly dividing the frequency of the periodic signal is required, which also has the disadvantage of increasing the circuit scale.

[0022]

A PWM signal generator according to the present invention comprises a counting means for inputting a predetermined reference clock signal, counting and outputting the same, and a predetermined reference value corresponding to the counting means. N storage means formed by individually providing a first storage circuit for storing data and a second storage circuit arranged corresponding to the first storage circuit, and overflow of the counting means. The control operation is performed so as to transfer the storage contents of the first storage circuits respectively included in the n storage units to the corresponding second storage circuits in the storage units in synchronization with a signal or an underflow signal. And a data transfer control unit that compares the count value of the counting unit with a reference value stored in a second storage circuit included in each of the n storage units to generate a match signal or a mismatch signal. N comparators to be input, a coincidence signal output from the n comparators, and an overflow signal or an underflow signal from the counter, and generates and outputs a predetermined PWM signal. And output control means, at least during which a predetermined reference value is written in a first storage circuit included in each of the n storage means. The data transfer control means inhibits data transfer of the contents stored in the first storage circuit to the second storage circuit, which is performed in synchronization with the overflow signal or the downflow signal of the means.

The first storage circuit may be formed by a master register, and the second storage circuit may be formed by a slave register.

The data transfer control means receives a latch controlled by a predetermined central processing unit, receives an output of the latch and an overflow signal or an underflow signal output from the counting means, and performs a logical operation. And a logic level signal for controlling the availability of data transfer via the control operation of the central processing unit. Alternatively, the data transfer control means may include: An active level is output by a first data rewrite signal for the first first storage circuit via a write control signal output from a predetermined central processing unit, and an n-th output signal for the n-th first storage circuit is output.
A flip-flop that outputs an inactive level after the end of the data write signal, and a logic circuit that receives the output of the flip-flop and an overflow signal or an underflow signal that is output from the counting means and performs a logical operation. A logic level signal for controlling whether or not data can be transferred may be output through a control operation of the central processing unit.

[0025]

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention. As shown in FIG.
It includes a counter 102 for inputting and counting a predetermined reference clock signal 101, a master register 103a and a slave register 103b, a compare register A103 for storing a comparison value with the counter 102, and a master register 104a and a slave register 104b. A compare register B104 for storing a comparison value with the counter 102, and a comparator for comparing the count value of the counter 102 with the values of the compare register A103 and the compare register B104, respectively, and outputting match signals 115 and 116, respectively. A105 and a comparator B106, the coincidence signals 115 and 116,
An output control circuit A110 and an output control circuit B111 that receive an overflow signal of the counter 102, control the waveform of the PWM signal, and output a predetermined PWM signal via output terminals 113 and 114, and a central processing unit 109 A latch 107 whose output is controlled, an output of the latch 107 and an overflow signal of the counter 102 are input to a master register (master register 103).
a, an AND circuit 108 for controlling a data transfer operation from the master register 104a) to the corresponding slave register (slave register 103b, slave register 104b). The data transfer from the compare register to the slave register is performed in synchronization with the overflow signal output from the counter 102.

FIGS. 2 (a), (b), (c),
(D), (e), (f), (g) and (h) are operation timing diagrams in the present embodiment.

Next, this embodiment will be described with reference to FIGS. In order to simplify the description, the counter 102, the compare register A103, and the compare register B104 have an 8-bit configuration,
The counter 102 periodically counts a value from 0 to 255. The stored value M1 is preset in the compare register A103, and the compare register B10
4, a stored value M2 is set in advance.
Is set to "0" in advance as an initial value.

In the operation state before rewriting of the compare register, as in the case of the conventional example (2) shown in FIG.
The output control circuit A110 periodically outputs a PWM signal (output waveform A) having a duty ratio of M1 / 256,
The output control circuit A111 periodically outputs a PWM signal (output waveform B) having a duty ratio of M2 / 256 (see FIGS. 2B and 2C). Thereafter, in order to change the signal waveform of the PWM signal, the compare register is rewritten. Immediately before this rewriting operation is performed, the output from the latch 107 to the AND circuit 108 is controlled by the central processing unit 109. Is changed to "1" (see FIG. 2 (h)). While the transfer inhibit signal is at the level of "1",
“0” is always output from the AND circuit 108 irrespective of the level of the overflow signal output from the counter 102, and in response thereto, the compare register A 1 by the central processing unit 109 is received.
03 and the compare register B104 are rewritten, and after the rewriting of all the compare registers is completed, a process of returning the value of the latch 107 to the original value “0” is performed.

By the above processing operation, during the rewrite period of the compare register, the signal output from the AND circuit 108 is always at "0" level.
While the compare register is being rewritten, data transfer from the master register to the slave register is not performed even when the counter 102 is overflowing (FIG. 2D).
(E) and (f), (g)). Since the rewriting of the compare register is performed by the central processing unit 109, the value of the latch 107 may be changed by the central processing unit 109 before and after the period of the rewriting process of the compare register. While the compare register is rewritten, the data transfer from the master register to the slave register is prohibited as described above. Therefore, no matter what the count value of the counter 102 is, the central processing unit 109 Since the rewrite of the compare register can be performed according to a certain procedure, there is an advantage that the process of checking the count value of the counter 102 and changing the operation procedure based on the count value becomes unnecessary and is omitted.

FIG. 3 is a block diagram showing the configuration of the second embodiment of the present invention. In one embodiment, the inhibition of data transfer from the master register to the slave register in the compare register is realized by another circuit. is there.

As shown in FIG. 3, as in the first embodiment, a counter 102 for inputting and counting a predetermined reference clock signal 101 and a master register 10
3a and a slave register 103b, and a compare register A1 for storing a comparison value with the counter 102
03, a compare register B104 including a master register 104a and a slave register 104b, and also storing a comparison value with the counter 102;
Is compared with the values of compare register A103 and compare register B104, respectively, and comparator A1 outputs match signals 115 and 116, respectively.
05, the comparator B106, the coincidence signals 115 and 116, and the overflow signal of the counter 102, and control the waveforms of the PWM signals to output predetermined PWM signals via output terminals 113 and 114, respectively. Control circuit A110 and output control circuit B111
And a flip-flop 112 which is activated by a data write signal A117 to the compare register A103 output from the central processing unit 109 and becomes inactive after the end of the data write signal B118 to the compare register B104.
12 and the overflow signal of the counter 102 are input to a master register (master register 103).
a, an AND circuit 108 for controlling data transfer from the master register 104a) to the corresponding slave register (slave register 103b, slave register 104b). FIG. 4A,
(B) and (c) are operation timing diagrams in the present embodiment.

In the first and second embodiments, the logic circuit for inhibiting the transfer is formed by the inverter and the AND logic element. In the case where the active level of the signal for performing data transfer to the register is different, the logic circuit naturally has a different configuration.

In the above-mentioned conventional example (3), although it was possible to avoid the trouble by reading the count value of the counter 102 by the central processing unit 109, the processing amount of the central processing unit increases. In addition, there is a drawback that a readout circuit is required. In contrast, in the present embodiment, as shown in the processing flow of FIG. 5, in the main processing 201, an output request is generated and a routine for rewriting the compare register is started. In the central processing unit 109, a transfer prohibition process is performed (step 202), and the counter 10
The rewrite processing of the compare register A103 and the compare register B104 is performed without checking the count value of 2 (steps 203 and 204). Next, after the rewriting of the register is completed, a transfer prohibition release process is performed (step 205), and the process returns to the main process 201.
The routine for rewriting the compare register ends.

Further, in the case of the second embodiment,
Since the transfer prohibition process (step 202) and the transfer prohibition release process (step 205) are performed not by software but by hardware, the operation procedure required for the process can be simplified. In addition, in the conventional configuration, when the bit width of the counter is 8 bits, at least eight read buffers are required as the counter read circuit in the conventional configuration. However, in the case of the present invention, it can be constituted by only one latch or flip-flop, one AND logic element and one inverter,
The circuit scale is simplified accordingly. Also, since the bit width of the counter and the bit width of the readout circuit are the same,
In general, the larger the bit width of the counter, the larger the circuit scale of the readout circuit. However, in the present invention, the circuit that needs to be added is kept constant without depending on the bit width of the counter. In addition, as the bit width of the counter increases, the difference between the additional elements in the circuit configuration of the present invention and the conventional example increases, and the advantages of the present invention become clearer. Furthermore, in the conventional circuit configuration, when the operation of the central processing unit and the counter operate asynchronously, a stable read operation can be performed even when the read operation of the counter and the count-up operation conflict with each other. In addition, it is necessary to add a circuit such as a latch for holding a count value during a reading period to form a reading circuit,
This further increases the difference in hardware circuit scale from the present invention that does not require a counter readout circuit.

[0036]

As described above, the present invention is applied to a PWM signal generator including a plurality of compare registers and comparators, and transfers data from a master register of a compare register to a slave register. By providing a circuit that inhibits the rewriting during the rewrite execution period, there is an effect that the relationship between the combinations of the duty ratios of a plurality of PWM signals can always be normally maintained.

Further, the transfer prohibition process and the transfer prohibition release process can be performed simultaneously with the process of rewriting the compare register, so that an increase in the processing amount in the central processing unit can be eliminated.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is an operation timing chart in the first embodiment.

FIG. 3 is a block diagram showing a second embodiment of the present invention.

FIG. 4 is an operation timing chart in the second embodiment.

FIG. 5 is a diagram showing a flowchart of a processing procedure in the present invention.

FIG. 6 is a block diagram showing a conventional example (1).

FIG. 7 is a block diagram showing a conventional example (2).

FIG. 8 is an operation timing chart in the conventional example (1).

FIG. 9 is an operation timing chart in the conventional example (2).

FIG. 10 is a diagram showing a flowchart of a processing procedure in a conventional example.

FIG. 11 is a block diagram showing a conventional example (3).

FIG. 12 is a diagram showing one application example of a PWM signal generator.

[Explanation of symbols]

 101 Reference clock signal 102 Counter 103 Compare register A 103a, 104a Master register 103b, 104b Slave register 104 Compare register B 105 Comparator A 106 Comparator B 107 Latch 108 AND circuit 109 Central processing unit 110 Output control circuit A 111 Output control circuit B 112 Flip-flop 113, 114 Output terminal 115, 116 Match signal 117 Data write signal A 118 Data write signal B 201 Main process 202 Transfer inhibit process 203 Compare register A rewrite process 204 Compare register B rewrite process 205 Transfer inhibit release process 206 Counter Read 207 Rewriteable count value? 208 wait processing 301 interval timer 302 timer register 303 period register 304 timer arithmetic unit 305 parallel comparison type associative memory 306 output time master register group 307 output time slave register group 308 output control master register group 309 output control slave register group 310 comparator group 311 Copy permission circuit 312 Output control circuit 313 Control register S1 Timer clock signal S2 Period signal S3 Copy signal S4 Match signal group S5 Interrupt signal

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H02M 7/42-7/98 H03K 7/08 H02P 7/63 H02P 5/41

Claims (4)

(57) [Claims] 1. A counting means for receiving a predetermined reference clock signal, counting and outputting the same, a first storage circuit for storing a predetermined reference value corresponding to the counting means, N (positive integers) storage means individually provided with a second storage circuit arranged corresponding to the storage circuit of (i), and in synchronization with an overflow signal or underflow signal of the counting means. A data transfer control unit that performs a control operation to transfer the storage contents of the first storage circuit included in each of the n storage units to the corresponding second storage circuit in the storage unit; N comparing means for comparing and counting the count value of the counting means with a reference value stored in a second storage circuit included in each of the n storing means, and outputting a match signal or a mismatch signal; The n n that the the coincidence signal outputted from the comparing means, inputs an overflow signal or an underflow signal of said counting means, and generates and outputs a predetermined PWM signal
And at least one of the n output control means, and in the period in which a predetermined reference value is written in the first storage circuit included in each of the n storage means, A data transfer control unit for prohibiting the data transfer of data stored in the first storage circuit to the second storage circuit, the data transfer being performed in synchronization with an overflow signal or a downflow signal of the unit. Generator. 2. The PWM signal generator according to claim 1, wherein said first storage circuit is formed by a master register, and said second storage circuit is formed by a slave register. 3. The data transfer control means inputs a latch whose output is controlled by a predetermined central processing unit, and inputs an output of the latch and an overflow signal or an underflow signal output from the counting means to perform a logical operation. 3. A PW according to claim 1, wherein said PW outputs a logic level signal for controlling whether or not data transfer is possible through a control operation of said central processing unit.
M signal generation circuit. 4. The data transfer control means according to claim 1, wherein said write control signal is output from a predetermined central processing unit.
A flip-flop that outputs an active level in response to a first data rewrite signal for the first storage circuit and outputs an inactive level after termination of an n-th data write signal for the n-th first storage circuit; It is constituted by a logic circuit which inputs and outputs an output of the flip-flop and an overflow signal or an underflow signal output from the counting means, and controls whether or not data transfer is possible through a control operation of the central processing unit. 3. The PWM signal generation circuit according to claim 1, wherein the PWM signal generation circuit outputs a logic level signal.