JP5232971B2 - Method for manufacturing nitride-based semiconductor light-emitting device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a process for fabricating a nitride-based semiconductor light emitting element having high light extraction efficiency and excellent in light emission characteristic and productivity. <P>SOLUTION: The process for fabricating a nitride-based semiconductor light emitting element comprises a step for forming a semiconductor layer 104 by laminating at least an n-type semiconductor layer, a light emitting layer, and a p-type semiconductor layer sequentially on a first substrate 101, and obtaining a lamination semiconductor having a side face consisting of an inclining surface formed by blasting the semiconductor layer; and a step for providing a second substrate on the lamination semiconductor and then stripping the first substrate from the lamination semiconductor by irradiating the interface thereof with laser light, wherein a substrate having a Vickers hardness higher than that of the semiconductor layer is employed as the first substrate. <P>COPYRIGHT: (C)2008,JPO&amp;INPIT

Description

The present invention relates to the production how the nitride-based semiconductor light-emitting device.

  In recent years, GaN-based compound semiconductor materials that are nitride-based semiconductors have attracted attention as semiconductor materials for short-wavelength light-emitting elements. GaN-based compound semiconductors include sapphire single crystals, various oxides and III-V group compounds as substrates, and metal organic vapor phase epitaxy (MOCVD), molecular beam epitaxy (MBE), etc. on this substrate. Formed by.

  A characteristic of the GaN-based compound semiconductor material is that current diffusion in the lateral direction is small. For this reason, current is injected only into the semiconductor directly under the electrode, and light emitted from the light emitting layer is blocked by the electrode and is not extracted outside. Therefore, in such a semiconductor light emitting element, a translucent positive electrode is usually used, and light is extracted through the translucent positive electrode.

  Conventionally, the translucent positive electrode used has a layer structure in which an oxide of Ni or Co and Au as a contact metal are combined. In recent years, a translucent positive electrode having a layer structure in which the thickness of the contact metal is made as thin as possible by using an oxide having higher conductivity than ITO or the like to increase translucency is used. Thus, the light from the light emitting layer is efficiently extracted to the outside.

  By the way, the external quantum efficiency of the light emitting element is expressed as a product of the light extraction efficiency and the internal quantum efficiency. The internal quantum efficiency is a ratio of energy converted into light in the energy of current injected into the light emitting element. The light extraction efficiency is the proportion of light that can be extracted outside of the light generated inside the semiconductor crystal.

It is said that the internal quantum efficiency of the light-emitting element has been improved to about 70 to 80% at present due to the examination of the improvement of the crystal state and the optimization of the structure, etc., which has a sufficient effect on the amount of injected current. It can be said that it is obtained.
However, in light-emitting diodes (LEDs) as well as GaN-based compound semiconductors, the light extraction efficiency is generally low and it is difficult to say that internal light emission is sufficiently extracted outside with respect to the energy of the injected current. .

  The light emission efficiency of the light emitting diode is low because the refractive index of the light emitting layer in the GaN-based compound semiconductor is about 2.5, which is very high compared to the refractive index of air, and the critical angle is about 25 °. This is because the light cannot be extracted outside by repeating reflection and absorption in the crystal.

In order to improve the light extraction efficiency of a light-emitting element made of a GaN-based compound semiconductor, a semiconductor light-emitting element having a side surface formed on an inclined surface by blasting has been proposed (for example, Patent Document 1).
However, since the semiconductor light emitting device described in Patent Document 1 is manufactured by a method of forming a tapered shape while performing angle control of blasting, it is difficult to control the angle to stably form the tapered shape, and productivity There is a problem that is low.

In addition, a semiconductor light emitting element in which irregularities are formed by blasting on a part of a sapphire substrate used for the semiconductor light emitting element has been proposed (for example, Patent Document 2).
The semiconductor light-emitting element described in Patent Document 2 has a certain effect in improving light extraction efficiency due to the above configuration.

However, the light extraction efficiency of a semiconductor light emitting device made of a GaN-based compound is mainly due to the difficulty in extracting light from the inside due to the large refractive index of the GaN-based compound. In the configuration in which the sapphire substrate is formed with unevenness like the semiconductor light emitting device, the light extraction efficiency cannot be sufficiently improved.
Japanese Patent Laid-Open No. 10-341035 JP 2004-56088 A

  The present invention has been made in view of the above circumstances, and has a high light extraction efficiency, excellent light emission characteristics, and a method for producing a nitride semiconductor light emitting device excellent in productivity, nitride semiconductor light emitting device, and The purpose is to provide a lamp.

In order to achieve the above object, the present invention employs the following configuration.
[1] A method for manufacturing a nitride-based semiconductor light-emitting device in which a semiconductor layer made of a nitride-based semiconductor is stacked on a substrate, wherein at least an n-type semiconductor layer, a light-emitting layer, and a p-type semiconductor are formed on the first substrate. Forming a semiconductor layer by sequentially laminating layers, forming a mask layer having processing resistance against blasting on the semiconductor layer, and blasting a portion of the semiconductor layer not covered by the mask layer; A step of dividing the semiconductor layer and forming a plurality of stacked semiconductors having side surfaces made of inclined surfaces formed by the blasting , and a step of forming a sacrificial film so as to be embedded between the stacked semiconductors. Then, after providing the second substrate on the laminated semiconductor and the sacrificial film, the first substrate is placed on the laminated semiconductor by irradiating a laser beam to the interface between the first substrate and the laminated semiconductor. And a step of removing the sacrificial film after peeling of the first substrate, and the thickness of the semiconductor layer is in the range of 3 to 15 μm,
The blasting is performed using blast particles having a Vickers hardness lower than that of the first substrate, the processing width is 30 to 100 μm, the average particle size of the blast particles is 5 to 50 μm, and the first substrate is A method for manufacturing a nitride-based semiconductor light-emitting device, comprising using a substrate having a Vickers hardness higher than that of the semiconductor layer.
[2] A method for manufacturing a nitride-based semiconductor light-emitting device in which a semiconductor layer made of a nitride-based semiconductor is stacked on a substrate, wherein at least an n-type semiconductor layer, a light-emitting layer, and a p-type semiconductor are formed on the first substrate. Forming a semiconductor layer by sequentially laminating layers, forming a mask layer having processing resistance against blasting on the semiconductor layer, and blasting a portion of the semiconductor layer not covered by the mask layer; A step of dividing the semiconductor layer and forming a plurality of stacked semiconductors having side surfaces made of inclined surfaces formed by the blasting , and a step of forming a sacrificial film so as to be embedded between the stacked semiconductors. The first laminated body is formed by laminating a first bonding layer made of a conductor on the p-type semiconductor layer or on the electrode layer formed on the p-type semiconductor layer and on the sacrificial film. Forming a second stacked body by stacking at least a second bonding layer made of a conductor on a conductive second substrate, and the first stacked body, A step of integrating the second stacked body by bonding the first bonding layer and the second bonding layer; and irradiating the interface between the first substrate and the stacked semiconductor with a laser beam. At least a step of peeling the first substrate from the laminated semiconductor and a step of removing the sacrificial film after peeling the first substrate, and the thickness of the semiconductor layer is in the range of 3 to 15 μm. The blasting is performed using blast particles having a Vickers hardness lower than that of the first substrate, the processing width is 30 to 100 μm, and the average particle size of the blast particles is 5 to 50 μm. Higher than the semiconductor layer Production method for a nitride semiconductor light emitting device which is characterized by using a substrate having a Vickers hardness.
[3] The method for manufacturing a nitride-based semiconductor light-emitting element according to item 1 or 2, wherein the first substrate peeled off from the laminated semiconductor is reused as a substrate for forming the semiconductor layer. .
[4] The nitride-based semiconductor light-emitting device according to any one of items 1 to 3, wherein the semiconductor layer has a Vickers hardness of 90% or less of the Vickers hardness of the first substrate. Method.
[ 5 ] The method for producing a nitride-based semiconductor light-emitting element according to any one of [ 1 ] to [ 4 ], wherein the blast particles are mainly composed of alumina or silicon.
[6] The blasting method for a nitride semiconductor light emitting device according to any one of the preceding 1-5, characterized in that performing by performing patterning with a resist on the semiconductor layer side.
[7] The preceding paragraph 1 to the production method for a nitride semiconductor light emitting device according to any one of 6, wherein the first substrate is a sapphire.
[8] The method for producing a nitride semiconductor light emitting device according to any one of the above 1 to 7, wherein the nitride semiconductor forming the semiconductor layer is characterized in that it is a GaN-based semiconductor.

According to the method for manufacturing a nitride-based semiconductor light-emitting device of the present invention, the nitride-based semiconductor light-emitting device with the above-described configuration can have a side surface of a laminated semiconductor including a light-emitting layer as an inclined surface, and the light extraction efficiency is improved. It can be manufactured and productivity is improved.
According to the present invention, since the first substrate having a Vickers hardness higher than that of the semiconductor layer is used as the substrate for forming the laminated semiconductor, the first substrate may be damaged when sandblasting is performed. Thus, the first substrate can be reused.
As described above, a nitride-based semiconductor light-emitting device having excellent light emission characteristics can be manufactured at low cost.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. The drawings referred to in the following description are for explaining the method of manufacturing the nitride-based semiconductor light-emitting device of the present embodiment. The size, thickness, dimensions, and the like of each part shown in the drawings are the actual nitride-based ones. The dimensional relationship of the semiconductor light emitting device may be different.
Further, the present invention is not limited to the following embodiments, and for example, the constituent elements of these embodiments may be appropriately combined.

“First Embodiment”
In the method of manufacturing a nitride-based semiconductor light-emitting device (hereinafter referred to as a light-emitting device) according to this embodiment, at least an n-type semiconductor layer, a light-emitting layer, and a p-type semiconductor layer are sequentially stacked on a first substrate. A semiconductor layer forming step of forming a layer, a sand blasting step of blasting the semiconductor layer to make the semiconductor layer a laminated semiconductor having a side surface composed of an inclined surface formed by blasting; The second substrate forming step for providing two substrates and the laser lift-off step for irradiating the interface between the first substrate and the laminated semiconductor with laser light to separate the first substrate from the laminated semiconductor.
Hereinafter, each process will be described sequentially.

(Semiconductor layer formation process)
In the semiconductor layer forming step, as shown in FIG. 1, an n-type semiconductor layer 102a, a light emitting layer 102b, and a p-type semiconductor layer 102c are sequentially stacked on a first substrate 101 (first substrate) to form the semiconductor layer 102. Form.

As the first substrate 101, sapphire single crystal (Al ₂ O ₃ ; A plane, C plane, M plane, R plane), spinel single crystal (MgAl ₂ O ₄ ), ZnO single crystal, LiAlO ₂ single crystal, LiGaO ₂ Substrate materials such as single crystals, oxide single crystals such as MgO single crystals, Si single crystals, SiC single crystals, GaAs single crystals, AlN single crystals, GaN single crystals, and boride single crystals such as ZrB ₂ can be used. . In the present invention, any substrate material including these substrate materials can be used without any limitation. Among these, sapphire single crystal (Vickers hardness Hv2300) and SiC single crystal (Vickers hardness Hv2400) are preferable because they have higher Vickers hardness than the semiconductor layer 102 and blast particles described later.

  As the semiconductor layer 102, a known semiconductor light-emitting material such as a GaN-based single crystal, a GaP-based single crystal, a GaAs-based single crystal, or a ZnO-based single crystal can be used, but a sapphire single crystal or SiC constituting the first substrate 101 can be used. A GaN-based single crystal and a ZnO-based single crystal that can be epitaxially grown on the single crystal are more preferable. Furthermore, it is more preferable to use a GaN-based single crystal.

On the first substrate 101, an n-type semiconductor layer 102a, a light emitting layer 102b, and a p-type semiconductor layer 102c made of a GaN-based semiconductor are usually stacked via a GaN layer as a buffer layer. Depending on the substrate used and the growth conditions of the epitaxial layer, the buffer layer may be unnecessary.
As the GaN-based semiconductor, for example, the general formula Al _X Ga _Y In _Z N _1-A M _A (0 ≦ X ≦ 1, 0 ≦ Y ≦ 1, 0 ≦ Z ≦ 1, and X + Y + Z = 1. Symbol M is nitrogen (N) represents another group V element, and 0 ≦ A <1.) Many GaN-based semiconductors represented by this are known, and the present invention includes these well-known GaN-based semiconductors. formula _{Al X Ga Y in Z N 1} -a M a ( and in 0 ≦ X ≦ 1,0 ≦ Y ≦ 1,0 ≦ Z ≦ 1, X + Y + Z = 1. symbol M another is nitrogen (N) A GaN-based semiconductor represented by a group V element and 0 ≦ A <1) can be used without any limitation.
GaN-based semiconductors can contain other group III elements in addition to Al, Ga, and In, and contain elements such as Ge, Si, Mg, Ca, Zn, Be, P, As, and B as required. You can also Furthermore, it is not limited to elements that are intentionally added, but may include impurities that are inevitably included depending on film forming conditions and the like, as well as trace impurities that are included in the raw materials and reaction tube materials.

The growth method of GaN-based semiconductors is not particularly limited, and it is known to grow GaN-based semiconductors such as MOCVD (metal organic chemical vapor deposition), HVPE (hydride vapor deposition), MBE (molecular beam epitaxy). All the methods described can be applied. A preferred growth method is the MOCVD method from the viewpoint of film thickness controllability and mass productivity.
In the MOCVD method, hydrogen (H ₂ ) or nitrogen (N ₂ ) is used as a carrier gas, trimethyl gallium (TMG) or triethyl gallium (TEG) is used as a Ga source as a group III source, and trimethyl aluminum (TMA) or triethyl aluminum is used as an Al source. (TEA), trimethylindium (TMI) or triethylindium (TEI) as an In source, ammonia (NH ₃ ), hydrazine (N ₂ H ₄ ), or the like as an N source that is a group V source. In addition, as a dopant, for n-type, monosilane (SiH ₄ ) or disilane (Si ₂ H ₆ ) is used as a Si raw material, germanium gas (GeH ₄ ) or tetramethyl germanium ((CH ₃ ) ₄ Ge) is used as a Ge raw material. And an organic germanium compound such as tetraethylgermanium ((C ₂ H ₅ ) ₄ Ge) can be used.
In the MBE method, elemental germanium can also be used as a doping source. For the p-type, for example, biscyclopentadienyl magnesium (Cp ₂ Mg) or bisethylcyclopentadienyl magnesium (EtCp ₂ Mg) is used as the Mg raw material.

The n-type semiconductor layer 102a is usually composed of an underlayer, an n contact layer, and an n clad layer. The n contact layer can also serve as an underlayer and / or an n clad layer. Underlayer Al _X Ga _1-X N layer (0 ≦ x ≦ 1, preferably 0 ≦ x ≦ 0.5, and more preferably 0 ≦ x ≦ 0.1) is preferably configured from. The film thickness is 0.1 μm or more, preferably 0.5 μm or more, more preferably 1 μm or more. When the thickness is larger than this, an AlxGa1-XN layer with good crystallinity is easily obtained.
The underlayer may be doped with n-type impurities within the range of 1 × 10 ¹⁷ to 1 × 10 ¹⁹ / cm ³ , but undoped (<1 × 10 ¹⁷ / cm ³ ) is a better crystal. It is preferable in terms of maintaining the property. Although it does not specifically limit as an n-type impurity, For example, Si, Ge, Sn, etc. are mentioned, Preferably it is Si and Ge.
The growth temperature for growing the underlayer is preferably 800 to 1200 ° C, more preferably 1000 to 1200 ° C. If it grows within this growth temperature range, a crystal with good crystallinity can be obtained. The pressure in the MOCVD growth furnace is adjusted to 15 to 40 kPa.

The n contact layer is composed of an Al _x Ga _1-x N layer (0 ≦ x ≦ 1, preferably 0 ≦ x ≦ 0.5, more preferably 0 ≦ x ≦ 0.1), as in the case of the base layer. It is preferable. The n contact layer is preferably doped with an n-type impurity, and the n-type impurity is preferably 1 × 10 ¹⁷ to 1 × 10 ¹⁹ / cm ³ , preferably 1 × 10 ¹⁸ to 1 × 10 ¹⁹ / cm ^3. If it is contained at a concentration of 1, it is preferable in terms of maintaining good ohmic contact with the negative electrode, suppressing the occurrence of cracks, and maintaining good crystallinity. Although it does not specifically limit as an n-type impurity, For example, Si, Ge, Sn, etc. are mentioned, Preferably it is Si and Ge. The growth temperature is the same as that of the underlayer.
The GaN-based semiconductor constituting the n contact layer preferably has the same composition as that of the base layer, and the total film thickness of the n contact layer and the base layer is 1 to 20 μm, preferably 2 to 15 μm, more preferably 3 to 3. It is preferable to set in the range of 12 μm. When the total film thickness of the n-contact layer and the underlayer is in the above range, the crystallinity of the semiconductor is favorably maintained.

It is preferable to provide an n clad layer between the n contact layer and the light emitting layer 3. This is because the deterioration of the flatness generated on the surface of the n contact layer can be filled. The n-clad layer can be formed of AlGaN, GaN, GaInN, or the like. Alternatively, a heterojunction of these structures or a superlattice structure in which a plurality of layers are stacked may be used. Needless to say, when the n-cladding layer is formed of GaInN, it is preferably larger than the band gap of GaInN of the light emitting layer 3.
The thickness of the n-clad layer is not particularly limited, but is preferably 0.005 to 0.5 μm, more preferably 0.005 to 0.1 μm. The n-type doping concentration of the n-clad layer is preferably 1 × 10 ¹⁷ to 1 × 10 ²⁰ / cm ³ , more preferably 1 × 10 ¹⁸ to 1 × 10 ¹⁹ / cm ³ . A doping concentration within this range is preferable in terms of maintaining good crystallinity and reducing the operating voltage of the device.

Next, as the light emitting layer 102b laminated on the n-type semiconductor layer 102a, a light emitting layer made of a GaN-based semiconductor, preferably a Ga _1-s In _s N (0 <s <0.4) GaN-based semiconductor. Is normally used in the present invention. The film thickness of the light emitting layer 102b is not particularly limited, but may be a film thickness to the extent that a quantum effect can be obtained, that is, a critical film thickness, for example, preferably 1 to 10 nm, and more preferably 2 to 6 nm. The film thickness of the light emitting layer 102b is preferably in the above range in terms of light emission output.
In addition to the single quantum well (SQW) structure as described above, the light emitting layer 102b uses the Ga _{1 -s} In _s N as a well layer, and Al _c Ga _{1 −} has a larger band gap energy than the well layer. _It is good also as a multiple quantum well (MQW) structure which consists of cN (0 <= c <0.3) barrier layer. The well layer and the barrier layer may be doped with impurities.

The growth temperature of the Al _c Ga _1-c N barrier layer is preferably 700 ° C. or higher, and more preferably 800 to 1100 ° C., since crystallinity is improved. The GaInN well layer is grown at 600 to 900 ° C., preferably 700 to 900 ° C. That is, in order to improve the MQW crystallinity, it is preferable to change the growth temperature between layers.

Next, the p-type semiconductor layer 102c is usually composed of a p-cladding layer and a p-contact layer. However, the p contact layer may also serve as the p clad layer.
The p-cladding layer is not particularly limited as long as it has a composition larger than the band gap energy of the light-emitting layer 102b and can confine carriers in the light-emitting layer 102b, but is preferably Al _d Ga _1-d N ( 0 <d ≦ 0.4, preferably 0.1 ≦ d ≦ 0.3). When the p-cladding layer is made of such AlGaN, it is preferable in terms of confining carriers in the light emitting layer 102b. The thickness of the p-clad layer is not particularly limited, but is preferably 1 to 400 nm, more preferably 5 to 100 nm. The p-type doping concentration of the p-clad layer is preferably 1 × 10 ¹⁸ to 1 × 10 ²¹ / cm ³ , more preferably 1 × 10 ¹⁹ to 1 × 10 ²⁰ / cm ³ . When the p-type dope concentration is in the above range, a good p-type crystal can be obtained without reducing the crystallinity.

The p-contact layer includes at least Al _e Ga _1-e N (0 ≦ e <0.5, preferably 0 ≦ e ≦ 0.2, more preferably 0 ≦ e ≦ 0.1). Is a layer. When the Al composition is in the above range, it is preferable in terms of maintaining good crystallinity and good ohmic contact with the p ohmic electrode. When a p-type impurity (dopant) is contained at a concentration of 1 × 10 ¹⁸ to 1 × 10 ²¹ / cm ³ , preferably at a concentration of 5 × 10 ^{19 to} 5 × 10 ²⁰ / cm ³ , good ohmic contact is achieved. It is preferable from the standpoints of maintaining the thickness, preventing the occurrence of cracks, and maintaining good crystallinity. Although it does not specifically limit as a p-type impurity, For example, Preferably Mg is mentioned. Although a film thickness is not specifically limited, 0.01-0.5 micrometer is preferable, More preferably, it is 0.05-0.2 micrometer. When the film thickness is within this range, it is preferable in terms of light emission output.

  The Vickers hardness of the semiconductor layer 102 stacked on the first substrate 101 can be measured with a thin film Vickers hardness measuring apparatus.

(Sandblasting process)
Next, in the sand blasting process, the semiconductor layer 102 is blasted so that the semiconductor layer 102 is appropriately divided into the stacked semiconductor 104. The formed laminated semiconductor 104 is provided with a side surface composed of an inclined surface formed by blasting.

First, as shown in FIG. 2, a resist film is attached on the semiconductor layer 102, and the resist film is exposed and developed to remove a portion of the resist film to be blasted to form a mask layer 103. The plan view shape of the mask layer 103 is preferably a rectangular shape such as a square.
Any resist film may be used as long as it has processing resistance to blasting, but it is preferable to use a resist film for blasting. As a commercially available resist film, Odile BF series manufactured by Tokyo Ohka Kogyo Co., Ltd., Sunfort manufactured by Asahi Kasei Electronics, etc. can be used. Moreover, exposure of a resist film can be implemented using an exposure machine similarly to normal photolithography. Furthermore, development of the resist film can be carried out by spraying a sodium carbonate aqueous solution in a shower form.

Next, as shown in FIG. 3, blast particles are sprayed onto the semiconductor layer 102 and the mask layer 103 to perform sandblasting. As a result, the portion of the semiconductor layer 102 that is covered with the mask layer 103 is not processed, and the portion that is not covered with the mask layer 103 is ground by the blast particles, so that the semiconductor layer 102 is divided into a substantially rectangular shape in plan view. The laminated semiconductor 104 is formed. The side surface of the laminated semiconductor 104 becomes an inclined surface 104d by sandblasting.
The shape of the inclined surface by sandblasting may be any shape as long as the shape is inclined as a whole. For example, a taper shape may be sufficient and a single slope shape may be sufficient. The tilt angle is preferably in the range of 20 ° to 70 ° because the light extraction efficiency is further improved.

The blast particles used for the blast treatment may have any shape, but a spherical shape or a needle shape is preferable because a tapered shape can be stably formed, and a spherical shape is more preferable.
The particle size of the blast particles used for the blast treatment varies depending on the processing width and the thickness of the semiconductor layer. In the processing width of 30 to 100 μm and the thickness of the semiconductor layer of 3 to 15 μm, the average particle size of the blast particles is 5 It is preferably ˜50 μm. If it is this range, a favorable taper shape can be created.

  Then, the mask layer 103 is removed as shown in FIG. In this way, the laminated semiconductor 104 having the inclined surface 104d is formed. Between the stacked semiconductors 104, there is no residual semiconductor layer, and the substrate surface 101a of the first substrate 101 is completely exposed to prevent damage to the stacked semiconductor 104 in the laser lift-off process described later. It is preferable in that it can be performed.

    Note that the sandblasting may be performed in a state where the p-type semiconductor layer 104c is laminated, or after the formation of an interdiffusion prevention layer described later. Moreover, you may implement in the process in the middle.

FIG. 5A to FIG. 5C are diagrams schematically illustrating the creation of the inclined surface shape of the side surface of the laminated semiconductor by sandblasting. In the figure, 104 is a blast particle.
When the semiconductor layer 102 is processed using the blast particles 105, the first substrate 101 side is hardly processed by using the blast particles 105 having a Vickers hardness smaller than that of the first substrate 101. Since the shape is a spherical shape or a needle shape, a region that cannot be processed on the side surface of the stacked semiconductor 104 is generated by being blocked by the mask layer 103 and the first substrate 101 as shown in FIGS. . Since the blast particle 105 has a spherical shape or a needle shape as described above, a region that cannot be processed on the side surface of the laminated semiconductor 104 becomes large along the first substrate 101 side, and a tapered processing can be performed.

  On the other hand, even when the hardness of the blast particle 105 is harder than that of the first substrate 101, or when the hardness of the blast particle 105 is smaller than that of the first substrate 101, when the collision speed of the blast particle 105 is extremely high, In this case, the processing proceeds to the first substrate 101 side. In such a case, the tapered shape gradually approaches a right angle with respect to the first substrate 101 as shown in FIG. 6A, and finally the tapered shape disappears as shown in FIG. 6B. End up. Processing to the first substrate 101 side in this way is not preferable for creating a tapered shape.

  In the present invention, the semiconductor layer 102 is processed to form the laminated semiconductor 104 having the inclined surface 104d having a tapered shape without processing the first substrate 101, so that the Vickers hardness of the blast particle 105 is the first substrate 101. It may be harder. However, when the Vickers hardness of the blast particle 105 is harder than that of the first substrate 101, in order to create a tapered shape without almost processing the first substrate 101 side, the protrusion pressure and processing time of the blast particle 105 are set. It must be controlled more strictly. Accordingly, the Vickers hardness of the blast particle 105 is preferably lower than that of the first substrate 101.

  From the above, the Vickers hardness of the semiconductor layer 102 is preferably in the range of 10% to 90% of the Vickers hardness of the first substrate 101. If it exceeds 90%, the difference in Vickers hardness between the first substrate 101 and the semiconductor layer 102 is almost eliminated, so that there is a high possibility that the first substrate 101 is also processed depending on the processing conditions of the semiconductor layer 102. The lower limit is not particularly limited, but is preferably 10% or more in order to prevent damage to the semiconductor layer 102 by pasting or developing a resist film.

  When the semiconductor layer 102 (GaN-based single crystal) epitaxially grown on the first substrate 101 (sapphire single crystal or SiC single crystal) is blasted, alumina and silicon-based blast particles are sapphire single crystal and SiC single crystal. The Vickers hardness is lower than that of the GaN-based single crystal, and the Vickers hardness is about the same as that of the GaN-based single crystal.

In addition, since a difference may arise in a result depending on a measuring method, it is preferable to perform the comparison of the Vickers hardness using the same apparatus. Since the semiconductor layer 102 is a thin film (about 1 to 20 μm), it is preferable to use a Vickers hardness measuring apparatus for the thin film.
The Vickers hardness of the semiconductor layer 102 can be measured with the thin film Vickers hardness measuring apparatus as described above, but it is difficult to measure the Vickers hardness of the blast particles with the same apparatus. The Vickers hardness of the blast particles substitutes the bulk Vickers hardness, but it is difficult to accurately compare this value with the value of the Vickers hardness measuring device for the thin film. Therefore, in reality, it is sufficient that the blast processing is performed under a certain condition and the processing rate for the semiconductor layer 102 is larger than the processing rate for the first substrate 101. It is preferable that the processing rate for the semiconductor layer 102 be three times or more the processing rate for the first substrate 101. Furthermore, 10 times is more preferable.

(Second substrate forming step)
Next, in the second substrate forming step, an ohmic contact layer or the like is formed on the laminated semiconductor, and a second substrate is further provided thereon.

Here, the reason for providing the second substrate will be described.
When a sapphire substrate is used as the substrate for forming the laminated semiconductor 104, since sapphire is an insulator, the first substrate 101 made of sapphire is finally peeled off in order to manufacture a light emitting element having an upper and lower electrode structure. Must.
However, when the first substrate 101 is peeled off, the thickness of the laminated semiconductor is only about 1 to 20 μm, so that the mechanical strength that can withstand the subsequent processing cannot be obtained with the laminated semiconductor 104 alone. In addition, when the blasting process according to the present invention is performed, the semiconductor layer 102 is divided as the laminated semiconductor 104, and if the first substrate 101 is peeled in this state, the laminated semiconductor 104 will be separated.
In order to solve this problem, it is effective to produce another substrate (second substrate) on the side opposite to the first substrate 101. As a method for manufacturing the second substrate (hereinafter referred to as the second substrate), there are a method of manufacturing the second substrate by plating and a method of attaching a conductive silicon or metal substrate as the second substrate. Here, a method of manufacturing the second substrate by plating will be described.

  First, as shown in FIG. 7, the ohmic contact layer 106, the reflective layer 107, and the mutual diffusion prevention layer 108 are formed on the p-type semiconductor layer 104 c of the stacked semiconductor 104.

As the performance required for the ohmic contact layer 106, it is essential that the contact resistance with the p-type semiconductor layer 104c is small. The material of the ohmic contact layer 106 is preferably a platinum group such as Pt, Ru, Os, Rh, Ir, Pd or Ag from the viewpoint of contact resistance with the p-type semiconductor layer 104c. More preferred are Pt, Ir, Rh and Ru. Pt is particularly preferred. Using Ag is preferable for obtaining good reflection, but the contact resistance is lower than Pt. Therefore, Ag can be used for applications that do not require much contact resistance.
The thickness of the ohmic contact layer 106 is preferably 0.1 nm or more in order to stably obtain a low contact resistance. More preferably, it is 1 nm or more, and uniform contact resistance is obtained.

On the ohmic contact layer 106, a reflective layer 107 such as an Ag alloy or an Al alloy is formed. Pt, Ir, Rh, Ru, OS, Pd, and the like have a lower reflectance from visible light to ultraviolet region than Ag alloys. Therefore, it is difficult to obtain an element with high output because the light from the light emitting layer 104b is not sufficiently reflected. In this case, it is better to form the ohmic contact layer 106 thin enough to allow light to pass therethrough, and to form the reflection layer 107 such as an Ag alloy to obtain reflected light, thereby obtaining good ohmic contact and higher output. An element can be created. In this case, the thickness of the ohmic contact layer 106 is preferably 30 nm or less. More preferably, it is 10 nm or less.
The thickness of the reflective layer 107 is preferably 0.1 nm or more in order to obtain a good reflectance. More preferably, it is 1 nm or more, and uniform adhesion is obtained. The Ag alloy is easy to cause migration, so the thinner one is preferable. Therefore, the film thickness is preferably 200 nm or less.

  A method for forming the reflective layer 107 is not particularly limited, and a known sputtering method or vapor deposition method can be used. In the sputtering method, since the sputtered particles collide with the substrate surface with high energy to form a film, a film having high adhesion can be obtained. Therefore, it is more preferable to use the sputtering method.

Next, as illustrated in FIG. 8, a sacrificial layer 109 is formed between the stacked semiconductors 104.
If the second substrate is formed by a plating method without forming the sacrificial layer 109, the inclined surface 104d formed by the sandblasting process is also plated. Since the n-type semiconductor layer 104a and the p-type semiconductor layer 104c are exposed on the inclined surface 104d, the n-type semiconductor layer 104a and the p-type semiconductor layer 104c are short-circuited when plating is performed on those portions. . In order to prevent this, the sacrificial layer 109 may be formed so as to cover the inclined surface 104d before the plating process. The sacrificial layer 109 may be removed after the first substrate 101 is peeled off.

As the sacrificial layer 109, it is preferable to select a material that does not damage the laminated semiconductor 104 made of GaN, the metal layer such as the positive electrode and the negative electrode, and the second substrate that is the plating substrate when the sacrificial layer 109 is removed.
For example, the material of the sacrificial layer 109 is preferably a resist material, resin, ceramics, or the like. In particular, if the resist material is developed, it is more preferable because the groove can be selectively filled as it is, and if a special release material is used, it can be easily removed. When ceramic is used, it is preferable because SiO ₂ can be easily removed by HF. Further, when forming a sacrificial layer made of SiO ₂ , it is preferable to use an SOG (spin-on-glass) material because the groove can be sufficiently filled.

In the case of using a resist as the sacrificial layer 109, it is preferable to form a metal layer to be patterned before filling the groove with the resist. In particular, the ohmic contact layer 106 and the reflective layer 107 are more preferably formed before filling the groove with a resist. This is because since a resist is used for patterning, if the resist is first filled before the groove is filled with the resist, the resist at the groove filling portion is peeled off.
The sacrificial layer 109 is preferably applied by a known method such as a spin coating method, a spray method, or a dip coating method. Furthermore, it is preferable to use a spin coat method from the viewpoint of productivity.
Further, when the sacrificial layer 109 is formed, the sacrificial layer 109 is preferably formed so that the upper surface of the sacrificial layer 109 is flush with the upper surface of the interdiffusion prevention layer 108.
As a method for removing the sacrificial layer 109, a known method such as a wet etching method or a dry etching method can be used without any limitation.

  It is also effective to form a protective film on the inclined surface 104d instead of forming the sacrificial layer 109. As the protective film, silicon oxide, aluminum oxide, or the like can be used.

  Next, as shown in FIG. 9, the plating adhesion layer 110 and the second substrate 111 are formed on the interdiffusion prevention layer 108 and the sacrificial layer 109. Although the mutual diffusion prevention layer 108 may be directly plated, it is preferable to use the plating adhesion layer 110 in order to improve the adhesion of plating.

The material of the plating adhesion layer 110 differs depending on the material of the second substrate 111 formed by plating, but the adhesion is improved when the material mainly contained in the plating component is contained. For example, the plating adhesion layer 110 preferably includes 50% by mass or more of the same composition as the main component occupying 50% by mass or more of the second substrate 111 which is a plating substrate.
For example, when NiP plating is used for the second substrate 111, it is preferable to use a Ni-based alloy for the plating adhesion layer 110. More preferably, a NiP alloy is used. When Cu plating is used for the second substrate 111, it is preferable to use a Cu-based alloy for the plating adhesion layer 110. More preferably, Cu is used.

The thickness of the plating adhesion layer 110 is preferably 0.1 nm or more in order to obtain good adhesion. More preferably, it is 1 nm or more, and uniform adhesion is obtained. The thickness of the plating adhesion layer 110 is not particularly limited, but is preferably 2 μm or less from the viewpoint of productivity.
A method for forming the plating adhesion layer 110 is not particularly limited, and a known sputtering method or vapor deposition method can be used. In the sputtering method, since the sputtered particles collide with the substrate surface with high energy to form the film, a film having high adhesion can be obtained. Therefore, it is more preferable to use a sputtering method.

Next, either electroless plating or electrolytic plating can be applied to the second substrate 111 which is a plating substrate. In the case of electroless plating, NiP alloy plating is preferably used as the material, and in the case of electrolytic plating, Cu is preferably used as the material.
The thickness of the second substrate 111 is preferably 10 μm or more in order to maintain the strength as a substrate. Further, if the second substrate 111 is too thick, peeling of the plating is likely to occur and the productivity is lowered, so that the thickness is preferably 200 μm or less.

  When performing plating, it is preferable to degrease and clean the surfaces of the laminated semiconductor 104, the plating adhesion layer 110, and the like in advance using a general-purpose neutral detergent or the like. Further, it is preferable to remove the natural oxide film on the plating adhesion layer 110 by performing chemical etching on the surface of the plating adhesion layer 110 or the like using an acid such as nitric acid.

As a plating treatment method such as NiP plating, an electroless plating treatment method using a nickel bath such as nickel sulfate or nickel chloride and a phosphorus source such as hypophosphite as a plating bath is employed. be able to. A commercially available product suitable as a plating bath used in the electroless plating method includes Nimden HDX manufactured by Uemura Kogyo. The pH of the plating bath when performing the electroless plating treatment is preferably 4 to 10, and the temperature is preferably 30 to 95 ° C.
Moreover, as a plating treatment method for Cu or Cu alloy, an electrolytic plating treatment method using a Cu source such as copper sulfate can be employed as a plating bath. The pH of the plating bath when performing electroplating is preferably 2 or less under strong acid conditions. The temperature is preferably 10 to 50 ° C., more preferably at room temperature (25 ° C.). The current density is preferably carried out at 0.5~10A / dm ^2, and more preferably carried out in 2~4A / dm ^2.
Moreover, it is more preferable to add a leveling agent in order to smooth the surface. As a commercial item used for the leveling agent, for example, ETN-1-A and ETN-1-B manufactured by Uemura Kogyo are used.

  In order to improve the adhesion of the second substrate 111 obtained as described above, heat treatment may be performed. It is preferable from the point of the adhesive improvement that the heat processing temperature shall be the range of 100-300 degreeC. If the heat treatment temperature is set to the above range or more, the adhesiveness may be further improved, but the ohmic property may be lowered, which is not preferable.

(Laser lift-off process)
Next, in the laser lift-off process, the first substrate 101 is separated from the laminated semiconductor 104 by irradiating the interface between the first substrate 101 and the laminated semiconductor 104 with laser light.
As a peeling method of the first substrate 101, a known technique such as a polishing method, an etching method, or a laser lift-off method can be used without any limitation. In the present invention, from the viewpoint of reusing the first substrate 101, the first substrate 101 is used. It is preferable to use a laser lift-off method that can peel 101 as it is.

When the laser lift-off method is used, it is preferable to use a KrF excimer laser (wavelength 248 nm) or an ArF excimer laser (wavelength 193 nm).
When using a laser lift-off method using an excimer laser, it is preferable to irradiate it as a planar laser beam of an excimer laser. The planar laser beam preferably has a uniform beam profile in the plane. The shape of the surface may be any shape such as a circle or a rectangle, but since the light emitting element is generally a square or a rectangle, the shape of the surface is preferably a rectangle. As for the size of the surface, the length of one side is 100 μm to 5 mm, but when considering the size and productivity of the light emitting element, 300 μm to 2 mm is preferable. Energy density of the laser is preferably 0.3~5J / cm ^2, further, 0.5~2J / cm ² is more preferable.

  FIG. 10 is a plan view of the positional relationship between the laminated semiconductor 104 and the irradiation range of the laser light L as viewed from the first substrate side. As shown in FIG. 10, the outermost peripheral portion (square outer peripheral portion indicated by oblique lines) of the planar laser beam L is irradiated to the divided portion (the portion without the semiconductor layer) of the divided stacked semiconductor 104. It is preferable. As shown in FIG. 11A, when the outermost peripheral portion of the laser beam L is on the laminated semiconductor 104, distortion occurs in that portion, and damage such as a crack K occurs on the laminated semiconductor 104 side. It is because it ends. As shown in FIG. 11B, if there is nothing under the outermost peripheral portion of the laser beam L, no distortion occurs, so that the substrate can be peeled without damaging the laminated semiconductor 104. Further, as shown in FIG. 11C, if the semiconductor layer 104e remains even in a part between the laminated semiconductors 104, distortion occurs in the outermost peripheral portion of the laser light L, and the laminated semiconductor 104 has cracks K and the like. Will cause damage.

  The first substrate 101 (sapphire substrate) after peeling can be reused only by re-polishing for smoothing the surface after peeling if the substrate itself is not damaged. In dry etching or the like, it is difficult to simultaneously remove the residue of the semiconductor layer from the divided portion and to prevent damage to the sapphire substrate. On the other hand, in the present invention, the sapphire substrate is hardly processed, and only the laminated semiconductor 104 can be completely removed. Therefore, this problem can be easily solved. By using the present invention, the first substrate 101 can be reused by polishing the surface of the first substrate 101 after peeling off the substrate by at least about 1 μm.

Then, a negative electrode 113 is formed on the n-type semiconductor layer 104 a exposed by peeling the first substrate 101, and a positive electrode 112 is formed on the second substrate 111. Then, by dividing the second substrate 111 for each element, a light emitting element 114 having an upper and lower electrode structure as shown in FIG. 12 is obtained.
As the dividing method, a known technique such as a laser scribing method or a dicing method can be used without any limitation.
Moreover, the positive electrode 112 has various structures using materials such as Au, Al, Ni and Cu, and these known materials can be used without any limitation. Moreover, as the negative electrode 113, negative electrodes having various compositions and structures are known, and these known negative electrodes can be used without any limitation.

“Second Embodiment”
The method for manufacturing a light-emitting element according to this embodiment includes a semiconductor layer forming step of forming a semiconductor layer by sequentially stacking at least an n-type semiconductor layer, a light-emitting layer, and a p-type semiconductor layer on a first substrate; Forming the semiconductor layer on the p-type semiconductor layer or on the p-type semiconductor layer by blasting the layer to form the semiconductor layer on the p-type semiconductor layer having a side surface composed of an inclined surface formed by the blasting; A first laminated body forming step of forming a first laminated body by laminating a first bonding layer made of a conductor on the electrode layer, and at least a conductor on the second substrate having conductivity By laminating the second bonding layer comprising: a second stacked body forming step of forming the second stacked body; the first stacked body and the second stacked body; Bonding two bonding layers It is configured to include at least a joining step for further integration and a laser lift-off step for irradiating the interface between the first substrate and the laminated semiconductor with laser light to separate the first substrate from the laminated semiconductor. .

  Hereinafter, each step will be described in order, but among the above steps, the semiconductor forming step, the sandblasting step, and the laser lift-off step are the same as the steps in the first embodiment, and therefore the description is omitted or simplified. Explained.

In FIG. 13, the outline of the manufacturing method of the light emitting element of this embodiment is shown. In FIG. 13, (A)-(C) show the steps of the manufacturing procedure.
In FIG. 13, in step (A), a laminated semiconductor 204 made of a GaN-based semiconductor in which an n-type semiconductor layer, a light emitting layer, and a p-type semiconductor layer are sequentially laminated is formed on a first substrate 201, and an ohmic contact layer is further formed. After forming the functional layer 205 composed of the reflective layer and the mutual diffusion prevention layer, the first bonding layer 206 composed of metal is formed as the uppermost layer, and the first laminated body 200 is obtained.
In addition, after forming the intermediate layer 302 on the second substrate (conductive substrate) 301, the second bonding layer 303 is formed on the intermediate layer 302 to form the second stacked body 300.

As the crystal structure and crystal orientation of the bonding interface between the first bonding layer 206 and the second bonding layer 303 are aligned, the stability at the time of bonding increases, so that the bonding strength increases. Ideally, if the same material is used and has the same crystal structure and the crystal orientation is aligned in the direction perpendicular to the plane, the crystal strain or the like does not occur at the bonding interface, so that it is considered that the bulk equivalent strength is generated.
Accordingly, it is preferable that the first bonding layer 206 and the second bonding layer 303 are substantially the same material and have the same crystal orientation in the direction perpendicular to the bonding surface, since the bonding strength increases.
Further, it is more preferable that the first bonding layer 206 and the second bonding layer 303 have the same crystal structure, and the crystal strength in the direction perpendicular to the bonding surface and the direction in the bonding surface is the same, because the bonding strength increases.
Furthermore, if the first bonding layer 206 and the second bonding layer 303 have the same material and the same crystal structure, and the crystal orientations in the direction perpendicular to the bonding surface and the direction in the bonding surface are the same, the bonding strength increases. More preferred.
The substantially same material means that the concentration of the same material in the first bonding layer 206 and the second bonding layer 303 is 50 at% or more, has the same crystal structure, and has a lattice constant difference within 5%. Is defined as being.
Further, it is more preferable that the first bonding layer 206 and the second bonding layer 303 have the same crystal structure, and the difference between the lattice constants of the first bonding layer and the second bonding layer 303 is within 5%.
Furthermore, it is more preferable if the first bonding layer 206 and the second bonding layer 303 are the same material.
For example, if the first bonding layer 206 is an Au (111) surface, the second bonding layer 303 is most preferably Au (111).

In the next step (B), the first stacked body 200 and the second stacked body 300 are integrated by bonding the first bonding layer 206 and the second bonding layer 303 together.
Subsequently, in step (C), after removing the first substrate 201 from the first stacked body 200, an electrode (not shown) is provided to form the light emitting element 400.
Here, the functional layer 205 is provided in the first stacked body 200 and the intermediate layer 302 is provided in the second stacked body 300. However, the functional layer 205 and the intermediate layer 302 can be omitted, and if necessary. The layer is appropriately provided. As will be described later, the functional layer 205 can be a laminate composed of an ohmic contact layer, a reflective layer, and an interdiffusion prevention layer, and the intermediate layer 302 is composed of an orientation adjustment layer, an interdiffusion prevention layer, and a lattice matching layer. A laminate can be used.

  As shown in FIG. 13C, the GaN-based semiconductor light-emitting element 1 manufactured by the above procedure is a stacked layer having a stacked semiconductor 204 made of a GaN-based semiconductor and a first bonding layer 206 made of metal as the uppermost layer. 200 </ b> A and a second bonding layer 303 bonded to the first bonding layer 206. The second bonding layer 303 is formed on the second substrate 301 and the surface opposite to the side on which the second substrate 301 is formed is bonded to the first bonding layer 206.

(Semiconductor layer formation process-1st laminated body formation process)
Next, with reference to FIGS. 14-18, the light emitting element of the upper-lower electrode structure by the board | substrate sticking method produced using the 1st board | substrate which consists of a sapphire single crystal, and its manufacturing method are demonstrated in detail.
FIG. 14 is a diagram schematically showing a cross section of a configuration example of the first stacked body 200. In the figure, on a first substrate 201 made of sapphire, a laminated semiconductor 204 made up of an n-type semiconductor layer 204a, a light emitting layer 204b and a p-type semiconductor layer 204c, an ohmic contact layer 205a, a reflective layer 205b, and an interdiffusion prevention layer 205c. A functional layer 205 made of the above and a first bonding layer 206 are laminated to form a first laminated body 200.

As in the case of the first embodiment, the stacked semiconductor 204 can be formed by sequentially stacking an n-type semiconductor layer 204a, a light emitting layer 204b, and a p-type semiconductor layer 204c.
Since the n-type semiconductor layer 204a, the light emitting layer 204b, and the p-type semiconductor layer 204c are all GaN-based single crystals, in order to control the crystal orientation of the first bonding layer 206, the ohmic contact layer 205a and the reflective layer 205b There is also a need to control the crystal orientation.
The crystal structure of GaN is a wurtzite structure, and the lattice constants are a = 3.16Å (0.316 nm) and c = 5.13Å (0.513 nm). Since the p-type semiconductor layer 204c in contact with the ohmic contact layer 205a is doped with Al, the lattice constant fluctuates. However, since the addition amount is at most about 10%, the lattice constant is approximately a = 3.16Å (0 (The crystal structure of AlN is also a wurtzite structure, and the lattice constants are a = 3.08 Å (0.308 nm) and c = 4.93 Å (0.493 nm), so the added amount is about 10%. Then the lattice constant is almost the same.)

When the first substrate 201 is a sapphire single crystal, the stacked semiconductor 204 (n-type semiconductor layer 204a, light-emitting layer 204b, p-type semiconductor layer 204c) made of a GaN-based single crystal stacked on the first substrate 201 is ( (00 · 1) orientation, the ohmic contact layer 205a, the reflective layer 205b, and the first bonding layer 206 laminated thereon have a hexagonal (00 · 1) plane or a face-centered cubic crystal. It preferably has a (111) plane.
In order for the hexagonal (00 · 1) plane to be oriented on the (00 · 1) orientation of the GaN-based single crystal, the difference in lattice constant is preferably within 20%. Within this range, the crystal direction can be aligned in the direction perpendicular to the joint surface. Since the lattice constant of GaN is a = 3.16Å (0.316 nm), the hexagonal lattice constant used for the ohmic contact layer 205a, the reflective layer 205b, and the first bonding layer 206 is a = 2.53Å (0 .253 nm) to 3.79 mm (0.379 nm). Since the orientation is (00 · 1), the lattice constant c may take any value.

  Since the laminated semiconductor 204 is a semiconductor composed of a GaN-based single crystal, the hexagonal shape is regularly arranged as shown in FIG. Therefore, in order to align the crystal orientation in the in-plane direction, it is preferable to use a single crystal whose crystal orientation is originally aligned in the in-plane direction. In order to align the crystal orientation in the in-bonding direction, it is preferable that the difference in lattice constant is within 20% as in the case of the straight direction of the bonding surface. Note that aligning the crystal orientation in the in-bonding direction means that a regular crystal structure in the bonding surface is maintained. For example, since the GaN single crystal is a hexagonal crystal, when the (00 · 1) plane is oriented, the regularity of the object six times is maintained in the in-plane direction. In this case, the regularity of the object six times is also maintained in the bonding layer.

  As shown in FIG. 15, the face-centered cubic (111) plane has the same crystal plane as the hexagonal (00 · 1) plane. 1 / √2 of the lattice constant a of the face-centered cubic system corresponds to the lattice constant a of the hexagonal system. As in the case of the hexagonal system, the difference in lattice constant is preferably within 20%. Therefore, the lattice constant of the face-centered cubic system used for the ohmic contact layer 205a, the reflective layer 205b, and the first bonding layer 206 is a = The range of 3.58 mm (0.358 nm) to 5.36 mm (0.536 nm) is preferable. Within this range, when using a GaN-based single crystal, the crystal orientations in the direction perpendicular to the joint surface and the direction in the joint surface can be aligned.

  Note that “·” in the crystal plane notation indicates an abbreviation of the Miller Bravay index representing the crystal plane. That is, in the hexagonal system such as GaN to represent the crystal plane, it is represented by normal (hkil) and four indices, and among these, “i” is defined as i = − (h + k). In a format in which “i” is omitted, it is expressed as (hk · l).

Next, as the performance required for the ohmic contact layer 205a, it is essential that the contact resistance with the p-type semiconductor layer 204c is small. However, in the present invention, the crystal structure and the lattice constant are within the above-mentioned ranges. It is preferable.
As a material of the ohmic contact layer 205a, Pt (face-centered cubic structure a = 3.93Å (0.393 nm)), Ru from the viewpoint of contact resistance with the p-type semiconductor layer 204c, and from the viewpoint of crystal structure and lattice constant. (Hexagonal closest packed structure a = 2.70 Å (0.270 nm)), Re (Hexagonal closest packed structure a = 2.76 ＝ (0.276 nm)), Os (Hexagonal closest packed structure a = 2.74 Å ( 0.274 nm,)), Rh (face-centered cubic structure a = 3.80 Å (0.380 nm)), Ir (face-centered cubic structure a = 3.84 Å (0.384 nm)), Pd (face-centered cubic) It is preferable to use a platinum group such as crystal structure a = 3.89Å (0.389 nm)) or Ag (face-centered cubic crystal structure a = 4.09Å (0.409 nm)). More preferred are Pt, Ir, Rh and Ru, with Pt being particularly preferred.

The use of Ag for the ohmic contact layer 205a is preferable for obtaining good reflection, but the contact resistance is larger than Pt. Therefore, Ag can be used for applications that do not require much contact resistance.
The thickness of the ohmic contact layer 205a is preferably 0.1 nm or more in order to stably obtain a low contact resistance. More preferably, it is 1 nm or more, and uniform contact resistance is obtained. Further, since the ohmic contact layer 205a has a lower reflectance than an Ag alloy or the like, the film thickness is preferably 30 nm or less. More preferably, it is 10 nm or less.

  Next, Ag, Al (face-centered cubic structure a = 4.05Å (0.405 nm)), or the like can be used for the reflective layer 205b. In addition, it is effective to add Mo, Cu, Nd or the like to Ag in order to improve corrosion resistance and temperature resistance. Since the amount of addition is 5 at% or less for any element, the lattice constant does not change significantly. It is effective to add Nd or the like to Al in order to improve the flatness. Since the amount of addition is 5 at% or less for any element, the lattice constant does not change significantly.

Next, the first bonding layer 206 has a lattice structure and a lattice constant of a = 2.53Å (0.253 nm) to 3.79Å (0.379 nm) in the hexagonal system, or a = in the face-centered cubic system. Any single metal or alloy may be used as long as it is 3.58 nm (0.358 nm) to 5.36 mm (0.536 nm), but an inert gas ion beam or an inert gas in a vacuum at the time of bonding. A metal whose surface is easily activated by irradiation with a neutral atom beam is preferable. The activation means that the surface impurities are removed and the dangling bonds are exposed. Since the surface of metal is often oxidized in the atmosphere, the oxide film can be easily removed with a smaller affinity with oxygen. Therefore, it is preferable to use a noble metal.
The metal used for the first bonding layer 206 is preferably a single metal such as Au, Ag, Ir, Pt, Pd, Rh, Ru, Re, or Cu, or an alloy containing at least two of these metals. .

  An interdiffusion prevention layer 205c is preferably provided between the reflective layer 205b and the first bonding layer 206 in order to improve adhesion between the reflective layer 205b and the first bonding layer 206 and to prevent mutual diffusion. The interdiffusion prevention layer 205c may be omitted. Even when these layers are provided, the lattice structure and the lattice constant of the single metal or alloy constituting the layers are a = 2.53Å (0.253 nm) to 3.79Å (0.379 nm) or hexagonal system. In the face-centered cubic system, a is required to be 3.58 (0.358 nm) to 5.36 (0.536 nm). For example, when Ag is used for the reflective layer 205b and Au is used for the first bonding layer 206, Ag and Au are completely dissolved, causing mutual diffusion. In order to prevent this, the interdiffusion prevention layer 205c is made of Pt, Ru, Re, Os, Rh, Ir, Pd, Ti (hexagonal close-packed structure a = 2.95Å (0.295 nm)), Hf (hexagonal close-packed packing). Structures a = 3.20 Å (0.320 nm)), Zr (hexagonal close-packed structure a = 3.23 Å (0.323 nm)), and the like can be used.

Sandblasting for the stacked semiconductor 204 may be performed in a state where the p-type semiconductor layer 304c is stacked, or after the first bonding layer 206 is formed. Moreover, you may implement in the process in the middle. A specific processing method may be the same as in the case of the first embodiment.
The shape of the inclined surface 204d by sandblasting may be any shape as long as it is inclined. For example, a tapered surface shape or a single slope shape may be used. The tilt angle is preferably in the range of 20 ° to 70 ° because the light extraction efficiency is further improved.

(Second laminated body forming step)
In FIG. 16, the cross section of the structural example of the 2nd laminated body 300 is shown typically. In the drawing, an amorphous layer or lattice matching layer 302 and a second bonding layer 303 are sequentially stacked on a conductive second substrate 301 to form a second stacked body 300. Note that the lattice matching layer or the alignment adjustment layer 302 is not particularly required as long as the lattice matching between the second substrate 301 and the second bonding layer 303 is ensured.
Any material can be used for the second substrate 301 as long as it has conductivity, but it is preferable to use metal or silicon having conductivity. Any material can be used as long as it is metal, but Cu or Cu alloy having high thermal conductivity is preferably used. Silicon is inferior to metals such as Cu in terms of thermal conductivity, but if silicon (111) is used, it is easy to control crystal orientation and good workability when dividing a GaN-based semiconductor light-emitting device into elements. Have.

Although it is possible to use a metal single crystal substrate for the second substrate 301, the cost increases. Therefore, it is preferable to use a metal substrate that is polycrystalline and does not have a uniform crystal orientation. However, if the second bonding layer 303 is formed directly on a polycrystalline metal substrate having a uniform crystal orientation, it is affected by the crystal plane of the metal, resulting in a hexagonal (00 · 1) plane or face-centered cubic. Crystalline (111) planes cannot be preferentially grown.
In order to suppress the influence of a polycrystalline metal substrate having a uniform crystal orientation, it is preferable to form the amorphous layer 302 before the second bonding layer 303 is formed. Any material can be used for the amorphous layer 302 as long as it is an amorphous metal. However, the hexagonal (00 · 1) plane or the face-centered cubic system of the second bonding layer 302 can be used. It is preferable that the (111) plane has a property of preferentially growing.
Specifically, it is a metal containing at least one selected from Co, Ni and Fe and at least one selected from W, Mo, Ta and Nb, or selected from Ru and Re. It is preferable that it is a metal containing any one or more types and one or more types selected from W, Mo, Ta and Nb.
More specifically, CoW alloy, CoMo alloy, CoTa alloy, CoNb alloy, NiW alloy, NiMo alloy, NiTa alloy, NiNb alloy, FeW alloy, FeMo alloy, FeTa alloy, FeNb An alloy based on Ru, RuW, RuMo, RuTa, RuNb, ReW, ReMo, ReTa, or ReNb is preferred.

  For the same reason as the first bonding layer 206, the second bonding layer 303 is a single metal such as Au, Ag, Ir, Pt, Pd, Rh, Ru, Re, Cu, or an alloy containing at least two kinds of these metals. It is preferable that

  A crystallinity improving layer may be provided between the amorphous layer 302 and the second bonding layer 303 in order to increase the crystallinity of the second bonding layer 303. However, even when these layers are provided, the lattice structure and lattice constant of the single metal or alloy constituting the layer is a = 2.53 (0.253 nm) to 3.79 (0.379 nm) in the hexagonal system. Alternatively, it is necessary that a = 3.58? (0.358nm) to 5.36? (0.536nm) in a face-centered cubic system. Pt, Ru, Re, Os, Rh, Ir, Pd, Ti, Hf, Zr, and the like can be used for the crystallinity improving layer, but it is particularly preferable to use Pt because (111) is preferable.

When the amorphous layer 302 is used, the crystallinity in the direction perpendicular to the plane can be controlled, but the crystallinity in the in-plane direction cannot be controlled. By controlling the crystallinity in the in-plane direction in addition to the perpendicular direction, the bonding strength can be further improved.
Although the control of the perpendicular direction and the in-plane direction can be performed by using a single crystal substrate as the second substrate, it is preferable to use the (111) plane of silicon single crystal in consideration of bonding with the first bonding layer 206. .
When the (111) plane of the silicon single crystal having conductivity is used, the atomic arrangement of the (111) plane of the silicon single crystal is the same as the atomic arrangement of the GaN (00 · 1) plane, so that Au, Ag, Cu , Pt, Pd, Rh, Cu, Ir, etc., and the (111) plane of the center-centered cubic structure, and the six-method closest packing (00 · 1) such as Ru, Re, etc. are easily oriented. However, since the lattice constant a of Au having a face-centered cubic structure is 4.08 Å (0.408 nm), the lattice constant a of Si is shifted to 5.43 Å (0.543 nm) by 25%. It is not easy to orient the (111) plane of the center cubic structure. Even in the six-method close-packing such as Ru and Re, the lattice constant is large, and it is not easy to orient (00 · 1).
A face-centered cubic structure (111) surface such as Au, Ag, Cu, Pt, Pd, Rh, Cu, and Ir, and six-method closest packing (00 · 1) such as Ru and Re are grown on Si (111). There are two ways to do this.

One method is to sufficiently clean the surface of a silicon single crystal substrate having a (111) plane by RCA cleaning or the like, then terminate the surface with hydrogen fluoride or the like, and then form a film having an ultrahigh vacuum. It is forming into a film using an apparatus. The concentration of dilute hydrofluoric acid is preferably about 0.1 to 2% by mass, and the silicon single crystal substrate surface having the (111) plane can be hydrogen-terminated by performing the treatment for about 1 to 20 minutes. RCA cleaning is preferable because it has a function of making the surface oxide film uniform, and the surface of the Si single crystal after hydrogen termination can be further planarized. If an impurity gas such as oxygen or nitrogen is present during the film formation, a clean cleaning surface cannot be maintained. Therefore, the ultimate vacuum degree of the vacuum device is preferably higher. The ultimate vacuum is preferably 1.0 × 10 ^{−4 to} 1.0 × 10 ⁻⁸ Pa. Furthermore, 5.0 * 10 < ^-5 > -1.0 * 10 < ^-6 > Pa is preferable. The higher the vacuum, the easier the epitaxial growth, but in order to achieve 1.0 × 10 ⁻⁸ Pa with the vacuum device, an exhaust system with a large displacement is provided or the vacuum device is baked for a long time. There is a lack of efficiency. If the surface of the silicon single crystal substrate having the (111) plane is hydrogen-terminated, the vacuum is higher than 1.0 × 10 ⁻⁴ Pa, more preferably higher than 5.0 × 10 ⁻⁵ Pa. Good epitaxial growth can be realized.

Since Ag does not form silicide with Si, it is most easily possible to realize good epitaxial growth on the surface of a silicon single crystal substrate having a (111) plane.
When Ag is formed on the surface of a silicon single crystal substrate having a (111) plane, it can be used as it is as the second bonding layer 303, but it is more preferable to use Au which is less oxidizable as the second bonding layer 303. . In this case, since Ag and Au are completely dissolved, mutual diffusion occurs. In order to prevent this, Pt, Ru, Re, Os, Rh, Ir, Pd, Ti (hexagonal close-packed structure a = 2.95Å (0.295 nm)), Hf (hexagonal close-packed structure) a = 3.20 cm (0.320 nm)), Zr (hexagonal close-packed structure a = 3.23 cm (0.323 nm)), or the like can be used.

Another technique is to use a lattice matching layer.
The lattice matching layer has a hexagonal close-packed structure, and the deviation from the corresponding side length a / √2 of 3.84 mm (0.384 nm) within the Si (111) plane is within 20%. , (00 · 1) having a hexagonal close-packed structure is preferably oriented on the Si (111) plane. Further, since Si uses a single crystal, the crystal orientation can be aligned in the in-bonding direction if the difference in lattice constant is within 20%.
As the lattice matching layer, Hf (hexagonal close-packed structure, a = 3.20Å (0.320 nm)), Mg (hexagonal close-packed structure, a = 3.21Å (0.321 nm)), Zr (hexagonal close-packed structure) Using a close-packed structure, a = 3.23 Å (0.323 nm)) has a 20% deviation from the corresponding side length a / √2 of 3.84 ａ (0.384 nm) of the Si (111) surface. Is preferable.

It is preferable to remove the surface oxide film from the Si substrate before forming the lattice matching layer. If the surface oxide film exists, it is possible to remove the significant inhibition of crystal growth reflecting the Si (111) plane. As a method for removing the surface oxide film, it is preferable to use a method such as bias etching in a vacuum apparatus.
When Hf, Mg, Zr is used as the lattice matching layer, the hexagonal (00 · 1) plane is oriented on the (00 · 1) orientation of the lattice matching layer Hf, Mg, Zr. The lattice constant difference is preferably within 20%. Within this range, the crystal direction can be aligned in the direction perpendicular to the joint surface. Therefore, the hexagonal lattice constant used for the bonding layer 2 is preferably a = 2.58 (0.258 nm) to 3.84 (0.384 nm). Since the orientation is (00 · 1), the lattice constant c may take any value.

  As shown in FIG. 15, the face-centered cubic (111) plane has the same crystal plane as the hexagonal (00 · 1) plane. 1 / √2 of the lattice constant a of the face-centered cubic system corresponds to the lattice constant a of the hexagonal system. As in the case of the hexagonal system, the difference in lattice constant is preferably within 20%. Therefore, the lattice constant of the face-centered cubic system used for the second bonding layer 303 is a = 3.65Å (0.365 nm) to It is preferably 5.42 mm (0.542 nm). Within this range, it is possible to align the crystal orientation directly on the bonding surface and within the bonding surface on the lattice matching layer.

  Even when the lattice matching layer is used, the second bonding layer 303 is a single metal such as Au, Ag, Ir, Pt, Pd, Rh, Ru, Re, or Cu, or an alloy containing at least two kinds of these metals. However, considering the orientation with the lattice matching layer, it should be a single metal such as Au, Ag, Ir, Pt, Pd, Rh, Ru, Re, or an alloy containing at least two of these metals. Is more preferable.

(Joining process)
FIG. 17 is a schematic diagram for explaining a process of bonding the first stacked body 200 and the second stacked body 300. Bonded samples (first stacked body 200 and second stacked body 300) to be bonded to each of the two substrate holders 401 and 401 are attached, and the surface of each bonded sample (the bonded surface of the first bonding layer 206, the first stacked layer). (2) the inert gas ion beam or the inert gas neutral atom beam is irradiated from the inert gas beam source 403 toward the bonding surface of the bonding layer 303, and then the bonding surfaces of the bonding samples are superimposed.
Any bonding method can be used as long as bonding is performed in a state where the surfaces of the bonding layers 206 and 303 are activated in a vacuum (dangling bonds are exposed). However, as described above, it is preferable to overlap the bonding surfaces after irradiation with an inert gas ion beam or an inert gas neutral atom beam.

After irradiation with an inert gas ion beam or an inert gas neutral atom beam, it takes a certain time (for example, 1 second to 60 seconds) to overlap the bonding surfaces. Contamination of the surface of 303 is a concern. For this reason, it is preferable to reduce the amount of impurity gases by setting the ultimate vacuum in the vacuum apparatus to 10 ⁻⁴ Pa or less. More preferably, it is 10 < ^-5 > Pa or less.
It is preferable to apply pressure at the time of bonding because the bonding strength is improved. The pressure for pressurization is preferably 0.1 to 100 MPa. If the pressure is less than 0.1 MPa, the pressure is too weak to obtain sufficient bonding strength. If it exceeds 100 MPa, the substrate may be damaged. More preferably, it is 1-10 MPa.
Any gas can be used as the inert gas as long as it is inert, but it is preferable to use He, Ne, Ar, Kr, or Xe. In particular, Ar is more preferable because it can be obtained at low cost.
Heating at the time of bonding or after bonding is preferable in order to increase the bonding strength. However, when the first substrate 201 is sapphire and the second substrate 301 is a silicon single crystal or metal, it is preferable that the temperature is 200 ° C. or less because sapphire and silicon or metal have a large difference in thermal expansion coefficient.

(Laser lift-off process)
In the laser lift-off process, the first substrate 201 is separated from the laminated semiconductor 204 by irradiating the interface between the first substrate 201 and the laminated semiconductor 204 with laser light.
As a peeling method of the first substrate 201, a known technique such as a polishing method, an etching method, or a laser lift-off method can be used without any limitation. In the present invention, from the viewpoint of reusing the first substrate 201, the first substrate 201 is used. It is preferable to use a laser lift-off method that can peel 201 as it is.
The specific procedure of the laser lift-off method may be performed in the same manner as in the first embodiment.

Then, a negative electrode 208 is formed on the n-type semiconductor layer 204 a exposed by peeling off the first substrate 201, and a positive electrode 207 is formed on the second substrate 301. Then, by dividing the second substrate 301 for each element, a light emitting element 400 having an upper and lower electrode structure as shown in FIG. 18 is obtained.
As the dividing method, a known technique such as a laser scribing method or a dicing method can be used without any limitation.
Further, the positive electrode 207 has various known structures using materials such as Au, Al, Ni, and Cu, and these known materials can be used without any limitation. As the negative electrode 208, negative electrodes having various compositions and structures are known, and these known negative electrodes can be used without any limitation.

Next, a case where a lamp is configured using the light emitting element 400 will be described.
FIG. 19 is a cross-sectional view schematically showing an example of a lamp (bullet type) according to the present invention. The lamp shown in FIG. 19 has the upper and lower electrode type light emitting elements 1605 shown in FIG. 18 mounted thereon, and can be manufactured by a conventionally known method except that this light emitting element 1605 is used. Specifically, for example, of the two frames 1602A and 1602B, the positive electrode of the light emitting element 1605 is bonded to the frame 1602B with a conductive adhesive such as silver paste, and the negative electrode of the light emitting element 1605 is framed with a wire 1603 made of gold. After bonding to 1602A, the periphery of the light-emitting element 1605 can be molded with a mold 1604 made of a transparent resin.

As described above, according to the method for manufacturing the light emitting elements 114 and 400 according to the embodiment of the present invention, the side surfaces of the stacked semiconductors 104 and 204 including the light emitting layers 104b and 204b can be the inclined surfaces 104d and 204d. In addition, the light emitting elements 114 and 400 with improved light extraction efficiency can be manufactured, and productivity can be improved.
Moreover, since the 1st board | substrates 101 and 201 which have higher Vickers hardness than a semiconductor layer are used as a board | substrate at the time of forming the laminated semiconductors 104 and 204, when the sandblasting was performed, the 1st board | substrates 101 and 201 were damaged. There is no risk of receiving it, so that the first substrates 101 and 201 can be reused.
As described above, the light-emitting elements 114 and 400 having excellent light-emitting characteristics can be manufactured at low cost.

Example 1
As described below, the light emitting device having the upper and lower electrode structures shown in FIG. 18 was manufactured, and the light emission output was measured.
First, a buffer layer made of AlN was formed on a first substrate made of sapphire single crystal, and a semiconductor layer made of a gallium nitride (GaN) -based compound semiconductor was formed on the buffer layer. This semiconductor layer is formed by laminating a base layer made of undoped GaN having a thickness of 4 μm, a Ge-doped n-type GaN contact layer having a thickness of 2 μm, and an n-type In _0.1 Ga _0.9 N cladding layer having a thickness of 0.02 μm in this order. A light emitting layer having a multiple quantum well structure in which an n-type semiconductor layer, a Si-doped GaN barrier layer having a thickness of 16 nm and an In _0.06 Ga _0.94 N well layer having a thickness of 2.5 nm are stacked five times, and finally a barrier layer is provided. And a p-type semiconductor layer in which a Mg-doped p-type Al _0.07 Ga _0.93 N cladding layer having a thickness of 0.01 μm and a Mg-doped p-type Al _0.02 Ga _0.98 N contact layer having a thickness of 0.18 μm are stacked in this order. It was formed by sequentially laminating.
In this structure, the carrier concentration of the n-type GaN contact layer is 1 × 10 ¹⁹ cm ⁻³ , the Si doping amount of the GaN barrier layer is 1 × 10 ¹⁷ cm ⁻³ , and the carrier concentration of the p-type AlGaN contact layer is 5 a × 10 ¹⁸ cm ^-3, Mg doping amount of p-type AlGaN cladding layer was 5 × 10 ¹⁹ cm ^-3.
The layers of the semiconductor layers were stacked by MOCVD under normal conditions well known in the technical field.

Next, a Pt layer having a thickness of 1.5 nm was formed as an ohmic contact layer on the p-type semiconductor layer by a sputtering method.
Next, an Ag layer having a thickness of 20 nm as a reflective layer, a Pt layer having a thickness of 20 nm as an anti-diffusion layer, and an Au layer having a thickness of 20 nm as a first bonding layer are formed in this order by sputtering, so that the first A laminate was formed.

Next, the semiconductor layer was processed into a laminated semiconductor having an inclined surface by using a sandblast method.
First, a resist film (BF 45Z manufactured by Tokyo Ohka) was adhered to the surface of the semiconductor layer. Next, the resist film was exposed with a predetermined pattern using an exposure machine. Next, the resist film was removed leaving a 350 μm square lattice pattern. The interval between the lattice patterns was 50 μm. Then, development was performed using an aqueous sodium carbonate solution.
Next, blasting was performed using white alundum (Vickers hardness 2000) having an average particle diameter of 20 μm using a sand blasting apparatus. Thereafter, the resist film and the blast particle residue were removed by ultrasonic cleaning.
As described above, a laminated semiconductor having an inclined surface was formed.

  A cross-sectional SEM photograph of the laminated semiconductor subjected to blasting is shown in FIG. 20, and a planar SEM photograph is shown in FIG. As shown in FIG. 20, it can be seen that an inclined surface with an inclination angle of 45 degrees can be formed in the semiconductor layer 302 on the first substrate 301.

Next, a second substrate made of a Si single crystal having a (111) plane on the surface is prepared, and a 50 nm Ag layer, a 20 nm Pt layer, and a 20 nm Au layer as a second bonding layer are prepared on the second substrate. The layers were formed by sputtering in this order. In this way, a second laminate was formed. Note that before the Ag film was formed on the Si substrate (second substrate), RCA cleaning was performed, and the substrate was treated with dilute hydrofluoric acid (0.5 mass%) for 10 minutes. The ultimate vacuum of the sputtering apparatus was 1.0 × 10 ⁻⁵ Pa.

Next, the first stacked body and the second stacked body were bonded in a vacuum apparatus by overlapping the bonding surfaces of the first bonding layer and the second bonding layer. At this time, the ultimate degree of vacuum in the vacuum apparatus was 1.0 × 10 ⁻⁵ Pa, and each bonding surface was irradiated with an Ar gas neutral atom beam for 1 minute, and then pressed and bonded at a pressure of 5 MPa. In addition, the heating process was not performed at the time of joining and before and after joining.
Next, a laser lift-off method was applied to the joined body of the first stacked body and the second stacked body to remove the first substrate. An ArF excimer laser was used for the laser lift-off method, and the laser irradiation area per shot was set to 700 μm × 700 μm, and the energy density was 1000 mJ / cm ² .

Next, the buffer layer made of AlN and the base layer made of undoped GaN were removed by a dry etching method to expose the n-type semiconductor layer.
Next, a negative electrode made of Cr (40 nm), Ti (100 nm), and Au (1000 nm) was formed on the central portion on the surface of the n-type semiconductor layer by vapor deposition. A known photolithography technique and lift-off technique were used for the negative electrode pattern.
A positive electrode made of Au (1000 nm) was formed on the surface of the second substrate by a vapor deposition method.
Then, it was divided by dicing to obtain a 350 μm square light emitting device as shown in FIG.

  About the obtained light emitting element, it mounted in the TO-18 can package, and the light emission output in 20 mA of applied currents was measured with the tester. As a result, Vf was 3.1 V and Po was 18 mW.

(Comparative Example 1)
A light emitting device was produced in the same manner as in Example 1 except that a known photolithography method was used instead of the sand blasting method as a process for the semiconductor layer, and evaluation was performed in the same manner as in Example 1.
About the obtained light emitting element, it mounted in the TO-18 can package, and the light emission output in 20 mA of applied currents was measured with the tester. As a result, Vf was 3.1 V, Po was 14 mW, and Po was lower than that in Example 1.

(Example 2)
The semiconductor light-emitting device of Example 1 was manufactured using ten first substrates, and damage to the first substrate (sapphire) and cracks in the semiconductor light-emitting device were examined by microscopic observation.
(Comparative Example 2)
The semiconductor light emitting device of Comparative Example 1 was manufactured using ten first substrates, and the damage to the first substrate (sapphire) and the cracks in the semiconductor light emitting device were examined by microscopic observation.

  In Example 2, there was no damage to the sapphire and no cracks were generated on the light emitting element in all 10 substrates. On the other hand, in Comparative Example 2, damage to sapphire was observed for 4 substrates out of 10 substrates. Moreover, the crack to a light emitting element was confirmed about five board | substrates.

FIG. 1 is a cross-sectional process diagram illustrating a method for manufacturing a light-emitting element according to the first embodiment of the present invention. FIG. 2 is a cross-sectional process diagram illustrating the method for manufacturing the light-emitting element according to the first embodiment of the present invention. FIG. 3 is a cross-sectional process diagram illustrating a method for manufacturing a light-emitting element according to the first embodiment of the present invention. FIG. 4 is a cross-sectional process diagram illustrating a method for manufacturing a light-emitting element according to the first embodiment of the present invention. FIG. 5 is a schematic cross-sectional view illustrating a sandblasting process in the method for manufacturing a light-emitting element according to the first embodiment of the present invention. FIG. 6 is a schematic cross-sectional view illustrating a sandblasting process in the method for manufacturing a light-emitting element according to the first embodiment of the present invention. FIG. 7 is a cross-sectional process diagram illustrating the method for manufacturing the light-emitting element according to the first embodiment of the present invention. FIG. 8 is a cross-sectional process diagram illustrating a method for manufacturing a light-emitting element according to the first embodiment of the present invention. FIG. 9 is a cross-sectional process diagram illustrating a method for manufacturing a light-emitting element according to the first embodiment of the present invention. FIG. 10 is a schematic plan view illustrating a laser lift-off process in the method for manufacturing a light-emitting element according to the first embodiment of the present invention. FIG. 11 is a schematic cross-sectional view illustrating a laser lift-off process in the method for manufacturing a light-emitting element according to the first embodiment of the present invention. FIG. 12 is a schematic cross-sectional view showing a light emitting device manufactured by the method for manufacturing a light emitting device according to the first embodiment of the present invention. FIG. 13 is a process diagram illustrating a method for manufacturing a light-emitting element according to the second embodiment of the present invention. FIG. 14 is a view for explaining the method for manufacturing the light-emitting element according to the second embodiment of the present invention, and is a schematic cross-sectional view showing the first laminate. FIG. 15 is a diagram illustrating a method for manufacturing a light-emitting element according to the second embodiment of the present invention, and is a schematic diagram illustrating a crystal structure. FIG. 16 is a diagram illustrating a method for manufacturing a light-emitting element according to the second embodiment of the present invention, and is a schematic cross-sectional view illustrating a second stacked body. FIG. 17 is a schematic diagram for explaining a bonding step in the method for manufacturing a light emitting device according to the second embodiment of the present invention. FIG. 18 is a schematic cross-sectional view showing a light emitting device manufactured by the method for manufacturing a light emitting device according to the second embodiment of the present invention. FIG. 19 is a schematic cross-sectional view illustrating a lamp including a light emitting element. 20 is a cross-sectional SEM photograph showing the laminated semiconductor after the sandblasting process in Example 1. FIG. FIG. 21 is a planar SEM photograph showing the laminated semiconductor after the sandblasting process in Example 1.

Explanation of symbols

101, 201 ... first substrate (first substrate), 102, 202 ... semiconductor layer, 102a, 104a ... n-type semiconductor layer, 102b, 104b ... light emitting layer, 102c, 104c ... p-type semiconductor layer, 104, 204 ... Stacked semiconductor, 104d, 204d ... inclined surface (side surface), 111, 301 ... second substrate (second substrate), 114, 400 ... light emitting element (nitride semiconductor light emitting element), 200 ... first stacked body (first) 1), 206... 1st bonding layer (first bonding layer), 300... 2nd stacking body (second stacking body), 303... 2nd bonding layer (second bonding layer).

Claims (8)

A method for manufacturing a nitride semiconductor light emitting device in which a semiconductor layer made of a nitride semiconductor is laminated on a substrate,
A semiconductor layer is formed by sequentially stacking at least an n-type semiconductor layer, a light emitting layer, and a p-type semiconductor layer on a first substrate, and then a mask layer having processing resistance against blasting is formed on the semiconductor layer. Then, by blasting a portion of the semiconductor layer that is not covered by the mask layer , the semiconductor layer is divided, and a plurality of stacked semiconductors having side surfaces made of inclined surfaces formed by the blasting are obtained. Process,
Forming a sacrificial film so as to be embedded between the stacked semiconductors;
Providing a second substrate on the laminated semiconductor and the sacrificial film, and then irradiating a laser beam on an interface between the first substrate and the laminated semiconductor to separate the first substrate from the laminated semiconductor; When,
And a step of removing the sacrificial film after peeling off the first substrate,
The semiconductor layer has a thickness in the range of 3 to 15 μm,
The blasting is performed using blast particles having a Vickers hardness lower than that of the first substrate,
The processing width is 30-100 μm, the average particle size of the blast particles is 5-50 μm,
A method for manufacturing a nitride-based semiconductor light-emitting element, wherein a substrate having a Vickers hardness higher than that of the semiconductor layer is used as the first substrate. A method for manufacturing a nitride semiconductor light emitting device in which a semiconductor layer made of a nitride semiconductor is laminated on a substrate,
A semiconductor layer is formed by sequentially stacking at least an n-type semiconductor layer, a light emitting layer, and a p-type semiconductor layer on a first substrate, and then a mask layer having processing resistance against blasting is formed on the semiconductor layer. Then, by blasting a portion of the semiconductor layer that is not covered by the mask layer , the semiconductor layer is divided, and a plurality of stacked semiconductors having side surfaces made of inclined surfaces formed by the blasting are obtained. Process,
Forming a sacrificial film so as to be embedded between the stacked semiconductors;
A first stacked body is formed by stacking a first bonding layer made of a conductor on the p-type semiconductor layer or on the electrode layer formed on the p-type semiconductor layer and on the sacrificial film. And a process of
Forming a second laminate by laminating at least a second bonding layer made of a conductor on a conductive second substrate;
Integrating the first laminate and the second laminate by joining the first joining layer and the second joining layer; and
Irradiating a laser beam to an interface between the first substrate and the laminated semiconductor to separate the first substrate from the laminated semiconductor;
And a step of removing the sacrificial film after peeling off the first substrate,
The semiconductor layer has a thickness in the range of 3 to 15 μm,
The blasting is performed using blast particles having a Vickers hardness lower than that of the first substrate,
The processing width is 30-100 μm, the average particle size of the blast particles is 5-50 μm,
A method for manufacturing a nitride-based semiconductor light-emitting element, wherein a substrate having a Vickers hardness higher than that of the semiconductor layer is used as the first substrate.     The method for manufacturing a nitride-based semiconductor light-emitting element according to claim 1, wherein the first substrate separated from the laminated semiconductor is reused as a substrate for forming the semiconductor layer.     4. The method for manufacturing a nitride-based semiconductor light-emitting element according to claim 1, wherein a Vickers hardness of the semiconductor layer is 90% or less of a Vickers hardness of the first substrate. The method for producing a nitride-based semiconductor light-emitting element according to any one of claims 1 to 4, wherein the blast particles are mainly composed of alumina or silicon. The blasting method for manufacturing a nitride semiconductor light emitting device according to any one of claim 1 to 5, wherein the resist to perform subjected to patterning in the semiconductor layer side. Production method for a nitride semiconductor light emitting device according to any one of claim 1 to 6, wherein the first substrate is a sapphire. Production method for a nitride semiconductor light emitting device according to any one of claim 1 to 7, wherein the nitride semiconductor forming the semiconductor layer is a GaN-based semiconductor.

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