JP5229200B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- H01L2224/401—Disposition
- H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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Description
さらに、金属製の板状接続導体に代えて、配線基板としてポリイミドフィルムを使用する製造方法も考えられているが、一般にポリイミドフィルムは材料価格が高いために、コストアップになるという問題もあった。
また、リジッド基板として安価なガラス・エポキシ基板を使用することが可能であるから、低コストの半導体パッケージを構成することができる。
図2は、MOSFETパッケージの製造工程(第1工程)で用意される第1、第2のリジッド基板を示す図である。
図3は、リジッド基板と銅箔との接着構造を拡大して示す断面図である。
図4は、第1のリジッド基板に第2のリジッド基板が積層された状態を示し、(a)は積層状態の平面図、(b)はそのC−C線に沿う断面図である。
ここでは、第1のリジッド基板10上の半導体チップ14と金属配線パターン21,22とが接続され、さらに金属配線パターン21,22は、それぞれ半田バンプ16c,17cによって外部リード端子となるプリフォーム半田層15,16a,17aと結線されている。図5には、リフロー加熱された半田バンプ17cが接続部17dとして固化した後に、第2のリジッド基板20を金属配線パターン21,22から引き剥がし、第2のリジッド基板20本体(すなわち、プリプレグ2)のみを取り除いた状態を示している。
図6は、MOSFETの単品基板が複数配列された第1のリジッド基板を示す平面図、図7は、半導体チップの表面電極側の金属配線パターンが複数配列された第2のリジッド基板を示す平面図である。
さらに、半導体チップ14としてMOSFETチップだけではなく、ダイオードチップなど他の半導体チップについても、上述した実施の形態を適用して製造することが可能である。
3 銅箔
10 第1のリジッド基板
11 第1の金属配線パターン
12 第2の金属配線パターン
13 第3の金属配線パターン
14 半導体チップ
14b,15,16a,17a,23,24a,24b プリフォーム半田層
16c,17c 半田バンプ
18,19,25,26 位置合わせマーク
20 第2のリジッド基板
21,22 金属配線パターン
Claims (10)
- パッケージに実装された半導体チップの表面電極を前記パッケージの外部リード端子との間で接続する半導体装置の製造方法において、
前記半導体チップが実装された第1のリジッド基板、および半田材が塗布された金属配線パターンを付着した第2のリジッド基板を用意する工程と、
前記第1のリジッド基板上に前記第2のリジッド基板を位置合わせして載置する工程と、
前記半田材によって前記金属配線パターンをそれぞれ前記半導体チップの表面電極と前記外部リード端子とに接合する工程と、
前記金属配線パターンが前記半導体チップの表面電極および前記外部リード端子に接着した後に前記金属配線パターンを残して前記第2のリジッド基板を取り除く工程と、
を備えたことを特徴とする半導体装置の製造方法。 - 前記第2のリジッド基板は、ガラス・エポキシ基板であることを特徴とする請求項1記載の半導体装置の製造方法。
- 前記第2のリジッド基板は、ロウプロファイルの銅箔が付着されたプリプレグであることを特徴とする請求項2記載の半導体装置の製造方法。
- 前記第2のリジッド基板は、前記銅箔がその凹凸の極めて小さいシャイニー面側で前記プリプレグに重ねて積層されていることを特徴とする請求項3記載の半導体装置の製造方法。
- 前記第2のリジッド基板は、前記プリプレグ内のレジンコンテントが30〜55%であることを特徴とする請求項3記載の半導体装置の製造方法。
- 前記第2のリジッド基板を接合する際に、前記半田材をリフロー加熱することを特徴とする請求項1記載の半導体装置の製造方法。
- 前記第2のリジッド基板を取り除く工程は、120〜150℃の温度範囲で加熱して実施することを特徴とする請求項1記載の半導体装置の製造方法。
- 前記第2のリジッド基板を取り除いた後に、前記金属配線パターンおよび前記半導体チップを樹脂モールドするようにしたことを特徴とする請求項1記載の半導体装置の製造方法。
- 前記第1のリジッド基板は、銅板を加工したリードフレームであることを特徴とする請求項1記載の半導体装置の製造方法。
- 前記第1のリジッド基板上に複数の半導体チップを載置し、前記第2のリジッド基板には、前記各半導体チップの表面電極に対応する複数の金属配線パターンが付着されていて、複数の半導体装置について同時一括して接合工程を実行したことを特徴とする請求項1記載の半導体装置の製造方法。
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CN104247012B (zh) * | 2012-10-01 | 2017-08-25 | 富士电机株式会社 | 半导体装置及其制造方法 |
US9922160B2 (en) | 2015-02-12 | 2018-03-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuit stack verification method and system for performing the same |
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