JP5208701B2

JP5208701B2 - Insulation inspection method and insulation inspection apparatus

Info

Publication number: JP5208701B2
Application number: JP2008309708A
Authority: JP
Inventors: 浩山嵜
Original assignee: Hioki EE Corp
Current assignee: Hioki EE Corp
Priority date: 2008-12-04
Filing date: 2008-12-04
Publication date: 2013-06-12
Anticipated expiration: 2028-12-04
Also published as: JP2010133819A

Description

本発明は、複数の回路基板が面付けされた多面付け基板における各回路基板に形成されている各導体パターンの間の絶縁状態を検査する絶縁検査方法および絶縁検査装置に関するものである。 The present invention relates to an insulation inspection method and an insulation inspection apparatus for inspecting an insulation state between conductor patterns formed on each circuit board in a multi-sided board on which a plurality of circuit boards are attached.

この種の絶縁検査方法に従って検査処理を実行可能に構成された絶縁検査装置として、出願人は、特開２００３−９８２１６号公報において回路基板検査装置を開示している。出願人が開示しているこの回路基板検査装置では、第１Ｘ−Ｙ移動機構および第２Ｘ−Ｙ移動機構（以下、区別しないときには「移動機構」ともいう）に第１検査プローブおよび第２検査プローブ（以下、区別しないときには「検査プローブ」ともいう）がそれぞれ取り付けられると共に、制御装置が両移動機構を制御して載置台上の回路基板に両検査プローブを接触させて電気的に検査する構成が採用されている。具体的には、出願人が開示している回路基板検査装置では、図４に示すように、一例として、回路基板１１０ａ〜１１０ｄの４個（以下、区別しないときには「回路基板１１０」ともいう）が面付けされた多面付け基板１００（図３参照）を検査対象として検査する際に、両検査プローブを導体パターンＰ１〜Ｐ４０（以下区別しないときには「導体パターンＰ」ともいう）に対して順次接触させ、両プローブを接触させた導体パターンＰ，Ｐの間の電気的信号のレベルに基づいて絶縁状態を検査する。なお、図４では、出願人が開示している回路基板検査装置の図示しない検査部における電圧供給部の高電位出力部に接続されている検査プローブを「Ｈ」として図示すると共に、電圧供給部の低電位出力部に接続されている検査プローブを「Ｌ」として図示している。 As an insulation inspection apparatus configured to be able to execute inspection processing according to this type of insulation inspection method, the applicant discloses a circuit board inspection apparatus in Japanese Patent Application Laid-Open No. 2003-98216. In this circuit board inspection apparatus disclosed by the applicant, the first inspection probe and the second inspection probe are used as the first XY movement mechanism and the second XY movement mechanism (hereinafter also referred to as “movement mechanism” when not distinguished). (Hereinafter also referred to as “inspection probe” when not distinguished), and a control device controls both moving mechanisms to bring both inspection probes into contact with the circuit board on the mounting table for electrical inspection. It has been adopted. Specifically, in the circuit board inspection apparatus disclosed by the applicant, as shown in FIG. 4, as an example, four circuit boards 110a to 110d (hereinafter, also referred to as “circuit board 110” when not distinguished). When inspecting the multi-sided substrate 100 (see FIG. 3) with the surface of the substrate as an inspection object, the inspection probes are sequentially brought into contact with the conductor patterns P1 to P40 (hereinafter also referred to as “conductor pattern P” when not distinguished). Then, the insulation state is inspected based on the level of the electrical signal between the conductor patterns P and P in contact with both probes. In FIG. 4, the inspection probe connected to the high potential output unit of the voltage supply unit in the inspection unit (not shown) of the circuit board inspection apparatus disclosed by the applicant is shown as “H”, and the voltage supply unit The inspection probe connected to the low-potential output section is indicated as “L”.

さらに具体的には、第１回の検査として、一方の検査プローブを多面付け基板１００における回路基板１１０ａの導体パターンＰ１に接触させると共に他方の検査プローブを導体パターンＰ２に接触させた状態において、電圧供給部から両検査プローブを介して導体パターンＰ１，Ｐ２の間に検査用電圧を供給し、その状態において測定した電気的信号のレベルに基づいて導体パターンＰ１，Ｐ２の間の絶縁状態を検査する。次いで、第２回の検査として、一方の検査プローブを導体パターンＰ１に接触させた状態を維持すると共に他方の検査プローブを導体パターンＰ３に接触させて絶縁状態を検査する。続いて、第３回の検査として、一方の検査プローブを導体パターンＰ１に接触させた状態を維持すると共に他方の検査プローブを導体パターンＰ４に接触させて絶縁状態を検査する。また、第４４回の検査として、一方の検査プローブを導体パターンＰ８に接触させると共に他方の検査プローブを導体パターンＰ１０に接触させて絶縁状態を検査した後に、第４５回の検査として、一方の検査プローブを導体パターンＰ９に接触させると共に他方の検査プローブを導体パターンＰ１０に接触させて絶縁状態を検査する。これにより、多面付け基板１００における１枚目の回路基板１１０ａについての検査が完了する。 More specifically, as the first inspection, in the state where one inspection probe is in contact with the conductor pattern P1 of the circuit board 110a in the multi-sided substrate 100 and the other inspection probe is in contact with the conductor pattern P2, the voltage An inspection voltage is supplied between the conductor patterns P1 and P2 from the supply unit via both inspection probes, and the insulation state between the conductor patterns P1 and P2 is inspected based on the level of the electrical signal measured in that state. . Next, as a second inspection, the state in which one inspection probe is in contact with the conductor pattern P1 is maintained and the other inspection probe is in contact with the conductor pattern P3 to inspect the insulation state. Subsequently, as a third inspection, the state in which one inspection probe is in contact with the conductor pattern P1 is maintained, and the other inspection probe is in contact with the conductor pattern P4 to inspect the insulation state. As the 45th inspection, one inspection probe is brought into contact with the conductor pattern P8 and the other inspection probe is brought into contact with the conductor pattern P10 to inspect the insulation state. The probe is brought into contact with the conductor pattern P9 and the other inspection probe is brought into contact with the conductor pattern P10 to inspect the insulation state. Thereby, the inspection of the first circuit board 110a in the multi-sided board 100 is completed.

次いで、第４６回の検査として、一方の検査プローブを回路基板１１０ｂの導体パターンＰ１１に接触させると共に他方の検査プローブを導体パターンＰ１２に接触させて絶縁状態を検査した後に、第４７回の検査として、一方の検査プローブを導体パターンＰ１１に接触させた状態を維持すると共に他方の検査プローブを導体パターンＰ１３に接触させて絶縁状態を検査する。この後、第４８回から第９０回の検査として、上記の回路基板１１０ａに対する第３回から第４５回の検査時と同様の手順で導体パターンＰ１１〜Ｐ２０の相互間の絶縁状態をそれぞれ検査する。これにより、多面付け基板１００における２枚目の回路基板１１０ｂについての検査が完了する。この後、第９１回から第１３５回の検査によって３枚目の回路基板１１０ｃに形成されている導体パターンＰ２１〜Ｐ３０の絶縁状態を検査すると共に、第１３６回から第１８０回の検査によって４枚目の回路基板１１０ｄに形成されている導体パターンＰ３１〜Ｐ４０の絶縁状態を検査する。 Next, as the 46th inspection, one inspection probe is brought into contact with the conductor pattern P11 of the circuit board 110b and the other inspection probe is brought into contact with the conductor pattern P12 to inspect the insulation state, and then the 47th inspection is performed. While maintaining the state in which one inspection probe is in contact with the conductor pattern P11, the other inspection probe is in contact with the conductor pattern P13 to inspect the insulation state. Thereafter, as the 48th to 90th inspections, the insulation states between the conductor patterns P11 to P20 are inspected in the same procedure as the 3rd to 45th inspections on the circuit board 110a. . Thereby, the inspection of the second circuit board 110b in the multi-sided board 100 is completed. Thereafter, the insulation states of the conductor patterns P21 to P30 formed on the third circuit board 110c are inspected by the 91st to 135th inspections, and the four to 136th to 180th inspections. The insulation states of the conductor patterns P31 to P40 formed on the eye circuit board 110d are inspected.

このように、出願人が開示している回路基板検査装置では、多面付け基板１００を構成する各回路基板１１０に形成されている各導体パターンＰに対する両検査プローブの接触態様を変更して複数回に亘って絶縁状態を検査し、回路基板１１０上のすべての導体パターンＰの絶縁状態が良好であったときには、その回路基板１１０を良品と検査する。この場合、出願人が開示している回路基板検査装置において各回路基板１１０に対して実施される上記の検査方法は、「総当たりスキャン検査」として、下記の非特許文献１に開示されている。
特開２００３−９８２１６号公報（第５−８頁、第１図）編集委員長原靖彦、「高密度実装における検査技術・装置ハンドブック」、社団法人国際都市コミュニケーションセンター編集事務局、２００１年９月１日、ｐ．８７−８８ Thus, in the circuit board inspection apparatus disclosed by the applicant, the contact mode of both inspection probes with respect to each conductor pattern P formed on each circuit board 110 constituting the multi-sided board 100 is changed a plurality of times. The insulation state is inspected over a period of time, and when all the conductor patterns P on the circuit board 110 are in good insulation, the circuit board 110 is inspected as a good product. In this case, the above-described inspection method performed on each circuit board 110 in the circuit board inspection apparatus disclosed by the applicant is disclosed in Non-Patent Document 1 below as “brute force scan inspection”. .
JP 2003-98216 A (page 5-8, FIG. 1) Editor-in-Chief Akihiko Hara, “Inspection Technology and Equipment Handbook for High-Density Mounting”, International Urban Communication Center Editorial Office, September 1, 2001, p. 87-88

ところが、出願人が開示している回路基板検査装置には、以下の改善すべき課題がある。すなわち、出願人が開示している回路基板検査装置では、各導体パターンＰに対する一対の検査プローブの接触態様を変更して複数回に亘って導体パターンＰ，Ｐ間の絶縁状態を検査することによって各回路基板１１０の良否を検査している。この場合、この検査方法では、各回路基板１１０内のＭ個の導体パターンがすべて良好であると検査するのに必要な（検査対象の多面付け基板が良品であると検査するのに必要な）検査回数Ｃが、「Ｃ＝Ｍ（Ｍ−１）／２」との式によって表される。したがって、「Ｍ＝１０」の上記の回路基板１１０に形成されているすべての導体パターンＰの絶縁状態を検査するためには、検査回数Ｃ＝１０（１０−１）／２＝４５回の検査が必要となっている。また、上記の多面付け基板１００では、回路基板１１０ａ〜１１０ｄの４個が面付けされているため、１枚の多面付け基板１００に形成されているすべての導体パターンＰの絶縁状態を検査するためには、４５×４＝１８０回の検査が必要となっている。このため、多面付け基板を構成する各回路基板上に形成される導体パターンＰの数が徐々に増加する傾向がある今日、多面付け基板の１枚当りに要する検査時間の一層の短縮を図りたいとの要求があり、この点を改善するのが好ましい。 However, the circuit board inspection apparatus disclosed by the applicant has the following problems to be improved. That is, in the circuit board inspection apparatus disclosed by the applicant, the contact state of the pair of inspection probes with respect to each conductor pattern P is changed, and the insulation state between the conductor patterns P and P is inspected a plurality of times. The quality of each circuit board 110 is inspected. In this case, in this inspection method, it is necessary to inspect that all M conductor patterns in each circuit board 110 are good (necessary to inspect that the multi-sided substrate to be inspected is a non-defective product). The number of inspections C is expressed by an expression “C = M (M−1) / 2”. Therefore, in order to inspect the insulation state of all the conductor patterns P formed on the circuit board 110 with “M = 10”, the number of inspections C = 10 (10−1) / 2 = 45 inspections. Is required. In the multi-sided board 100, four circuit boards 110a to 110d are faced, so that the insulation state of all the conductor patterns P formed on one multi-sided board 100 is inspected. Requires 45 × 4 = 180 inspections. For this reason, there is a tendency that the number of conductor patterns P formed on each circuit board constituting the multi-sided board gradually increases, and it is desired to further reduce the inspection time required for each multi-sided board. It is preferable to improve this point.

本発明は、かかる改善すべき課題に鑑みてなされたものであり、多面付け基板の絶縁検査に要する時間を短縮し得る絶縁検査方法および絶縁検査装置を提供することを主目的とする。 The present invention has been made in view of such a problem to be improved, and it is a main object of the present invention to provide an insulation inspection method and an insulation inspection apparatus that can shorten the time required for insulation inspection of a multi-sided substrate.

上記目的を達成すべく請求項１記載の絶縁検査方法は、一対の検査用プローブを別個独立して移動させて検査対象の複数の回路基板が面付けされた多面付け基板における当該各回路基板に形成されている複数の導体パターンに当該一対の検査用プローブを接触させると共に、当該一対の検査用プローブのうちの一方を電圧供給部における高電位を出力する高電位出力部に接続し、かつ、当該一対の検査用プローブのうちの他方を電圧供給部における低電位を出力する低電位出力部に接続した状態において、当該一対の検査用プローブを介して前記電圧供給部から検査用電圧を供給して前記各導体パターンのうちの前記一方の検査用プローブを接触させた第１の導体パターンと当該各導体パターンのうちの前記他方の検査用プローブを接触させた第２の導体パターンとの間の電気的パラメータを測定し、当該測定した電気的パラメータに基づいて当該第１の導体パターンおよび当該第２の導体パターンの間の絶縁状態を検査する検査処理を前記各導体パターンに対する前記一対の検査用プローブの接触態様を変更して複数回に亘って実行することによって当該各導体パターンの間の絶縁状態をそれぞれ検査する絶縁検査方法であって、Ｎ個（Ｎは、２以上の自然数）の前記回路基板が面付けされた前記多面付け基板を検査対象として検査するときに、前記複数回の検査処理として、当該Ｎ個の回路基板毎の前記第１の導体パターンおよび前記第２の導体パターンの間の絶縁状態を、Ｎ組の前記検査用プローブを使用して当該第１の導体パターン同士を互いに同電位にすると共に当該第２の導体パターン同士を互いに同電位にした状態で当該各回路基板に対して同時に検査する第１の検査処理を前記接触態様を変更して複数回に亘って実行する。 In order to achieve the above object, an insulation inspection method according to claim 1, wherein a plurality of circuit boards to be inspected are arranged on each circuit board by moving a pair of inspection probes separately and independently. with contacting the pair of test probes to a plurality of conductive patterns are formed by connecting one of the pair of test probe to a high potential output unit that outputs the high potential in the voltage supply unit, and, In a state where the other of the pair of inspection probes is connected to a low potential output unit that outputs a low potential in the voltage supply unit, an inspection voltage is supplied from the voltage supply unit via the pair of inspection probes. Then, the first conductor pattern in which the one inspection probe of the conductor patterns is brought into contact with the other inspection probe in the conductor pattern. An inspection process for measuring an electrical parameter between the second conductor pattern and inspecting an insulation state between the first conductor pattern and the second conductor pattern based on the measured electrical parameter. An insulation inspection method for inspecting an insulation state between the conductor patterns by changing the contact mode of the pair of inspection probes with respect to each conductor pattern and executing the plurality of times, wherein N (N Is the first conductor for each of the N circuit boards as the plurality of inspection processes when inspecting the multi-sided board on which the circuit board of 2 or more natural numbers is imbedded as an inspection target The insulation state between the pattern and the second conductor pattern is set so that the first conductor patterns are made to have the same potential by using N sets of the inspection probes. Performing a plurality of times by changing the contact mode a first test process of testing simultaneously in a state in which the conductor patterns to each other and to the same potential with respect to the respective circuit board.

請求項２記載の絶縁検査方法は、請求項１記載の絶縁検査方法において、前記第１の検査処理時において前記絶縁状態を不良と検査したときに、前記各回路基板毎に前記第１の導体パターンおよび前記第２の導体パターンの間の絶縁状態を個別的に検査する第２の検査処理を実行する。 The insulation inspection method according to claim 2 is the insulation inspection method according to claim 1, wherein when the insulation state is inspected as defective during the first inspection process, the first conductor is provided for each circuit board. A second inspection process for individually inspecting the insulation state between the pattern and the second conductor pattern is executed.

請求項３記載の絶縁検査装置は、一対の検査用プローブを別個独立して移動させて検査対象の複数の回路基板が面付けされた多面付け基板における当該各回路基板に形成されている複数の導体パターンに当該一対の検査用プローブを接触させるプローブ移動機構と、前記一対の検査用プローブを介して当該各導体パターンに検査用電圧を供給する電圧供給部と、前記検査用電圧を供給させた状態において前記各導体パターンのうちの前記電圧供給部における高電位を出力する高電位出力部に接続された前記検査用プローブが接触している第１の導体パターンと当該各導体パターンのうちの当該電圧供給部における低電位を出力する低電位出力部に接続された前記検査用プローブが接触している第２の導体パターンとの間の電気的パラメータを測定して当該測定した電気的パラメータに基づいて当該第１の導体パターンおよび当該第２の導体パターンの間の絶縁状態を検査する検査処理を実行する検査部とを備え、当該検査部が前記プローブ移動機構を制御して前記各導体パターンに対する前記一対の検査用プローブの接触態様を変更させると共に前記電圧供給部を制御して前記検査用電圧を供給させて複数回の前記検査処理を実行することによって前記各導体パターンの間の絶縁状態をそれぞれ検査する絶縁検査装置であって、前記検査部が、Ｎ個（Ｎは、２以上の自然数）の前記回路基板が面付けされた前記多面付け基板を検査対象として検査するときに、前記複数回の検査処理として、当該Ｎ個の回路基板毎の前記第１の導体パターンおよび前記第２の導体パターンの間の絶縁状態を、Ｎ組の前記検査用プローブを使用して当該第１の導体パターン同士を互いに同電位にすると共に当該第２の導体パターン同士を互いに同電位にした状態で当該各回路基板に対して同時に検査する第１の検査処理を前記接触態様を変更して複数回に亘って実行する。 According to a third aspect of the present invention, there is provided the insulation inspection apparatus according to claim 3, wherein a plurality of inspection substrates are formed on each circuit board in a multi-sided board on which a plurality of circuit boards to be inspected are provided by moving a pair of inspection probes separately and independently . a probe moving mechanism for contacting the pair of test probe to the conductor pattern, and a voltage supply unit for supplying a test voltage to the conductor patterns through the pair of test probes were supply the test voltage In the state, the first conductor pattern in contact with the inspection probe connected to the high potential output section that outputs the high potential in the voltage supply section of the conductor patterns and the conductor pattern of the conductor pattern An electrical parameter between the second conductor pattern in contact with the inspection probe connected to the low potential output unit that outputs a low potential in the voltage supply unit. And an inspection unit that performs an inspection process for inspecting an insulation state between the first conductor pattern and the second conductor pattern based on the measured electrical parameter, and the inspection unit includes the probe Controlling the moving mechanism to change the contact mode of the pair of inspection probes with respect to the conductor patterns, and controlling the voltage supply unit to supply the inspection voltage to execute the inspection process a plurality of times. The multi-sided substrate, wherein the inspection unit is configured to inspect N (N is a natural number of 2 or more) of the circuit boards. As the inspection object, the insulation between the first conductor pattern and the second conductor pattern for each of the N circuit boards is performed as the plurality of inspection processes. With respect to each circuit board in a state in which the first conductor patterns are made to have the same potential and the second conductor patterns are made to have the same potential using N sets of inspection probes. The first inspection process for simultaneously inspecting is performed a plurality of times while changing the contact mode.

請求項１記載の絶縁検査方法および請求項３記載の絶縁検査装置によれば、Ｎ個の回路基板が面付けされた多面付け基板を検査対象として検査するときに、Ｎ個の回路基板毎の第１の導体パターンおよび第２の導体パターンの間の絶縁状態を、Ｎ組の検査用プローブを使用して第１の導体パターン同士を互いに同電位にすると共に第２の導体パターン同士を互いに同電位にした状態で各回路基板に対して同時に検査する第１の検査処理を各導体パターンに対する一対の検査用プローブの接触態様を変更して複数回に亘って実行することにより、第１の検査処理時に各回路基板内の第１の導体パターンおよび第２の導体パターンの間の絶縁状態をすべての回路基板に対して同時に検査する分だけ、１枚の多面付け基板を検査するのに要する検査処理の回数を十分に低減することができる。したがって、この絶縁検査方法および絶縁検査装置によれば、すべての導体パターンの相互間における絶縁状態の良否を検査しつつ多面付け基板の絶縁検査に要する時間を十分に短縮することができる。 According to the insulation inspection method according to claim 1 and the insulation inspection apparatus according to claim 3, when inspecting a multi-faced substrate on which N circuit boards are imposed as an inspection object, for each of the N circuit boards, The insulation state between the first conductor pattern and the second conductor pattern is set so that the first conductor patterns have the same potential by using N sets of inspection probes, and the second conductor patterns have the same potential. A first inspection process for simultaneously inspecting each circuit board in a state of potential is performed multiple times by changing the contact mode of the pair of inspection probes with respect to each conductor pattern, thereby performing the first inspection. Inspection required for inspecting one multi-sided board by the amount of simultaneously inspecting the insulation state between the first conductor pattern and the second conductor pattern in each circuit board for each circuit board at the time of processing The number of management can be sufficiently reduced. Therefore, according to this insulation inspection method and insulation inspection apparatus, it is possible to sufficiently reduce the time required for the insulation inspection of the multi-sided substrate while inspecting the quality of the insulation state between all the conductor patterns.

また、請求項２記載の絶縁検査方法によれば、第１の検査処理時において絶縁状態を不良と検査したときに、各回路基板毎に第１の導体パターンおよび第２の導体パターンの間の絶縁状態を個別的に検査する第２の検査処理を実行することにより、多面付け基板の絶縁検査に要する時間を十分に短縮しつつ、絶縁不良の生じている導体パターンを確実に特定することができる。 According to the insulation inspection method of the second aspect, when the insulation state is inspected as defective during the first inspection process, the gap between the first conductor pattern and the second conductor pattern is determined for each circuit board. By performing the second inspection process for individually inspecting the insulation state, the time required for the insulation inspection of the multi-sided substrate can be sufficiently shortened, and the conductor pattern in which the insulation failure has occurred can be specified reliably. it can.

以下、本発明に係る絶縁検査方法および絶縁検査装置の最良の形態について、添付図面を参照して説明する。 Hereinafter, the best mode of an insulation inspection method and an insulation inspection apparatus according to the present invention will be described with reference to the accompanying drawings.

最初に、絶縁検査装置１の構成について、図面を参照して説明する。 First, the configuration of the insulation inspection apparatus 1 will be described with reference to the drawings.

図１に示す絶縁検査装置１は、本発明に係る絶縁検査装置の一例であって、本発明に係る絶縁検査方法に従って図３に示す多面付け基板（多面取り基板）１００における各回路基板１１０ａ〜１１０ｄの良否を検査可能に構成されている。この場合、多面付け基板１００は、本発明における多面付け基板の一例であって、前述したように、一例として、導体パターンＰ１〜Ｐ１０が形成されている回路基板１１０ａ、導体パターンＰ１１〜Ｐ２０が形成されている回路基板１１０ｂ、導体パターンＰ２１〜Ｐ３０が形成されている回路基板１１０ｃ、および導体パターンＰ３１〜Ｐ４０が形成されている回路基板１１０ｄの４個（本発明における「Ｎ」が「４」の例：以下、区別しないときには「回路基板１１０」ともいう）が面付けされている。なお、同図では、本発明についての理解を容易とするために、多面付け基板１００の一方の面側だけを図示すると共に、導体パターンＰ１〜Ｐ４０（以下、区別しないときには「導体パターンＰ」ともいう）について、各回路基板１１０内において隣り合う各導体パターンＰ，Ｐの間隔を等間隔で図示している。一方、図１に示すように、絶縁検査装置１は、プローブ機構２、接続切替部３、電圧供給部４、測定部５、操作部６、表示部７、制御部８および記憶部９を備えている。 An insulation inspection apparatus 1 shown in FIG. 1 is an example of an insulation inspection apparatus according to the present invention, and each circuit board 110a˜ in the multi-faced substrate (multi-faced board) 100 shown in FIG. 3 according to the insulation inspection method according to the present invention. 110d is acceptable. In this case, the multi-sided substrate 100 is an example of the multi-sided substrate in the present invention. As described above, as an example, the circuit board 110a on which the conductor patterns P1 to P10 are formed and the conductor patterns P11 to P20 are formed. Circuit board 110b, the circuit board 110c on which the conductor patterns P21 to P30 are formed, and the circuit board 110d on which the conductor patterns P31 to P40 are formed ("N" in the present invention is "4") Example: Hereinafter, when not distinguished, it is also referred to as “circuit board 110”). In this figure, in order to facilitate understanding of the present invention, only one surface side of the multi-sided substrate 100 is illustrated, and conductor patterns P1 to P40 (hereinafter referred to as “conductor pattern P” when not distinguished). In the circuit board 110, adjacent conductor patterns P, P are illustrated at equal intervals. On the other hand, as shown in FIG. 1, the insulation inspection apparatus 1 includes a probe mechanism 2, a connection switching unit 3, a voltage supply unit 4, a measurement unit 5, an operation unit 6, a display unit 7, a control unit 8, and a storage unit 9. ing.

プローブ機構２は、移動機構１１Ｈ１〜１１Ｈ４，１１Ｌ１〜１１Ｌ４（以下、区別しないときには「移動機構１１」ともいう）と、検査用プローブ１２Ｈ１〜１２Ｈ４，１２Ｌ１〜１２Ｌ４（本発明における「Ｎ組」が「４組」の例：以下、区別しないときには「検査用プローブ１２」ともいう）とを備えている。各移動機構１１は、制御部８からの制御信号Ｓ２に従って各検査用プローブ１２を多面付け基板１００における各回路基板１１０上の各導体パターンＰ（各検査ポイント）に対して接触させる。また、各検査用プローブ１２は、一例としてピン状の伸縮型プローブで構成されている。この場合、この例では、検査用プローブ１２Ｈ１〜１２Ｈ４（以下、これらを総称して「検査用プローブ１２Ｈ」ともいう）が本発明における「一方の検査用プローブ」に相当し、接続切替部３によって電圧供給部４における高電位（以下、「Ｈ電位」ともいう）を出力する高電位出力部４Ｈに接続されている。また、この例では、検査用プローブ１２Ｌ１〜１２Ｌ４（以下、これらを総称して「検査用プローブ１２Ｌ」ともいう）が本発明における「他方の検査用プローブ」に相当し、電圧供給部４における低電位（一例として、接地電位：以下、「Ｌ電位」ともいう）を出力する低電位出力部４Ｌに接続されている。接続切替部３は、制御部８からの制御信号Ｓ１に従って、上記の各検査用プローブ１２を電圧供給部４の高電位出力部４Ｈおよび低電位出力部４Ｌのいずれかに接続する。 The probe mechanism 2 includes a moving mechanism 11H1 to 11H4, 11L1 to 11L4 (hereinafter also referred to as “moving mechanism 11” when not distinguished), and an inspection probe 12H1 to 12H4, 12L1 to 12L4 (“N set” in the present invention is “ "4 sets" example: hereinafter referred to as "inspection probe 12" when not distinguished). Each moving mechanism 11 brings each inspection probe 12 into contact with each conductor pattern P (each inspection point) on each circuit board 110 in the multi-sided substrate 100 in accordance with a control signal S2 from the control unit 8. Each inspection probe 12 is constituted by a pin-shaped extendable probe as an example. In this case, in this example, inspection probes 12H1 to 12H4 (hereinafter collectively referred to as “inspection probe 12H”) correspond to “one inspection probe” in the present invention. The voltage supply unit 4 is connected to a high potential output unit 4H that outputs a high potential (hereinafter also referred to as “H potential”). In this example, the inspection probes 12L1 to 12L4 (hereinafter collectively referred to as “inspection probe 12L”) correspond to the “other inspection probe” in the present invention, and the voltage supply unit 4 has a low level. It is connected to a low potential output unit 4L that outputs a potential (for example, ground potential: hereinafter also referred to as “L potential”). The connection switching unit 3 connects each of the inspection probes 12 to either the high potential output unit 4H or the low potential output unit 4L of the voltage supply unit 4 in accordance with the control signal S1 from the control unit 8.

電圧供給部４は、本発明における電圧供給部の一例であって、制御部８からの制御信号Ｓ３に従って図示しない定電圧源から上記の高電位出力部４Ｈ（Ｈ電位）および低電位出力部４Ｌ（Ｌ電位）の間に検査用電圧（直流定電圧）Ｖを印加することにより、上記の各検査用プローブ１２を介して各回路基板１１０における各導体パターンＰに検査用電圧Ｖを供給する。測定部５は、電圧測定部５ａおよび電流測定部５ｂを備えて、制御部８および接続切替部３と相俟って本発明における検査部を構成する。電圧測定部５ａは、電圧供給部４からの検査用電圧Ｖの供給によって生じる各導体パターンＰ，Ｐ（検査用プローブ１２Ｈが接続された導体パターンＰ、および検査用プローブ１２Ｌが接続された導体パターンＰ）の間の電圧（電位差：本発明における電気的パラメータの一例）を検出して、その電圧値を示す測定データＤｖを制御部８に出力する。電流測定部５ｂは、電圧供給部４からの検査用電圧Ｖの供給によって上記の導体パターンＰ，Ｐ間を導通する電流を検出して、その電流値（本発明における電気的パラメータの他の一例）を示す測定データＤｉを制御部８に出力する。操作部６は、電源スイッチや検査開始スイッチ等の各種のスイッチを備えて構成されて、各スイッチの操作に対応する操作信号を出力する。表示部７は、制御部８の制御に従って検査結果等の各種の画像を表示する。 The voltage supply unit 4 is an example of the voltage supply unit in the present invention, and the high potential output unit 4H (H potential) and the low potential output unit 4L are connected from a constant voltage source (not shown) according to the control signal S3 from the control unit 8. By applying a test voltage (DC constant voltage) V during (L potential), the test voltage V is supplied to each conductor pattern P on each circuit board 110 via each test probe 12 described above. The measuring unit 5 includes a voltage measuring unit 5a and a current measuring unit 5b, and together with the control unit 8 and the connection switching unit 3, constitutes an inspection unit in the present invention. The voltage measuring unit 5a includes the conductor patterns P and P generated by the supply of the inspection voltage V from the voltage supply unit 4 (the conductor pattern P to which the inspection probe 12H is connected and the conductor pattern to which the inspection probe 12L is connected). P) is detected (potential difference: an example of an electrical parameter in the present invention), and measurement data Dv indicating the voltage value is output to the controller 8. The current measuring unit 5b detects the current that conducts between the conductor patterns P and P by the supply of the inspection voltage V from the voltage supply unit 4, and the current value (another example of the electrical parameter in the present invention). ) Is output to the control unit 8. The operation unit 6 includes various switches such as a power switch and an inspection start switch, and outputs an operation signal corresponding to the operation of each switch. The display unit 7 displays various images such as inspection results under the control of the control unit 8.

制御部８は、絶縁検査装置１を総括的に制御する。具体的には、制御部８は、操作部６から出力される操作信号に従って絶縁検査処理を実行することにより、多面付け基板１００上（各回路基板１１０上）の導体パターンＰ，Ｐ間の絶縁状態を検査する。より具体的には、制御部８は、後述するようにして、記憶部９に記憶されている検査手順データＤｔに従って接続切替部３に制御信号Ｓ１を出力することにより、高電位出力部４Ｈおよび低電位出力部４Ｌと各検査用プローブ１２との接続を切り替えさせる。また、制御部８は、プローブ機構２の各移動機構１１に制御信号Ｓ２を出力することによって各検査用プローブ１２を多面付け基板１００における各回路基板１１０上の各導体パターンＰにそれぞれ接触させると共に、電圧供給部４に制御信号Ｓ３を出力することによって各検査用プローブ１２を介して導体パターンＰ，Ｐの間に検査用電圧Ｖを供給させる。さらに、制御部８は、測定部５を制御して測定処理を実行させる。また、制御部８は、電圧測定部５ａから出力される測定データＤｖおよび電流測定部５ｂから出力される測定データＤｉに基づいて導体パターンＰ，Ｐの間の抵抗値を演算すると共に、その演算結果と記憶部９に記憶されている検査用基準データＤｃ（基準抵抗値）とを比較して各回路基板１１０の良否（各導体パターンＰ，Ｐの間の絶縁状態）を検査する。 The control unit 8 comprehensively controls the insulation inspection apparatus 1. Specifically, the control unit 8 performs insulation inspection processing according to the operation signal output from the operation unit 6, thereby insulating between the conductor patterns P and P on the multi-sided substrate 100 (on each circuit substrate 110). Check the condition. More specifically, the control unit 8 outputs a control signal S1 to the connection switching unit 3 in accordance with the inspection procedure data Dt stored in the storage unit 9 as described later, whereby the high potential output unit 4H and The connection between the low potential output unit 4L and each inspection probe 12 is switched. Further, the control unit 8 outputs the control signal S2 to each moving mechanism 11 of the probe mechanism 2 to bring each inspection probe 12 into contact with each conductor pattern P on each circuit board 110 in the multi-sided substrate 100. Then, by outputting the control signal S3 to the voltage supply unit 4, the inspection voltage V is supplied between the conductor patterns P and P via each inspection probe 12. Furthermore, the control unit 8 controls the measurement unit 5 to execute measurement processing. The control unit 8 calculates the resistance value between the conductor patterns P and P based on the measurement data Dv output from the voltage measurement unit 5a and the measurement data Di output from the current measurement unit 5b, and the calculation The result and the reference data for inspection Dc (reference resistance value) stored in the storage unit 9 are compared to check the quality of each circuit board 110 (insulation state between the conductor patterns P, P).

記憶部９は、上記の検査手順データＤｔや検査用基準データＤｃなどを記憶する。この場合、この絶縁検査装置１では、上記の検査手順データＤｔは、図２に示すように、多面付け基板１００上の導体パターンＰ１〜Ｐ４０のすべてを各回路基板１１０毎にグループ分けして、本発明における第１の検査処理を実行するためのデータで構成されている。具体的には、検査手順データＤｔとしては、多面付け基板１００に対する複数回の検査処理時に各導体パターンＰをどのようにグループ分けして検査するか（各導体パターンＰがいずれの回路基板１１０上の導体パターンＰであるか）を特定可能なデータと、検査用プローブ１２Ｈ，１２Ｌをいずれの導体パターンＰに接触させるか（各検査処理時に一対の導体パターンＰ，ＰをＨ電位およびＬ電位のいずれの電位と同電位とするか）を特定可能なデータとで構成されている。なお、図２では、検査用プローブ１２Ｈを「Ｈ」として図示すると共に、検査用プローブ１２Ｌを「Ｌ」として図示している。この場合、この絶縁検査装置１では、後述するようにして、本発明における第１の検査処理時において、出願人が開示している回路基板検査装置において各回路基板１１０に対して順次実行していた検査方法（総当たりスキャン検査）を各回路基板１１０に対して同時に実行して各回路基板１１０内の各導体パターンＰ間の絶縁状態を検査する。 The storage unit 9 stores the inspection procedure data Dt, the inspection reference data Dc, and the like. In this case, in the insulation inspection apparatus 1, the inspection procedure data Dt is obtained by grouping all the conductor patterns P1 to P40 on the multi-sided substrate 100 for each circuit board 110 as shown in FIG. It is comprised by the data for performing the 1st test | inspection process in this invention. Specifically, as the inspection procedure data Dt, how the conductor patterns P are grouped and inspected at the time of a plurality of inspection processes for the multi-sided board 100 (on which circuit board 110 each conductor pattern P is inspected) Data that can specify the conductor pattern P) and which conductor pattern P the inspection probes 12H and 12L are brought into contact with (the pair of conductor patterns P and P have the H potential and the L potential at the time of each inspection process) And which potential is the same as the potential). In FIG. 2, the inspection probe 12H is illustrated as “H”, and the inspection probe 12L is illustrated as “L”. In this case, in the insulation inspection apparatus 1, as described later, the circuit board inspection apparatus disclosed by the applicant sequentially executes each circuit board 110 at the time of the first inspection processing in the present invention. The inspection method (brute force scan inspection) is simultaneously performed on each circuit board 110 to inspect the insulation state between the conductor patterns P in each circuit board 110.

次に、絶縁検査装置１を用いて多面付け基板１００における各回路基板１１０の良否（各回路基板１１０上の導体パターンＰの絶縁状態）を検査する絶縁検査方法およびその際の絶縁検査装置１の動作について、図面を参照して説明する。 Next, an insulation inspection method for inspecting the quality of each circuit board 110 (insulation state of the conductor pattern P on each circuit board 110) on the multi-sided substrate 100 using the insulation inspection apparatus 1 and the insulation inspection apparatus 1 at that time The operation will be described with reference to the drawings.

まず、検査対象の多面付け基板１００を図外の基板保持部に保持させた後に、操作部６を操作して検査開始を指示する。この際には、制御部８が、操作部６から出力された操作信号に従って、絶縁検査処理を開始する。この絶縁検査処理では、制御部８は、まず、接続切替部３に制御信号Ｓ１を出力することにより、各検査用プローブ１２Ｈを電圧供給部４の高電位出力部４Ｈ（Ｈ電位）に共通的に接続させると共に、各検査用プローブ１２Ｌを電圧供給部４の低電位出力部４Ｌ（Ｌ電位）に共通的に接続させる。この場合、この絶縁検査装置１では、各検査用プローブ１２Ｈ，１２Ｌを電圧供給部４の高電位出力部４Ｈおよび低電位出力部４Ｌに対して共通的に接続して１つの測定部５によって以下の測定処理を実行する構成を採用している。したがって、例えば、検査用プローブ１２Ｈ１，１２Ｌ１用の電圧供給部４および測定部５と、検査用プローブ１２Ｈ２，１２Ｌ２用の電圧供給部４および測定部５と、検査用プローブ１２Ｈ３，１２Ｌ３用の電圧供給部４および測定部５と、検査用プローブ１２Ｈ４，１２Ｌ４用の電圧供給部４および測定部５とをそれぞれ用意して各回路基板１１０毎の導体パターンＰ，Ｐ間の絶縁検査を並行して実行する構成と比較して、絶縁検査装置１の製造コストを十分に低減することが可能となっている。 First, after the multi-sided substrate 100 to be inspected is held by a substrate holding unit (not shown), the operation unit 6 is operated to instruct the start of inspection. At this time, the control unit 8 starts an insulation inspection process in accordance with the operation signal output from the operation unit 6. In this insulation inspection process, the control unit 8 first outputs the control signal S1 to the connection switching unit 3 so that each inspection probe 12H is common to the high potential output unit 4H (H potential) of the voltage supply unit 4. In addition, each inspection probe 12L is commonly connected to the low potential output unit 4L (L potential) of the voltage supply unit 4. In this case, in this insulation inspection apparatus 1, each of the inspection probes 12H and 12L is commonly connected to the high potential output unit 4H and the low potential output unit 4L of the voltage supply unit 4, and one measurement unit 5 performs the following. The configuration for executing the measurement process is adopted. Therefore, for example, the voltage supply unit 4 and the measurement unit 5 for the inspection probes 12H1 and 12L1, the voltage supply unit 4 and the measurement unit 5 for the inspection probes 12H2 and 12L2, and the voltage supply for the inspection probes 12H3 and 12L3. 4 and measurement unit 5, and voltage supply unit 4 and measurement unit 5 for inspection probes 12H4 and 12L4 are prepared, and the insulation inspection between conductor patterns P and P for each circuit board 110 is executed in parallel. Compared with the structure to perform, it becomes possible to fully reduce the manufacturing cost of the insulation test | inspection apparatus 1. FIG.

次いで、制御部８は、記憶部９に記憶されている検査手順データＤｔに従い、図２に示すように、多面付け基板１００に対する第１回の検査処理として、移動機構１１Ｈ１，１１Ｌ１を制御して回路基板１１０ａに形成されている導体パターンＰ１，Ｐ２に検査用プローブ１２Ｈ１，１２Ｌ１を接触させ、移動機構１１Ｈ２，１１Ｌ２を制御して回路基板１１０ｂに形成されている導体パターンＰ１１，Ｐ１２に検査用プローブ１２Ｈ２，１２Ｌ２を接触させ、移動機構１１Ｈ３，１１Ｌ３を制御して回路基板１１０ｃに形成されている導体パターンＰ２１，Ｐ２２に検査用プローブ１２Ｈ３，１２Ｌ３を接触させ、移動機構１１Ｈ４，１１Ｌ４を制御して回路基板１１０ｄに形成されている導体パターンＰ３１，Ｐ３２に検査用プローブ１２Ｈ４，１２Ｌ４を接触させる。 Next, the control unit 8 controls the moving mechanisms 11H1 and 11L1 as the first inspection process for the multi-sided substrate 100 according to the inspection procedure data Dt stored in the storage unit 9, as shown in FIG. Inspection probes 12H1 and 12L1 are brought into contact with the conductor patterns P1 and P2 formed on the circuit board 110a, and the moving mechanisms 11H2 and 11L2 are controlled to check the conductor patterns P11 and P12 formed on the circuit board 110b. 12H2 and 12L2 are brought into contact, the movement mechanisms 11H3 and 11L3 are controlled to bring the inspection probes 12H3 and 12L3 into contact with the conductor patterns P21 and P22 formed on the circuit board 110c, and the movement mechanisms 11H4 and 11L4 are controlled to control the circuit. Inspection probe 1 is formed on conductor patterns P31 and P32 formed on substrate 110d. Contacting the H4,12L4.

続いて、制御部８は、各回路基板１１０毎の検査用プローブ１２Ｈを接触させた導体パターンＰ（本発明における第１の導体パターン）と検査用プローブ１２Ｌを接触させた導体パターンＰ（本発明における第２の導体パターン）との間の絶縁状態をすべての回路基板１１０に対して同時に検査する検査処理（本発明における第１の検査処理）を実行する。具体的には、制御部８は、電圧供給部４に制御信号Ｓ３を出力することによって検査用電圧Ｖの供給を開始させる。この際に、測定部５では、電圧測定部５ａが、上記の第１の導体パターンと第２の導体パターンとの間の電位差を測定して測定データＤｖを出力すると共に、電流測定部５ｂが、上記の第１の導体パターンおよび第２の導体パターンの間を導通する電流の電流値を測定して測定データＤｉを出力する。 Subsequently, the control unit 8 has the conductor pattern P (first conductor pattern in the present invention) in contact with the inspection probe 12H for each circuit board 110 and the conductor pattern P (invention) in contact with the inspection probe 12L. An inspection process (first inspection process in the present invention) for inspecting all the circuit boards 110 at the same time with respect to the insulation state between the first conductor pattern and the second conductor pattern in FIG. Specifically, the control unit 8 starts the supply of the inspection voltage V by outputting the control signal S3 to the voltage supply unit 4. At this time, in the measurement unit 5, the voltage measurement unit 5a measures the potential difference between the first conductor pattern and the second conductor pattern and outputs the measurement data Dv, and the current measurement unit 5b Then, the current value of the current conducted between the first conductor pattern and the second conductor pattern is measured, and measurement data Di is output.

また、制御部８は、測定部５から出力された測定データＤｖ，Ｄｉに基づいて、上記の第１の導体パターンおよび第２の導体パターンの間の抵抗値（絶縁抵抗値）を演算する。さらに、制御部８は、電圧供給部４に制御信号Ｓ３を出力して検査用電圧Ｖの供給を停止させると共に、演算した絶縁抵抗値と、記憶部９に記憶されている検査用基準データＤｃ（基準抵抗値）とを比較して、第１の導体パターンおよび第２の導体パターンの間の絶縁状態を各回路基板１１０に対して同時に検査する。この際に、演算した絶縁抵抗値が基準抵抗値以上のときには、制御部８は、第１の導体パターンおよび第２の導体パターンの間の絶縁状態が良好と判定して、その判定結果を記憶部９に記憶させる。一方、演算した絶縁抵抗値が基準抵抗値に満たないときには、制御部８は、第１の導体パターンおよび第２の導体パターンの間に絶縁不良が生じていると判定して、その判定結果を記憶部９に記憶させる。これにより、多面付け基板１００に対する第１回の検査処理が完了する。 Further, the control unit 8 calculates the resistance value (insulation resistance value) between the first conductor pattern and the second conductor pattern based on the measurement data Dv and Di output from the measurement unit 5. Further, the control unit 8 outputs the control signal S3 to the voltage supply unit 4 to stop the supply of the inspection voltage V, and calculates the calculated insulation resistance value and the inspection reference data Dc stored in the storage unit 9. By comparing with (reference resistance value), the insulation state between the first conductor pattern and the second conductor pattern is simultaneously inspected for each circuit board 110. At this time, when the calculated insulation resistance value is equal to or greater than the reference resistance value, the control unit 8 determines that the insulation state between the first conductor pattern and the second conductor pattern is good, and stores the determination result. Store in unit 9. On the other hand, when the calculated insulation resistance value is less than the reference resistance value, the control unit 8 determines that an insulation failure has occurred between the first conductor pattern and the second conductor pattern, and determines the determination result. Store in the storage unit 9. Thereby, the first inspection process for the multi-sided substrate 100 is completed.

続いて、制御部８は、多面付け基板１００に対する第２回の検査処理として、移動機構１１Ｈ１〜１１Ｈ４を制御して検査用プローブ１２Ｈ１〜１２Ｈ４を導体パターンＰ１，Ｐ１１，Ｐ２１，Ｐ３１に接触させた状態を維持させると共に、移動機構１１Ｌ１〜１１Ｌ４を制御して検査用プローブ１２Ｌ１〜１２Ｌ４を導体パターンＰ３，Ｐ１３，Ｐ２３，Ｐ３３にそれぞれ接触させる。次いで、制御部８は、電圧供給部４を制御して検査用電圧Ｖの供給を開始させ、これに応じて、測定部５が上記したように測定データＤｖ，Ｄｉを出力する。また、制御部８は、測定部５から出力された測定データＤｖ，Ｄｉに基づいて、上記の第１の導体パターンおよび第２の導体パターンの間の抵抗値（絶縁抵抗値）を演算する。また、制御部８は、演算結果と検査用基準データＤｃとを比較して、第１の導体パターンおよび第２の導体パターンの間の絶縁状態を各回路基板１１０に対して同時に検査して検査結果（判定結果）を記憶部９に記憶させる。これにより、多面付け基板１００に対する第２回の検査処理が完了する。 Subsequently, the control unit 8 controls the moving mechanisms 11H1 to 11H4 to bring the inspection probes 12H1 to 12H4 into contact with the conductor patterns P1, P11, P21, and P31 as the second inspection process for the multi-sided substrate 100. While maintaining the state, the moving mechanisms 11L1 to 11L4 are controlled to bring the inspection probes 12L1 to 12L4 into contact with the conductor patterns P3, P13, P23, and P33, respectively. Next, the control unit 8 controls the voltage supply unit 4 to start supplying the inspection voltage V, and in response to this, the measurement unit 5 outputs the measurement data Dv and Di as described above. Further, the control unit 8 calculates the resistance value (insulation resistance value) between the first conductor pattern and the second conductor pattern based on the measurement data Dv and Di output from the measurement unit 5. Further, the control unit 8 compares the calculation result with the inspection reference data Dc, and simultaneously inspects and inspects each circuit board 110 for the insulation state between the first conductor pattern and the second conductor pattern. The result (determination result) is stored in the storage unit 9. Thereby, the second inspection process for the multi-sided substrate 100 is completed.

次いで、制御部８は、多面付け基板１００に対する第３回〜第９回までの各検査処理として、移動機構１１Ｈ１〜１１Ｈ４を制御して検査用プローブ１２Ｈ１〜１２Ｈ４を導体パターンＰ１，Ｐ１１，Ｐ２１，Ｐ３１に接触させた状態を維持させると共に、移動機構１１Ｌ１〜１１Ｌ４を制御して検査用プローブ１２Ｌ１〜１２Ｌ４を接触させる導体パターンＰを導体パターンＰ４，Ｐ１４，Ｐ２４，Ｐ３４から導体パターンＰ１０，Ｐ２０，Ｐ３０，Ｐ４０に向かってそれぞれ１つずつ順に変更させる。また、制御部８は、上記の第１回および第２回の両検査処理時と同様にして、第１の導体パターンおよび第２の導体パターンの間の絶縁状態を各回路基板１１０に対して同時に検査して検査結果（判定結果）を記憶部９に記憶させる。さらに、制御部８は、多面付け基板１００に対する第１０回〜第１７回までの各検査処理時には、移動機構１１Ｈ１〜１１Ｈ４を制御して検査用プローブ１２Ｈ１〜１２Ｈ４を導体パターンＰ２，Ｐ１２，Ｐ２２，Ｐ３２に接触させてその状態を維持させると共に、移動機構１１Ｌ１〜１１Ｌ４を制御して検査用プローブ１２Ｌ１〜１２Ｌ４を接触させる導体パターンＰを導体パターンＰ３，Ｐ１３，Ｐ２３，Ｐ３３から導体パターンＰ１０，Ｐ２０，Ｐ３０，Ｐ４０に向かってそれぞれ１つずつ順に変更させ、その都度、第１の導体パターンおよび第２の導体パターンの間の絶縁状態を各回路基板１１０に対して同時に検査して検査結果（判定結果）を記憶部９に記憶させる。 Next, the control unit 8 controls the moving mechanisms 11H1 to 11H4 to perform the inspection probes 12H1 to 12H4 as the conductor patterns P1, P11, P21, Conductor patterns P10, P20, and P30 from conductor patterns P4, P14, P24, and P34 are maintained from the conductor patterns P4, P14, P24, and P34 while maintaining the state in contact with P31 and controlling the moving mechanisms 11L1 to 11L4 to contact the inspection probes 12L1 to 12L4. , P40 one by one in order toward P40. Further, the control unit 8 determines the insulation state between the first conductor pattern and the second conductor pattern with respect to each circuit board 110 in the same manner as in both the first and second inspection processes. At the same time, the inspection result (determination result) is stored in the storage unit 9. Further, the control unit 8 controls the moving mechanisms 11H1 to 11H4 to place the inspection probes 12H1 to 12H4 in the conductor patterns P2, P12, P22, and the like in the 10th to 17th inspection processes for the multi-sided substrate 100. P32 is brought into contact with P32 and the state thereof is maintained, and the movement patterns 11L1 to 11L4 are controlled to contact the inspection probes 12L1 to 12L4 with the conductor patterns P3, P13, P23, and P33 to the conductor patterns P10, P20, Each of the circuit boards 110 is inspected simultaneously for the insulation state between the first conductor pattern and the second conductor pattern, and the inspection result (determination result). ) Is stored in the storage unit 9.

この後、制御部８は、多面付け基板１００に対する第１８回〜第４５回までの各検査処理として、各検査用プローブ１２Ｈ，１２Ｌを接触させる導体パターンＰを検査手順データＤｔに従って変更させて（各導体パターンＰに対する検査用プローブ１２Ｈ，１２Ｌの接触態様を変更させて）、その都度、第１の導体パターンおよび第２の導体パターンの間の絶縁状態を各回路基板１１０に対して同時に検査して検査結果（判定結果）を記憶部９に記憶させる。これにより、多面付け基板１００に対する４５回の第１の検査処理が完了し、この第４５回の第１の検査処理の完了時点において、各回路基板１１０を構成する回路基板１１０ａ〜１１０ｄのすべてについて、導体パターンＰ，Ｐの間に絶縁不良が生じているか否かの検査が完了する。したがって、４５回の検査処理のすべてにおいて、絶縁状態が良好であったときには、制御部８は、その多面付け基板１００を良品の多面付け基板１００と判定して、一連の検査処理を終了する。 Thereafter, the control unit 8 changes the conductor pattern P with which each of the inspection probes 12H and 12L is brought into contact according to the inspection procedure data Dt as the 18th to 45th inspection processes for the multi-sided substrate 100 ( Each time the circuit board 110 is inspected simultaneously for the insulation state between the first conductor pattern and the second conductor pattern (by changing the contact mode of the inspection probes 12H and 12L with respect to each conductor pattern P). The inspection result (determination result) is stored in the storage unit 9. Thereby, the 45th first inspection process for the multi-sided substrate 100 is completed, and all the circuit boards 110a to 110d constituting each circuit board 110 are completed when the 45th first inspection process is completed. Then, the inspection of whether or not an insulation failure has occurred between the conductor patterns P and P is completed. Therefore, when the insulation state is good in all 45 inspection processes, the control unit 8 determines that the multi-sided substrate 100 is a non-defective multi-sided substrate 100 and ends the series of inspection processes.

この場合、１枚の多面付け基板に対する第１の検査処理の処理回数（検査回数）Ｃは、前述したように、各回路基板１１０に形成されている導体パターンＰの数を「Ｍ」としたときに、「Ｃ＝Ｍ（Ｍ−１）／２」との式によって表される。したがって、回路基板１１０に形成されている導体パターンＰの数が１０（すなわち、「Ｍ＝１０」）のこの例では、各回路基板１１０毎のすべての導体パターンＰの絶縁状態を検査するためには、上記したように、検査回数Ｃ＝１０（１０−１）／２＝４５回の検査（第１の検査処理）が必要となっている。また、出願人が開示している回路基板検査装置による検査方法では、前述したように、各回路基板１１０に対して上記の４５回の検査処理を順次実行するため、１枚の多面付け基板１００の良否を検査するのに要する検査処理の回数は、上記の４５回に、多面付け基板１００を構成している回路基板１１０の数（この例では、「４」）を乗じた１８０回となっている。これに対して、この絶縁検査装置１による絶縁検査方法では、上記したように、各回路基板１１０に対する４５回の第１の検査処理を各回路基板１１０に対して同時に実行しているため、１枚の多面付け基板１００が良品であると検査するのに要する検査処理の回数が４５回（出願人が開示している回路基板検査装置による検査方法の回数に対して１／４）となっている。 In this case, the number of times of the first inspection processing (number of inspections) C for one multi-sided substrate is “M”, as described above, where the number of conductor patterns P formed on each circuit board 110 is “M”. Sometimes expressed by the equation “C = M (M−1) / 2”. Therefore, in this example in which the number of conductor patterns P formed on the circuit board 110 is 10 (that is, “M = 10”), in order to inspect the insulation state of all the conductor patterns P for each circuit board 110 As described above, the number of inspections C = 10 (10-1) / 2 = 45 inspections (first inspection process) is required. Further, in the inspection method using the circuit board inspection apparatus disclosed by the applicant, as described above, since the 45 times of inspection processes are sequentially performed on each circuit board 110, one multi-sided substrate 100 is provided. The number of inspection processes required for inspecting the quality of the product is 180 times obtained by multiplying the above 45 times by the number of circuit boards 110 constituting the multi-sided substrate 100 (in this example, “4”). ing. On the other hand, in the insulation inspection method using the insulation inspection apparatus 1, as described above, the first inspection process for 45 times for each circuit board 110 is simultaneously performed for each circuit board 110. The number of inspection processes required for inspecting that the multi-sided substrate 100 is a non-defective product is 45 times (1/4 of the number of inspection methods by the circuit board inspection apparatus disclosed by the applicant). Yes.

一方、この絶縁検査装置１では、上記の４５回の第１の検査処理時のいずれかにおいて絶縁状態を不良と検査したときには、各回路基板１１０毎に上記の第１の導体パターンおよび第２の導体パターンの間の絶縁状態を個別的に検査する検査処理（本発明における第２の検査処理）を実行する。 On the other hand, in this insulation inspection apparatus 1, when the insulation state is inspected as defective in any of the 45 times of the first inspection processes, the first conductor pattern and the second conductor for each circuit board 110. An inspection process (second inspection process in the present invention) for individually inspecting the insulation state between the conductor patterns is executed.

具体的には、例えば第４４回の検査処理時に絶縁不良が生じていると検査したときには、制御部８は、一例として、まず、上記の回路基板１１０ａに対する第２の検査処理を実行する。より具体的には、制御部８は、移動機構１１Ｈ１，１１Ｌ１を制御して検査用プローブ１２Ｈ１，１２Ｌ１を導体パターンＰ８（本発明における第１の導体パターン）および導体パターンＰ１０（本発明における第２の導体パターン）にそれぞれ接触させた状態において、上記の第１の導体パターンおよび第２の導体パターンの間の絶縁状態を検査する。この際に、絶縁状態が良好と検査したときには、制御部８は、回路基板１１０ｂに対する第２の検査処理を実行する。具体的には、移動機構１１Ｈ２，１１Ｌ２を制御して検査用プローブ１２Ｈ２，１２Ｌ２を導体パターンＰ１８（本発明における第１の導体パターン）および導体パターンＰ２０（本発明における第２の導体パターン）にそれぞれ接触させた状態において、上記の第１の導体パターンおよび第２の導体パターンの間の絶縁状態を検査する。 Specifically, for example, when it is inspected that an insulation failure has occurred during the 44th inspection process, for example, the control unit 8 first executes the second inspection process for the circuit board 110a. More specifically, the control unit 8 controls the moving mechanisms 11H1 and 11L1 to place the inspection probes 12H1 and 12L1 into the conductor pattern P8 (first conductor pattern in the present invention) and the conductor pattern P10 (second in the present invention). Insulation state between the first conductor pattern and the second conductor pattern is inspected in a state in which the conductor pattern is in contact with each other. At this time, when it is inspected that the insulation state is good, the control unit 8 executes a second inspection process for the circuit board 110b. Specifically, the moving probes 11H2 and 11L2 are controlled to place the inspection probes 12H2 and 12L2 on the conductor pattern P18 (first conductor pattern in the present invention) and the conductor pattern P20 (second conductor pattern in the present invention), respectively. In the state of contact, the insulation state between the first conductor pattern and the second conductor pattern is inspected.

この際に、絶縁不良が生じていると検査したときには、制御部８は、導体パターンＰ１８，Ｐ２０の間に絶縁不良が生じている（回路基板１１０ｂが不良である）との検査結果（判定結果）を記憶部９に記憶させた後に、回路基板１１０ｃ，１１０ｄに対する第２の検査処理をそれぞれ実行し、導体パターンＰ２８，Ｐ３０の間の絶縁状態、および導体パターンＰ３８，Ｐ４０の間の絶縁状態をそれぞれ検査して検査結果（判定結果：一例として、良好との検査結果）を記憶部９に記憶させる。この後、制御部８は、導体パターンＰ１８，Ｐ２０の間に絶縁不良が生じた不良の多面付け基板１００として、この多面付け基板１００についての一連の検査処理を終了する。なお、この例では、多面付け基板１００についての第２の検査処理を４回に亘って実行しているため、多面付け基板１００を構成する各回路基板１１０のうちのいずれの導体パターンＰ，Ｐの間に不良が生じているかを特定するのに要した検査回数が４９回となっている。 At this time, when it is inspected that an insulation failure has occurred, the control unit 8 performs an inspection result (determination result) that an insulation failure has occurred between the conductor patterns P18 and P20 (the circuit board 110b is defective). ) Is stored in the storage unit 9, the second inspection process is performed on the circuit boards 110c and 110d, respectively, and the insulation state between the conductor patterns P28 and P30 and the insulation state between the conductor patterns P38 and P40 are determined. Each inspection is performed, and the inspection result (determination result: as an example, the inspection result of good) is stored in the storage unit 9. Thereafter, the control unit 8 ends the series of inspection processes for the multi-sided substrate 100 as a defective multi-sided substrate 100 in which an insulation failure has occurred between the conductor patterns P18 and P20. In this example, since the second inspection process for the multi-sided board 100 is performed four times, any of the conductor patterns P, P of the circuit boards 110 constituting the multi-sided board 100 is used. The number of inspections required to identify whether or not a defect occurred during the period is 49.

このように、この絶縁検査装置１、および絶縁検査装置１による絶縁検査方法によれば、Ｎ個（この例では、Ｎ＝４個）の回路基板１１０ａ〜１１０ｄが面付けされた多面付け基板１００を検査対象として検査するときに、各回路基板１１０毎の本発明における第１の導体パターン（検査用プローブ１２Ｈが接触している導体パターンＰ）および本発明における第２の導体パターン（検査用プローブ１２Ｌが接触している導体パターンＰ）の間の絶縁状態を、Ｎ組（この例では、Ｎ＝４組）の検査用プローブ１２Ｈ，１２Ｌを使用して第１の導体パターン同士を互いに同電位（この例では、Ｈ電位）にすると共に第２の導体パターン同士を互いに同電位（この例では、Ｌ電位）にした状態で各回路基板１１０に対して同時に検査する検査処理（第１の検査処理）を各導体パターンＰに対する各検査用プローブ１２Ｈ，１２Ｌの接触態様を変更して複数回に亘って実行することにより、第１の検査処理時に各回路基板１１０内の第１の導体パターンおよび第２の導体パターンの間の絶縁状態をすべての回路基板１１０に対して同時に検査する分だけ、１枚の多面付け基板１００を検査するのに要する検査処理の回数を十分に低減することができる。したがって、この絶縁検査装置１、および絶縁検査装置１による絶縁検査方法によれば、すべての導体パターンＰ１〜Ｐ４０の相互間における絶縁状態の良否を検査しつつ多面付け基板１００の絶縁検査に要する時間を十分に短縮することができる。 As described above, according to the insulation inspection apparatus 1 and the insulation inspection method by the insulation inspection apparatus 1, the multi-sided board 100 on which N (N = 4 in this example) circuit boards 110a to 110d are faced. Are inspected as inspection targets, the first conductor pattern in the present invention (conductor pattern P in contact with the inspection probe 12H) and the second conductor pattern in the present invention (inspection probe) for each circuit board 110. The insulation state between the conductor patterns P) in contact with 12L is determined by using N sets (in this example, N = 4 sets) of inspection probes 12H and 12L, and the first conductor patterns have the same potential. (In this example, an H potential) and an inspection process for simultaneously inspecting each circuit board 110 in a state where the second conductor patterns are at the same potential (L potential in this example). The first inspection process) is performed over a plurality of times while changing the contact mode of the inspection probes 12H and 12L with respect to the respective conductor patterns P, so that the first in each circuit board 110 is performed during the first inspection process. The number of inspection processes required for inspecting one multi-sided substrate 100 is sufficiently reduced by inspecting all the circuit boards 110 simultaneously with the insulation state between the conductor pattern and the second conductor pattern. can do. Therefore, according to the insulation inspection apparatus 1 and the insulation inspection method by the insulation inspection apparatus 1, the time required for the insulation inspection of the multi-sided substrate 100 while inspecting the quality of the insulation state between all the conductor patterns P1 to P40. Can be shortened sufficiently.

また、この絶縁検査装置１、および絶縁検査装置１による絶縁検査方法によれば、本発明における第１の検査処理時において絶縁状態を不良と検査したときに、各回路基板１１０毎に本発明における第１の導体パターンおよび第２の導体パターンの間の絶縁状態を個別的に検査する検査処理（第２の検査処理）を実行することにより、多面付け基板１００の絶縁検査に要する時間を十分に短縮しつつ、絶縁不良の生じている導体パターンＰ，Ｐを確実に特定することができる。 Further, according to the insulation inspection apparatus 1 and the insulation inspection method by the insulation inspection apparatus 1, when the insulation state is inspected as defective during the first inspection process in the present invention, each circuit board 110 is in accordance with the present invention. By executing the inspection process (second inspection process) for individually inspecting the insulation state between the first conductor pattern and the second conductor pattern, the time required for the insulation inspection of the multi-sided substrate 100 is sufficiently provided. It is possible to reliably identify the conductor patterns P and P in which insulation failure occurs while shortening.

なお、本発明は、上記の構成に限定されない。例えば、４個の回路基板１１０ａ〜１１０ｄが面付けされた多面付け基板１００を検査対象として検査する例について説明したが、検査対象の多面付け基板を構成する回路基板の数（本発明における「Ｎ」）は「４」に限定されず、「２」、「３」または「５以上」の個数の回路基板が面付けされた多面付け基板（図示せず）を検査対象として検査することができる。また、本発明における第１の検査処理において絶縁状態を不良と検査したときに、本発明における第２の検査処理を実行することなく、例えば第１の検査処理を完了した時点において、多面付け基板を不良として一連の検査処理を終了する方法および構成や、第１の検査処理時に不良と検査した時点において、他のすべての検査処理を実行することなく、多面付け基板を不良として一連の検査処理を終了する方法および構成を採用することができる。このような方法および構成を採用することにより、不良の多面付け基板についての検査時間を一層短縮することができる。 In addition, this invention is not limited to said structure. For example, the example in which the multi-sided board 100 on which the four circuit boards 110a to 110d are imbedded has been described as an inspection target, but the number of circuit boards constituting the multi-sided board to be inspected (“N ")" Is not limited to "4", and a multi-sided board (not shown) on which a number of circuit boards of "2", "3", or "5 or more" are imbedded can be inspected as an inspection target. . Further, when the insulation state is inspected as defective in the first inspection process according to the present invention, for example, when the first inspection process is completed without executing the second inspection process according to the present invention, the multi-sided substrate And a series of inspection processes in which a multi-sided substrate is regarded as defective without performing all other inspection processes at the time of inspecting it as defective during the first inspection process. A method and a configuration for ending can be adopted. By adopting such a method and configuration, the inspection time for a defective multi-sided substrate can be further shortened.

絶縁検査装置１の構成を示すブロック図である。1 is a block diagram showing a configuration of an insulation inspection apparatus 1. FIG. 絶縁検査装置１による多面付け基板１００の絶縁検査方法について説明するための説明図である。It is explanatory drawing for demonstrating the insulation test | inspection method of the multi-sided board | substrate 100 by the insulation test | inspection apparatus 1. FIG. 多面付け基板１００（回路基板１１０ａ〜１１０ｄ）の平面図である。It is a top view of the multi-sided board | substrate 100 (circuit board 110a-110d). 多面付け基板１００を検査対象とする従来の絶縁検査方法について説明するための説明図である。It is explanatory drawing for demonstrating the conventional insulation test | inspection method which uses the multi-sided board | substrate 100 as a test object.

Explanation of symbols

１絶縁検査装置
２プローブ機構
３接続切替部
４電圧供給部
４Ｈ高電位出力部
４Ｌ低電位出力部
５測定部
８制御部
１１Ｈ１〜１１Ｈ４，１１Ｌ１〜１１Ｌ４移動機構
１２Ｈ１〜１２Ｈ４，１２Ｌ１〜１２Ｌ４検査用プローブ
１００多面付け基板
１１０ａ〜１１０ｄ回路基板
Ｄｔ検査手順データ
Ｐ１〜Ｐ４０導体パターン
Ｓ１〜Ｓ３制御信号
Ｖ検査用電圧 DESCRIPTION OF SYMBOLS 1 Insulation inspection apparatus 2 Probe mechanism 3 Connection switching part 4 Voltage supply part 4H High potential output part 4L Low potential output part 5 Measurement part 8 Control part 11H1-11H4, 11L1-11L4 Moving mechanism 12H1-12H4, 12L1-12L4 Inspection probe 100 Multi-sided board 110a to 110d Circuit board Dt Inspection procedure data P1 to P40 Conductor pattern S1 to S3 Control signal V Inspection voltage

Claims

The pair of test probes to a plurality of conductor patterns in which a plurality of circuit boards to be inspected is moved by independently a pair of test probes are formed in the respective circuit board in the multi with substrate that is imposition One of the pair of inspection probes is connected to a high potential output section that outputs a high potential in the voltage supply section, and the other of the pair of inspection probes is connected to a low potential section in the voltage supply section. In a state of being connected to a low potential output unit that outputs a potential, an inspection voltage is supplied from the voltage supply unit via the pair of inspection probes and the one inspection probe of the conductor patterns is contacted An electrical parameter between the first conductor pattern made to contact and the second conductor pattern in contact with the other inspection probe of the conductor patterns The inspection process for inspecting the insulation state between the first conductor pattern and the second conductor pattern based on the measured electrical parameter is changed in the contact mode of the pair of inspection probes with respect to the conductor patterns. Insulation inspection method for inspecting the insulation state between each conductor pattern by performing over a plurality of times,
When inspecting the multi-sided substrate on which the N (N is a natural number of 2 or more) circuit boards are inspected as an inspection target, the inspection for each of the N circuit boards is performed as the plurality of inspection processes. The insulation state between the first conductor pattern and the second conductor pattern is set such that the first conductor patterns have the same potential using the N sets of inspection probes, and the second conductor pattern. An insulation inspection method in which a first inspection process for simultaneously inspecting each circuit board in a state where they are at the same potential is performed a plurality of times by changing the contact mode.

Inspecting the insulation state between the first conductor pattern and the second conductor pattern individually for each circuit board when the insulation state is inspected as defective in the first inspection process. The insulation inspection method according to claim 1, wherein the inspection process of 2 is executed.

The pair of test probes to a plurality of conductor patterns in which a plurality of circuit boards to be inspected is moved by independently a pair of test probes are formed in the respective circuit board in the multi with substrate that is imposition A probe moving mechanism to be contacted, a voltage supply unit that supplies a voltage for inspection to each conductor pattern via the pair of inspection probes, and the conductor pattern among the conductor patterns in a state where the voltage for inspection is supplied A first conductor pattern that is in contact with the inspection probe connected to a high potential output unit that outputs a high potential in the voltage supply unit and a low potential that outputs a low potential in the voltage supply unit among the conductor patterns. An electrical parameter between the second conductor pattern in contact with the inspection probe connected to the potential output unit is measured, and the measured electrical parameter is measured. An inspection unit that performs an inspection process for inspecting an insulation state between the first conductor pattern and the second conductor pattern based on the data, and the inspection unit controls the probe moving mechanism to By changing the contact mode of the pair of inspection probes with respect to each conductor pattern and controlling the voltage supply unit to supply the inspection voltage and performing the inspection process a plurality of times, between the conductor patterns An insulation inspection device for inspecting the insulation state of each
When the inspection unit inspects the multi-sided substrate on which the N (N is a natural number of 2 or more) circuit boards are inspected as an inspection target, the inspection unit performs the N times as the inspection process. The insulation state between the first conductor pattern and the second conductor pattern for each circuit board is set so that the first conductor patterns have the same potential with each other using N sets of the inspection probes. An insulation inspection apparatus for performing a first inspection process for simultaneously inspecting each circuit board in a state where the second conductor patterns are at the same potential with each other by changing the contact mode and performing a plurality of times.