JP5208569B2 - 半導体装置 - Google Patents
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- DUMHRFXBHXIRTD-UHFFFAOYSA-N Tantalum carbide Chemical compound [Ta+]#[C-] DUMHRFXBHXIRTD-UHFFFAOYSA-N 0.000 claims description 30
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- FAPWRFPIFSIZLT-UHFFFAOYSA-M Sodium chloride Chemical compound [Na+].[Cl-] FAPWRFPIFSIZLT-UHFFFAOYSA-M 0.000 claims description 12
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- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 2
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- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical group [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/823842—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Thin Film Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
Description
TaC(111)配向性は、(1)式の分子をTaC(111)ピーク強度に置き換えることにより求められる。図10(b)、図11(b)より、本発明のTaリッチ組成TaxC1-x層においては、TaC(200)面の結晶配向比率は50%より大きいことがわかる。即ち、本発明では、ゲート電極層とゲート絶縁膜の界面の法線方向に対するTaC(200)面の結晶配向比率[TaC(200)面/{TaC(200)面+TaC(111)面}]は、50%より大きいことを特徴とする。
ΔTinv∝y*d=(2x−1)*d (2)
が考えられる。
式(3)に従うと、#3と同等の効果を得るための最も薄いdはx=1の場合に得えられ、d>0.54nmとなる。このことは、ゲート絶縁膜と別の耐熱メタル層、例えばCリッチ組成TaxC1-x電極層の間に0.54nmの100%Ta層を挿入した電極構造を形成すれば、#3と同等の効果が得られることを示している。
第1の実施形態に係るCMIS半導体装置は、本発明の共通概念を説明するのに用いた図1と同一になるので図1を援用し、既に説明した部分の説明は省略する。第1の実施形態のCMIS半導体装置におけるゲート電極6、16は、Taリッチ組成TaxC1-x電極層(x>0.5)の単層である。
図22は、第2の実施形態に係るCMOS半導体装置の断面図である。図1と共通部分には共通番号を付して、重複する説明を省略する。第2の実施形態のCMOS半導体装置は、積層ゲート電極構造を有し、TaリッチTaxC1-x電極層61 、161 と、その上に形成されたポリシリコン電極62 ,162 を有することである。ポリシリコン電極は、従来のMOS半導体装置において賞用されていた材料であり、従来の半導体プロセスとの適合性に優れている。
図23は、本発明の第3の実施形態に係るCMOS半導体装置を表す模式断面図である。第3の実施形態の半導体装置は、Taリッチ組成TaxC1-x電極層(x>0.5)61 、161 、耐熱メタル層63 、163 、多結晶Si層62 、162 の三層を有する積層電極構造をp チャネルMISトランジスタ、nチャネルMISトランジスタの両方のゲート電極として有することを特徴としている。
FIG.24は、第4の実施形態に係るCMIS半導体装置の概略構成を示す斜視図である。本実施形態は、p型、n型の半導体領域を基板表面から突出させた、所謂FinFETに適用したものである。
2…p型ウェル領域
3…n型ウェル領域
4…素子分離層
5、15、34,35、…ゲート絶縁膜
6,16、36…ゲート電極
61 ,161 …TaリッチTaC層
62 ,162 …耐熱メタル層
63 ,163 …ポリシリコン層
8,18、37…側壁絶縁膜
9,19…エクステンション領域
10,20…ディープ領域
24、31…層間(埋め込み)絶縁膜
32…p型Si領域
33…n型SiGe領域
Claims (10)
- 半導体基板と、前記半導体基板上に形成されたpチャネルMISトランジスタとnチャネルMISトランジスタとを具備し、
前記pチャネルMISトランジスタとnチャネルMISトランジスタは、前記半導体基板上に形成されたゲート絶縁膜と、前記ゲート絶縁膜上に形成されたゲート電極層を夫々備え、
前記pチャネルMISトランジスタとnチャネルMISトランジスタの前記ゲート電極における、少なくとも前記ゲート絶縁膜と接する最下層は、TaとCを含む同一組成を有し、CとTaとの合計に対するTaのモル比(Ta/(Ta+C))が0.5より大であり、前記最下層は同一配向性を有することを特徴とする半導体装置。 - 半導体基板と、前記半導体基板上に形成されたpチャネルMISトランジスタとnチャネルMISトランジスタとを具備し、
前記pチャネルMISトランジスタとnチャネルMISトランジスタは、前記半導体基板上に形成されたゲート絶縁膜と、前記ゲート絶縁膜上に形成された、TaとCを含む同一の組成と同一の配向性を有するゲート電極層と、前記ゲート電極層上に形成されたポリシリコン層を夫々備え、
前記ゲート電極層のCとTaとの合計に対するTaのモル比(Ta/(Ta+C))が0.5より大であることを特徴とする半導体装置。 - 半導体基板上と、前記半導体基板上に形成されたpチャネルMISトランジスタとnチャネルMISトランジスタを具備し、
前記pチャネルMISトランジスタとnチャネルMISトランジスタは、前記半導体基板上に形成されたゲート絶縁膜と、前記ゲート絶縁膜上に形成された、TaとCを含む同一の組成と同一の配向性を有する第1のゲート電極層と、前記第1のゲート電極層に接して積層された金属よりなる第2のゲート電極層と、前記第2のゲート電極層上に形成されたポリシリコン層を夫々備え、
前記第1のゲート電極層のCとTaとの合計に対するTaのモル比(Ta/(Ta+C))が0.5より大であることを特徴とする半導体装置。 - 前記第2のゲート電極層はTaとCを含む合金からなり、前記第2のゲート電極層のCとTaとの合計に対するTaのモル比(Ta/(Ta+C))が0.5以下であることを特徴とする請求項3に記載の半導体装置。
- 前記第2のゲート電極層はTiとNを含む合金からなることを特徴とする請求項3に記載の半導体装置。
- 前記第1のゲート電極層は、NaCl型構造からなる多結晶構造であることを特徴とする請求項1乃至5のいずれかに記載の半導体装置。
- 前記第1のゲート電極層の膜厚は、0.5nm以上、10nm以下であることを特徴とする請求項1乃至6のいずれかに記載の半導体装置。
- 前記第1のゲート電極層と前記ゲート絶縁膜の界面の法線方向に対するTaC(200)面の結晶配向比率[TaC(200)面/{TaC(200)面+TaC(111)面}]は、50%より大きいことを特徴とする請求項1乃至7のいずれかに記載の半導体装置。
- 前記ゲート絶縁膜が、HfとSiとを含むことを特徴とする請求項1乃至8のいずれかに記載の半導体装置。
- 前記ゲート絶縁膜は、前記pチャネル型トランジスタ用には、Alを含み、前記nチャネル用には、La,Ce,Pr,Tb,Dy,Er、Yb,Y、Mg,Sr,Baのいずれかを含むことを特徴とする請求項1乃至9のいずれかに記載の半導体装置。
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US8679962B2 (en) | 2008-08-21 | 2014-03-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuit metal gate structure and method of fabrication |
US8941171B2 (en) * | 2010-07-02 | 2015-01-27 | Micron Technology, Inc. | Flatband voltage adjustment in a semiconductor device |
US20120313149A1 (en) * | 2011-06-09 | 2012-12-13 | Beijing Nmc Co., Ltd. | Semiconductor structure and method for manufacturing the same |
US8766379B2 (en) | 2011-09-22 | 2014-07-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Multi-layer scavenging metal gate stack for ultra-thin interfacial dielectric layer |
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