JP5199437B2 - Wiring board and manufacturing method thereof - Google Patents

Description

  The present invention relates to a wiring board and a manufacturing method thereof.

  Patent Document 1 discloses a wiring board including forming a hole in an interlayer insulating layer, forming an electroless copper plating film on a wall surface of the hole, and filling electrolytic copper plating in the hole Manufacturing method (specifically, a method for forming a filled via as an interlayer connection) and a wiring board manufactured by this manufacturing method are disclosed.

JP 2003-31952 A

In the method for manufacturing a wiring board disclosed in Patent Document 1, electrolytic copper plating is filled in the holes under the following conditions. That is, as a copper plating solution, “a liquid composition is 170 to 240 g / L of copper sulfate, 30 to 80 g / L of sulfuric acid, and 20 to 60 mg / L of chloride ions, and further, for example, Cubelite VF-II (trade name, “Used as an additive” (see paragraph “0035” of Patent Document 1), and plating conditions of “bath temperature 20-30 ° C., current density 2-5 A / dm ² , preferably It is set to ² to 3 A / dm ² and the plating solution is stirred by an air method or a jet method ”(see paragraph“ 0036 ”of Patent Document 1).

  However, in such electrolytic plating, when a filled metal is formed by filling a small diameter via hole formed on a conductor layer to form a filled conductor, a seam is likely to occur between the conductor layer and the filled conductor. In addition, in order to obtain a good electroless copper plating film as a power feeding layer, formalin or the like is required as a reducing agent, and palladium (Pb) that is a rare metal is required as a catalyst. It tends to be disadvantageous.

  The present invention has been made in view of such circumstances, and an object thereof is to suppress seam generation between a conductor layer and a filled conductor. It is another object of the present invention to obtain a good power supply layer with a small environmental load or low cost. Another object of the present invention is to form a filled conductor with high productivity.

The wiring board according to the present invention is
A core insulating layer having a first surface and a second surface opposite thereto;
A plurality of first surface side conductor layers formed on the first surface side of the core insulating layer;
A plurality of second surface side conductor layers formed on the second surface side of the core insulating layer;
A first surface side interlayer insulating layer formed between the first surface side conductor layers;
A second surface side interlayer insulating layer formed between the second surface side conductor layers,
A through hole conductor having one end connected to the first surface side conductor layer and the other end connected to the second surface side conductor layer;
A wiring board having
Via conductors including a power supply layer and electrolytic plating formed on the power supply layer are formed in each of the first surface side interlayer insulating layer and the second surface side interlayer insulating layer,
The through-hole conductor includes a power feeding layer made of electroless plating, and electrolytic plating formed on the power feeding layer,
The feed layer of the via conductor formed in the first surface side interlayer insulating layer below the first surface side conductor layer to which one end of the through hole conductor is connected is connected to the other end of the through hole conductor. Each of the power supply layers of the via conductor formed in the second surface side interlayer insulating layer under the second surface side conductor layer is made of electroless plating, and the other power supply layers of the via conductor are Each is made of a material different from electroless plating.

  The material different from the electroless plating is preferably graphite.

  It is preferable that the through-hole conductor penetrates the wiring board and electrically connects the outermost first surface side conductor layer and the outermost layer second surface side conductor layer to each other.

  It is preferable that the number of the first surface-side conductor layers and the number of the second surface-side conductor layers are each 5 or more.

  In the wall surface of the through hole, it is preferable that at least one of the first surface side conductor layer of the inner layer and the second surface side conductor layer of the inner layer is electrically connected to the through hole conductor.

A hole penetrating the core insulating layer is formed in the core insulating layer,
The wiring board is formed on the wall surface of the hole on the first surface side conductor layer formed on the first surface of the core insulating layer and on the second surface of the core insulating layer. Having a connection conductor for electrically connecting the surface-side conductor layers to each other;
The connection conductor includes a power feeding layer made of graphite, and electrolytic plating formed on the power feeding layer.
It is preferable.

  The hole penetrating the core insulating layer is preferably filled with the power feeding layer and the electrolytic plating.

  The via conductor formed in each of the first surface side interlayer insulating layer and the second surface side interlayer insulating layer is formed in each of the first surface side interlayer insulating layer and the second surface side interlayer insulating layer. It is preferable that the via hole is filled with the power feeding layer and the electrolytic plating.

  The first surface side conductor layer and the second surface side conductor layer each include a power feeding layer made of at least one of electroless plating and metal foil, and electrolytic plating formed on the power feeding layer. Is preferred.

A method for manufacturing a wiring board according to the present invention includes:
Providing a core insulating layer having a first surface and a second surface opposite the first surface;
Forming a plurality of first surface-side conductor layers formed on the first surface side of the core insulating layer and a first surface-side interlayer insulating layer formed between the first surface-side conductor layers; When,
Forming a plurality of second surface side conductor layers formed on the second surface side of the core insulating layer and a second surface side interlayer insulating layer formed between the second surface side conductor layers; When,
Forming a via hole in each of the first surface side interlayer insulating layer and the second surface side interlayer insulating layer, and forming a via conductor in the via hole;
A through hole is formed in the core insulating layer, the first surface side interlayer insulating layer, and the second surface side interlayer insulating layer, and one end is connected to the first surface side conductor layer in the through hole, Forming a through-hole conductor having the other end connected to the second surface side conductor layer;
A method of manufacturing a wiring board including:
Formation of the through-hole conductor, formation of the via conductor formed in the first-surface-side interlayer insulating layer under the first-surface-side conductor layer to which one end of the through-hole conductor is connected, and the through-hole conductor In the formation of the via conductors formed in the second surface side interlayer insulating layer below the second surface side conductor layer to which the other end is connected, after forming a power supply layer made of electroless plating, the power supply layer Electrolytic plating is performed while supplying power to the electroplating layer on the power supply layer,
In the formation of the other via conductors, after forming a power feeding layer made of a material different from electroless plating, electrolytic plating is performed while feeding power to the power feeding layer to form electrolytic plating on the power feeding layer.

  The material different from the electroless plating is preferably graphite.

  It is preferable that the through-hole conductor penetrates the wiring board and electrically connects the outermost first surface side conductor layer and the outermost layer second surface side conductor layer to each other.

  By forming the through hole, at least one of the first-surface-side conductor layer of the inner layer and the second-surface-side conductor layer of the inner layer is scraped, and the scraped conductor layer is exposed to the wall surface of the through-hole. Is preferred.

  According to the present invention, it is possible to suppress seam generation between the conductor layer and the filled conductor. Further, according to the present invention, in addition to or instead of this effect, there may be an effect that a high-quality power supply layer can be obtained with a small environmental load or low cost. Moreover, according to this invention, in addition to this effect or instead of this effect, the effect that a filled conductor can be formed with high productivity may be show | played.

It is sectional drawing which shows the wiring board which concerns on Embodiment 1 of this invention. It is a figure which shows arrangement | positioning of the through-hole and filled stack of the wiring board which concern on Embodiment 1 of this invention. It is a figure which expands and shows a part of FIG. It is sectional drawing which shows the via conductor of the outermost layer of the wiring board which concerns on Embodiment 1 of this invention. It is sectional drawing which shows the via conductor of the inner layer of the wiring board which concerns on Embodiment 1 of this invention. It is sectional drawing which shows the connection conductor of the core part of the wiring board which concerns on Embodiment 1 of this invention. It is sectional drawing for demonstrating the 1st process of forming a core part in the manufacturing method of the wiring board which concerns on Embodiment 1 of this invention. It is sectional drawing for demonstrating the 2nd process after the process of FIG. 5A. It is sectional drawing for demonstrating the 3rd process after the process of FIG. 5B. It is sectional drawing for demonstrating the 4th process after the process of FIG. 5C. In the manufacturing method of the wiring board which concerns on Embodiment 1 of this invention, it is sectional drawing for demonstrating the 1st process of forming an electric power feeding layer in the wall surface of a bottomed hole. It is sectional drawing for demonstrating the 2nd process after the process of FIG. It is a top view which shows the example of the form of the electric power feeding layer formed by the process of FIG.6 and FIG.7. In the manufacturing method of the wiring board concerning Embodiment 1 of the present invention, it is a figure showing typically the example of composition of the device for performing electroplating with a pulse power supply. In the manufacturing method of the wiring board concerning Embodiment 1 of the present invention, it is a figure showing typically the example of the voltage waveform between the 1st electrode and the 2nd electrode in the case of performing electroplating with a pulse power supply. In the manufacturing method of the wiring board which concerns on Embodiment 1 of this invention, it is sectional drawing which shows a mode that a bottomed hole is filled with a plating metal by electrolytic plating. It is a figure which shows the voltage between a 1st electrode and a 2nd electrode in the example which performs electroplating with the DC power supply on the wiring board which has an electric power feeding layer which consists of electroless plating (chemical copper). In the example of FIG. 12, it is sectional drawing which shows a mode that a bottomed hole is filled with a plating metal by electrolytic plating. It is a figure which shows the electroplating characteristic about each electric power feeding layer which consists of a different material. It is sectional drawing for demonstrating the process of forming an etching resist in the manufacturing method of the wiring board which concerns on Embodiment 1 of this invention. FIG. 15B is a cross-sectional view for explaining a step of etching using the etching resist shown in FIG. 15A in the wiring board manufacturing method according to Embodiment 1 of the present invention. In the manufacturing method of the wiring board concerning Embodiment 1 of this invention, it is sectional drawing for demonstrating the 1st process of forming an inner layer buildup part on both surfaces of a core part. It is sectional drawing for demonstrating the 2nd process after the process of FIG. 16A. FIG. 16D is a cross-sectional view for explaining a third step after the step of FIG. 16B. FIG. 16D is a cross-sectional view for explaining a fourth step after the step of FIG. 16C. It is sectional drawing for demonstrating the 5th process after the process of FIG. 16D. FIG. 18 is a cross-sectional view for explaining a sixth step after the step of FIG. 17. In the manufacturing method of the wiring board which concerns on Embodiment 1 of this invention, it is sectional drawing for demonstrating the 1st process of forming the outermost layer and through-hole conductor of the said wiring board. FIG. 20 is a cross-sectional view for explaining a second step after the step of FIG. 19. It is sectional drawing which expands and shows the through hole formed by the process of FIG. It is a figure which shows an example of the planar shape of the conductor layer shaved by the process of FIG. It is sectional drawing for demonstrating the 3rd process after the process of FIG. It is sectional drawing for demonstrating the 4th process after the process of FIG. 23A. It is sectional drawing for demonstrating the 1st process of forming a power feeding layer in the manufacturing method of the wiring board which uses a graphite as a power feeding layer of the outermost layer. It is sectional drawing for demonstrating the 2nd process after the process of FIG. 24A. FIG. 24C is a cross-sectional view for explaining a fifth step after the step of FIG. 23B. It is sectional drawing for demonstrating the 6th process after the process of FIG. 25A. It is sectional drawing which shows the example which mounted the electronic component on the surface of the wiring board which concerns on Embodiment 1 of this invention. In other embodiment of this invention, it is sectional drawing which shows the wiring board which incorporates an electronic component. It is sectional drawing which shows the wiring board which concerns on Embodiment 2 of this invention. It is a figure which expands and shows a part of FIG. 28A. It is sectional drawing which shows the via conductor formed in the 1st surface side through-hole insulating layer and 2nd surface side through-hole insulating layer of the wiring board which concerns on Embodiment 2 of this invention. It is sectional drawing which shows the via conductor formed in the non-through-hole insulating layer of the wiring board which concerns on Embodiment 2 of this invention. In other embodiment of this invention, it is a figure which shows the wiring board in which the through hole which consists of a notch was formed. In other embodiment of this invention, it is a figure which shows the wiring board in which both the through hole which consists of a notch, and the through hole which consists of a hole were formed. In other embodiment of this invention, it is a figure for demonstrating an example of the formation method of the through hole which consists of notches. In other embodiment of this invention, it is a figure which shows the wiring board whose connection conductor of a core part is a through-hole conductor. In embodiment of this invention, it is a figure which shows the modification of the structure of the outermost conductor layer. In embodiment of this invention, it is a figure which shows the 1st modification of the planar shape of the connection conductor of a core part, the via conductor of a buildup part, and a through-hole conductor. In embodiment of this invention, it is a figure which shows the 2nd modification of the planar shape of the connection conductor of a core part, the via conductor of a buildup part, and a through-hole conductor. In embodiment of this invention, it is a figure which shows the 3rd modification of the planar shape of the connection conductor of a core part, the via conductor of a buildup part, and a through-hole conductor.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the figure, arrows Z1 and Z2 indicate the stacking direction of the wiring boards (or the thickness direction of the wiring boards) corresponding to the normal direction of the main surface (front and back surfaces) of the wiring boards. On the other hand, arrows X1 and X2 and Y1 and Y2 respectively indicate directions orthogonal to the stacking direction (or sides of each layer). The main surface of the wiring board is an XY plane. The side surface of the wiring board is an XZ plane or a YZ plane. In the stacking direction, the side closer to the core of the wiring board is referred to as a lower layer (or inner layer side), and the side far from the core is referred to as an upper layer (or outer layer side).

  The conductor layer is a layer composed of one or more conductor patterns. The conductor layer may include a conductor pattern that constitutes an electric circuit, for example, a wiring (including a ground), a pad, a land, or the like, or a planar conductor pattern that does not constitute an electric circuit.

  A via hole is, for example, an opening formed by drilling in a state where a conductor layer (mainly a lower-layer conductor layer) is present on one side of an insulating layer and reaching the conductor layer from the other side of the insulating layer. . A conductor formed in a via hole (hereinafter referred to as a via conductor) is formed with a conductor layer on one side of the insulating layer, so that the via conductor and the conductor layer on at least one side of the insulating layer are not continuous. Thus, an interface is formed between the two. On the other hand, the through hole means an opening formed so as to penetrate the insulating layer including the conductor layer when the conductor layer is provided on one side or both sides of the insulating layer. The conductor formed in the through hole (hereinafter referred to as the through hole conductor) is usually formed together with the conductor layers on both sides of the insulating layer by plating or the like, so that the through hole conductor and the conductor layers on both sides of the insulating layer are formed. Is at least partially continuous.

  The openings include notches and cuts in addition to holes and grooves. For example, the through hole includes not only a hole but also a notch (see FIGS. 30A, 30B, and 31 described later).

  Of the conductors (via conductors and through-hole conductors) formed in the opening, the conductor film formed on the wall surface (side and bottom) of the opening is called the conformal conductor, and the conductor filled in the opening is filled. It is called a conductor.

  Plating refers to depositing a conductor (for example, metal) in a layered manner on the surface of a metal, resin, or the like, and a deposited conductor layer (for example, a metal layer). In addition to wet plating such as electrolytic plating and electroless plating, plating includes dry plating such as PVD (Physical Vapor Deposition) and CVD (Chemical Vapor Deposition).

(Embodiment 1)
The wiring board 100 according to the present embodiment is a multilayer printed wiring board as shown in FIG. The wiring board 100 of this embodiment is a double-sided rigid wiring board. However, the wiring board which concerns on this invention is not limited to a rigid wiring board, For example, a flexible wiring board or a flex rigid wiring board may be sufficient. The wiring board according to the present invention is not limited to a double-sided wiring board, and may be a single-sided wiring board. In the wiring board 100, the dimensions and the number of layers of the conductor layer and the insulating layer can be arbitrarily changed.

  As shown in FIG. 1, the wiring board 100 includes a core insulating layer 10a, insulating layers 20a, 30a, 40a, 50a, 60a, 70a, 80a, 90a, and conductor layers 11a, 11b, 21, 31, 41, 51. , 61, 71, 81, 91, and the connection conductor 12 and the via conductors 22, 32, 42, 52, 62, 72, 82, 92. The core insulating layer 10a has a first surface F1 (Z1 side) and a second surface F2 (Z2 side) opposite thereto. The core insulating layer 10a, the connection conductor 12, and the conductor layers 11a and 11b correspond to a core portion. In addition, the insulating layers 20a to 90a and the like above the core portion correspond to the build-up portion.

  On the first surface F1 side of the core insulating layer 10a, five layers of conductor layers 11a, 21, 41, 61, 81 (first surface side conductor layers, respectively) and four layers of insulating layers 20a, 40a, 60a, 80a ( The first surface side interlayer insulating layers) are alternately stacked. As shown in FIG. 1, the insulating layers 20a, 40a, 60a, and 80a are formed between the conductor layers 11a, 21, 41, 61, and 81, respectively. However, the present invention is not limited to this, and the number of first surface side conductor layers is arbitrary.

  On the second surface F2 side of the core insulating layer 10a, five conductor layers 11b, 31, 51, 71, 91 (second surface side conductor layers, respectively) and four insulating layers 30a, 50a, 70a, 90a ( The second surface side interlayer insulating layers) are alternately stacked. As shown in FIG. 1, the insulating layers 30a, 50a, 70a, and 90a are formed between the conductor layers 11b, 31, 51, 71, and 91, respectively. However, the present invention is not limited to this, and the number of second surface side conductor layers is arbitrary.

  In the core insulating layer 10a, a connection hole 12a (via hole) penetrating the core insulating layer 10a is formed. The connection conductor 12 is a filled conductor, and is configured by filling the connection hole 12a with a conductor (see FIG. 4C described later). In the present embodiment, the connection conductor 12 is a via conductor. Since the via conductor can be formed more easily than the through-hole conductor, such a structure is advantageous for cost reduction and the like. However, the present invention is not limited to this, and the connection conductor 12 may be a through-hole conductor (see, for example, FIG. 32 described later).

  The core insulating layer 10a is made of, for example, an epoxy resin. The epoxy resin preferably contains a reinforcing material such as glass fiber (for example, glass cloth or glass nonwoven fabric) or aramid fiber (for example, aramid nonwoven fabric) by, for example, resin impregnation treatment. The reinforcing material is a material having a smaller coefficient of thermal expansion than the main material (in the present embodiment, epoxy resin). However, it is not limited to this, The material of the core insulating layer 10a is arbitrary. For example, instead of an epoxy resin, a polyester resin, a bismaleimide triazine resin (BT resin), an imide resin (polyimide), a phenol resin, an allylated phenylene ether resin (A-PPE resin), or the like can be used. Further, the core insulating layer 10a may not include a reinforcing material.

  The shape of the connection conductor 12 is, for example, a tapered cylinder (conical frustum) tapered so as to be reduced in diameter from the first surface F1 to the second surface F2 of the core insulating layer 10a. -Y plane) is, for example, a perfect circle. However, it is not limited to this, and the shape of the connection conductor 12 is arbitrary (for example, refer to FIGS. 34A to 34C described later).

  Via conductors 22, 32, 42, 52, 62, 72, 82, and 92 are formed in the insulating layers 20a, 30a, 40a, 50a, 60a, 70a, 80a, and 90a, respectively. Each of the via conductors 22 and the like is a filled conductor, and is configured by filling the via holes 22a, 32a, 42a, 52a, 62a, 72a, 82a, and 92a with a conductor (see FIGS. 4A and 4B described later). The shape of the via conductors 22, 42, 62, 82 is, for example, a tapered cylinder (conical frustum) that is tapered so as to be reduced in diameter toward the core insulating layer 10a, and the planar shape of the via conductors 22, 42, 62, 82. (XY plane) is, for example, a perfect circle. The via conductors 32, 52, 72, and 92 are, for example, tapered cylinders (conical frustums) tapered so as to be reduced in diameter toward the core insulating layer 10 a, and the via conductors 32, 52, 72, and 92 are The planar shape (XY plane) is, for example, a perfect circle. However, the present invention is not limited to this, and the shape of the via conductor 22 and the like is arbitrary (for example, see FIGS. 34A to 34C described later).

  Each of the insulating layers 20a, 30a, 40a, 50a, 60a, 70a, 80a, and 90a is formed by impregnating a reinforcing material into an epoxy resin, for example. As the reinforcing material, for example, an inorganic material such as glass fiber or aramid fiber can be used. However, it is not limited to this, and the material of each interlayer insulating layer is arbitrary. For example, instead of an epoxy resin, a polyester resin, a bismaleimide triazine resin (BT resin), an imide resin (polyimide), a phenol resin, an allylated phenylene ether resin (A-PPE resin), or the like can be used. In addition, each interlayer insulating layer may not include a reinforcing material.

  The wiring board 100 of the present embodiment includes a connection conductor 12 of a core part (core insulating layer 10a), and a via conductor 22 of a build-up part (insulating layers 20a, 30a, 40a, 50a, 60a, 70a, 80a, 90a), 32, 42, 52, 62, 72, 82, and 92 have a filled stack S configured by being stacked on the same axis (Z axis). However, it is not essential that the connection conductor 12 and the via conductor 22 are stacked on the same axis (Z axis).

  In the filled stack S, adjacent filled conductors are brought into close contact (contact) and conducted to each other. The filled stack S electrically connects the conductor layers on both sides of the wiring board 100, that is, the outermost conductor layers 81 and 91 to each other.

  The filled stack S of this embodiment has a so-called full stack structure in which filled conductors of all layers are stacked. For this reason, it becomes easy to secure the wiring space, and the degree of freedom in designing the wiring pattern is increased. Further, since the wiring in the X direction or the Y direction can be omitted, the wiring length can be shortened.

  In the present embodiment, one filled stack S is disposed at the center of the wiring board 100 as shown in FIG. The arrangement and number of filled stacks S are arbitrary. For example, there may be a plurality of filled stacks S.

  In the wiring board 100 of the present embodiment, as shown in FIG. 1, a through hole 102 a penetrating all layers of the wiring board 100 is formed. The through hole 102a penetrates the wiring board 100 in the Z direction (stacking direction). In the present embodiment, one end of the through-hole conductor 102 is connected to the outermost conductor layer 81 (specifically, a land 81a included in the conductor layer 81), and the other end of the through-hole conductor 102 is the outermost conductor layer. 91 (specifically, a land 91a included in the conductor layer 91).

  The shape of the through hole 102a is, for example, a cylinder, and the opening shape of the through hole 102a is, for example, an ellipse as shown in FIG. It is considered that the strength of a wide region in the XY plane can be effectively improved by the oval shape of the through hole 102a.

  The through hole 102a is disposed on the peripheral portion of the wiring board 100, for example, as shown in FIG. However, the number, opening shape, arrangement, etc. of the through holes 102a are arbitrary.

  FIG. 3 is an enlarged view of a part (near the through hole) of FIG.

  As shown in FIG. 3, in the present embodiment, the through-hole conductor 102 is formed on the wall surface F10 of the through-hole 102a. The through-hole conductor 102 is made of a conformal conductor. Unlike the filled conductor in which the conductor is filled in the through hole 102a, the conformal conductor has a conductor only on the wall surface F10 of the through hole 102a, so that a cavity is formed in the through hole 102a and the distortion of the wiring board 100 is reduced. It becomes easy to be done. However, the present invention is not limited to this, and a filled conductor may be used instead of the conformal conductor.

  In the present embodiment, the through-hole conductor 102 electrically connects the outermost conductor layer 81 (first surface side conductor layer) and the outermost layer conductor layer 91 (second surface side conductor layer). Further, on the wall surface F10 of the through hole 102a, the inner conductor layer 11a (first surface side conductor layer), the inner layer conductor layer 11b (second surface side conductor layer) and the like and the through hole conductor 102 are in contact with each other. Are electrically connected. However, it is not essential that the inner conductor layer and the through-hole conductor 102 are in contact with each other on the wall surface F10 of the through-hole 102a. The through-hole conductor 102 may be electrically connected to the ground line or the like of the wiring board 100, or may be electrically isolated from all other conductors.

  The outermost conductor layer 81 (first surface side conductor layer) on the first surface F1 side of the core insulating layer 10a is, for example, a copper foil 201a and, for example, copper on an insulating layer 80a (first surface side interlayer insulating layer). The electroless plating film 202a and, for example, copper electrolytic plating 203a are laminated in this order. That is, the conductor layer 81 includes a power feeding layer made of the copper foil 201a and the electroless plating film 202a, and an electrolytic plating 203a formed on the power feeding layer.

  The through-hole conductor 102 is configured, for example, by laminating, for example, a copper electroless plating film 202b and, for example, a copper electrolytic plating 203b in this order on the wall surface F10 of the through-hole 102a. That is, the through-hole conductor 102 includes a power feeding layer made of the electroless plating film 202b and an electrolytic plating 203b formed on the power feeding layer.

  The outermost conductor layer 91 (second surface side conductor layer) on the second surface F2 side of the core insulating layer 10a is, for example, on the insulating layer 90a (second surface side interlayer insulating layer) and a copper foil 201c, for example, copper The electroless plating film 202c and, for example, copper electrolytic plating 203c are laminated in this order. That is, the conductor layer 91 includes a power feeding layer composed of the copper foil 201c and the electroless plating film 202c, and an electrolytic plating 203c formed on the power feeding layer.

  The through hole 102a is formed so as to penetrate the insulating layer including the conductor layers (for example, copper foil) on both sides of the insulating layer (see FIGS. 19 to 22 described later). The through-hole conductor 102 is formed together with conductor layers 81 and 91 on both sides of the insulating layer by plating (see FIGS. 23A and 23B described later). For this reason, the through-hole conductor 102 and the conductor layers 81 and 91 on both sides of the insulating layer are at least partially continuous. Specifically, as shown in FIG. 3, in the through-hole conductor 102 and the conductor layers 81 and 91 at both ends thereof, the electroless plating film 202a, the electroless plating film 202b, and the electroless plating film 202c are The electroplating 203a, the electroplating 203b, and the electroplating 203c are integrally formed with each other.

  For example, as shown in FIG. 4A, the outermost via conductors 82 and 92 are configured by filling, for example, copper electroless plating film 202d and, for example, copper electrolytic plating 203d, in via holes 82a and 92a. The Specifically, the electroless plating film 202d is formed on the inner surfaces (wall surface and bottom surface) of the via holes 82a and 92a, and the inner side thereof is filled with the electrolytic plating 203d. That is, each of the via conductors 82 and 92 includes a power feeding layer made of the electroless plating film 202d and an electrolytic plating 203d formed on the power feeding layer.

  As shown in FIG. 4B, for example, the inner conductor layers 21, 31, 41, 51, 61, and 71 are respectively formed on the insulating layers 20a, 30a, 40a, 50a, 60a, and 70a with a copper foil 211a. Electrolytic plating 212a is laminated in this order. That is, each of the conductor layers 21, 31, 41, 51, 61, 71 includes a power feeding layer made of the copper foil 211a and an electrolytic plating 212a formed on the power feeding layer.

  As shown in FIG. 4B, for example, the inner via conductors 22, 32, 42, 52, 62, 72 are formed in the via holes 22a, 32a, 42a, 52a, 62a, 72a. The plating 212b is filled. Specifically, the graphite film 210 is formed on the inner surfaces (specifically, wall surfaces) of the via holes 22a, 32a, 42a, 52a, 62a, 72a, and the inner side thereof is filled with the electrolytic plating 212b. That is, each of the via conductors 22, 32, 42, 52, 62, 72 includes a power feeding layer made of the graphite film 210 and an electrolytic plating 212 b formed on the power feeding layer.

  For example, as shown in FIG. 4C, each of the conductor layers 11a and 11b in the core portion is formed by laminating copper foils 221a and 231a and, for example, copper electrolytic platings 222a and 232a in this order on the core insulating layer 10a. Composed. That is, each of the conductor layers 11a and 11b includes a power feeding layer made of copper foils 221a and 231a and electrolytic plating 222a and 232a formed on the power feeding layer.

  For example, as shown in FIG. 4C, the connecting conductor 12 in the core portion is configured by filling the connecting hole 12a with a graphite film 220 and, for example, copper electrolytic plating 222b. Specifically, the graphite film 220 is formed on the inner surface (specifically, the wall surface) of the connection hole 12a, and the inner side thereof is filled with the electrolytic plating 222b. That is, the connection conductor 12 includes a power feeding layer made of the graphite film 220 and an electrolytic plating 222b formed on the power feeding layer.

  Each of the connection hole 12a and the via holes 22a, 32a, 42a, 52a, 62a, 72a, 82a, and 92a is formed by drilling with a conductor layer on one side of the insulating layer, and from the other side of the insulating layer. The conductor layer is reached (see FIGS. 5B, 16B, and 20 described later). Since the connection conductor 12 and the via conductors 22, 32, 42, 52, 62, 72, 82, and 92 are each formed with a conductor layer on one side of the insulating layer, the via conductor and one side of the insulating layer are formed. The conductor layer is discontinuous, and an interface is formed between the two. Specifically, for example, as shown in FIG. 4A, in the via conductors 82 and 92 and the upper conductor layers 81 and 91, the electroless plating film 202a and the electroless plating film 202d are integrated with each other. In addition, the electrolytic plating 203a and the electrolytic plating 203d are integrally formed with each other. However, the via conductors 82 and 92 and the lower conductor layers 61 and 71 are discontinuous, and an interface is formed between them (see FIGS. 1 and 4A). For example, as shown in FIG. 4B, in the via conductors 22, 32, 42, 52, 62, 72 and the conductor layers 21, 31, 41, 51, 61, 71 on the upper layer side, The plating 212b is integrally formed with each other. However, the via conductors 22, 32, 42, 52, 62, 72 and the conductor layers 11 a, 11 b, 21, 31, 41, 51 on the lower side are discontinuous, and an interface is formed between them. (See FIGS. 1 and 4B). For example, as shown in FIG. 4C, in the connection conductor 12 and the conductor layer 11a on one side thereof, the electrolytic plating 222a and the electrolytic plating 222b are integrally formed with each other. However, the connection conductor 12 and the conductor layer 11b on the other side are discontinuous, and an interface is formed between them (see FIGS. 1 and 4C).

  In this embodiment, each of the insulating layers 20a, 40a, 60a, and 80a (first surface side interlayer insulating layer) and the insulating layers 30a, 50a, 70a, and 90a (respectively second surface side interlayer insulating layer) are provided with a power feeding layer. Via conductors 22, 32, 42, 52, 62, 72, 82, 92 including (electroless plating film 202 d, graphite film 210) and electrolytic plating 203 d, 212 b formed on the power feeding layer are formed. (See FIGS. 4A and 4B). In each of the insulating layers 20a, 30a, 40a, 50a, 60a, 70a, 80a, and 90a, the power supply layer (electroless plating film 202d) of the via conductors 82 and 92 in the outermost layer is made of electroless plating. The power feeding layer (graphite film 210) of the via conductors 22, 32, 42, 52, 62, 72 in the other layers is made of graphite.

  In the present embodiment, a hole (connection hole 12a) penetrating the core insulating layer 10a is formed in the core insulating layer 10a. Further, the wiring board 100 of the present embodiment has a conductor layer 11a (first surface side conductor layer) formed on the first surface F1 of the core insulating layer 10a and a second core insulating layer on the wall surface of the connection hole 12a. It has the connection conductor 12 which electrically connects the conductor layer 11b (2nd surface side conductor layer) formed on the surface F2 mutually. The connection conductor 12 includes a power supply layer (graphite film 220) made of graphite and an electrolytic plating 222b formed on the power supply layer (see FIG. 4C).

  Thereby, it becomes possible to improve the reliability of electrical connection (particularly, interlayer connection) in the build-up portion of the wiring board 100 of the present embodiment (for details, refer to the description of the manufacturing method described later).

  Thereby, it becomes possible to improve the reliability of the electrical connection (particularly, the electrical connection between both surfaces of the core insulating layer 10a) in the core portion of the wiring board 100 of the present embodiment (more specifically, a manufacturing method described later) See description).

  In the present embodiment, all conductor patterns (conductor patterns of each conductor layer) included in the wiring board 100 are made of a single metal material (for example, copper). However, the present invention is not limited to this, and each conductor pattern may be formed of a different conductor material (for example, distinguished by function).

  In the present embodiment, the number of conductor layers (first surface side conductor layers) formed on the first surface F1 side of the core insulating layer 10a and the conductor layers formed on the second surface F2 side of the core insulating layer 10a ( The number of layers of the second surface side conductor layer) is 5 or more. In the wiring board 100 of the present embodiment, the reliability of electrical connection (particularly, interlayer connection) in the build-up portion is improved by the above-described structure. Therefore, such a multilayer wiring board can be manufactured with a high yield. .

  Hereinafter, a method for manufacturing the wiring board 100 according to the present embodiment will be described.

  First, as shown in FIG. 5A, for example, a laminate 1000 (double-sided copper-clad laminate) is prepared as a starting material. The laminated plate 1000 includes a core insulating layer 10a and metal foils 1001 and 1002 (for example, copper foils, respectively). A metal foil 1001 is formed on the first surface F1 of the core insulating layer 10a, and a metal foil 1002 is formed on the second surface F2 of the core insulating layer 10a. The material of the core insulating layer 10a is, for example, an epoxy resin containing a reinforcing material. Each of the metal foils 1001 and 1002 may be attached with a predetermined thickness (thin state) from the beginning, or after a relatively thick metal foil is attached to the insulating layer, the metal foil is thinned by etching or the like. The thickness may be adjusted to a predetermined thickness.

  Subsequently, the surface (for example, the entire surface) of the metal foils 1001 and 1002 is blackened by, for example, a black oxidation method. Thereby, it is considered that the absorbability of the laser is increased and the processing efficiency of the laser process can be improved.

Subsequently, as shown in FIG. 5B, the connection holes 12a are formed in the laminated plate 1000 by, for example, a CO ₂ laser. The connection hole 12a penetrates the metal foil 1001 and the core insulating layer 10a, but does not penetrate to the metal foil 1002. Thereby, the connection hole 12a from the first surface F1 of the core insulating layer 10a to the metal foil 1002 is formed. Then, desmear or soft etch is performed as necessary.

  Subsequently, as shown in FIG. 5C, a power feeding layer 1003 made of graphite is formed in the connection hole 12a, and electrolytic plating is performed using the metal foils 1001, 1002 and the power feeding layer 1003 as shown in FIG. 5D. Thus, electrolytic plating 1004 and 1005 are formed. Hereinafter, the process of forming these electric power feeding layer 1003 and electrolytic plating 1004 and 1005 is demonstrated in detail.

  In the present embodiment, as shown in FIG. 5C, the power feeding layer 1003 is selectively formed only on the wall surface of the connection hole 12a.

  Specifically, prior to the formation of the power feeding layer 1003, conditioning is performed on the surface of the laminated plate 1000 in which the connection holes 12a are formed (particularly, the wall surface F21 of the connection holes 12a shown in FIG. 6). In a preferred example of conditioning, for example, the laminate 1000 is immersed in a conditioner solution for a predetermined time and then washed with deionized water.

  Subsequently, as shown in FIG. 6, the conditioned laminated plate 1000 is coated with a graphite film 1003a. In a preferred example of the coating, the laminated plate 1000 is immersed in a graphite dispersion for a predetermined time, and colloidal graphite (graphite film 1003a) is formed on the wall surface F21, the bottom surface F22 of the connection hole 12a of the laminated plate 1000, and the metal foil 1001. It adheres to the upper surface F23. Thereafter, the laminated plate 1000 is immersed in a sulfuric acid solution, for example, to fix the graphite film 1003a. Thereby, the graphite film 1003a is integrally formed on the wall surface F21 of the connection hole 12a, the bottom surface F22 of the connection hole 12a (on the metal foil 1002), and the upper surface F23 of the metal foil 1001 (on the metal foil 1001).

  Subsequently, a graphite film 1003a on the metal foils 1001 and 1002 is formed together with the metal foils 1001 and 1002 by etching (soft etching) using an etchant (for example, cupric chloride or ferric chloride) of the metal foils 1001 and 1002. Remove. The etchant enters under the graphite film 1003a, and removes the graphite film 1003a on the metal foils 1001 and 1002 under the graphite film 1003a. It is considered that the etchant enters under the graphite film 1003a through the gap between the graphite molecules. As a result, as shown in FIGS. 7 and 8, the graphite film 1003a (power feeding layer 1003) remains only on the wall surface F21 of the connection hole 12a. The core insulating layer 10a made of resin and the power feeding layer 1003 made of graphite have high adhesion (connection strength). In this embodiment, the surfaces of the metal foils 1001 and 1002 are etched in the range of about 0.2 μm to about 3.0 μm.

  When the power feeding layer 1003 is formed thick (for example, about 0.3 μm or more), the conditioning, the coating of the graphite film 1003a (formation of the graphite film 1003a), and the metal foils 1001 and 1002 are not formed once. It is preferable that the soft etching (removal of the graphite film 1003a) is repeated twice or more (formation and removal of the graphite film 1003a are performed twice or more alternately) to form in stages. By doing so, a high-quality (for example, low resistance) graphite film can be obtained.

  In FIG. 8, the thickness D1 (minimum thickness) of the power feeding layer 1003 is preferably in the range of 0.3 to 0.6 μm. If the thickness D1 of the power feeding layer 1003 is in such a range, the manufacturing efficiency is improved by reducing the electric resistance during electrolytic plating.

  Subsequently, electrolytic plating of copper is formed on the metal foils 1001 and 1002 and in the connection holes 12a by copper panel plating.

  Specifically, as shown in FIG. 9, a laminated plate 1000 on which a power feeding layer 1003 is formed and a first electrode 2001 are immersed in a solution 2002 in a container 2002a, and laminated at one end of a power source 2003 (pulse power source). The plate 1000 (specifically, each of the metal foils 1001 and 1002 and the power feeding layer 1003) is connected, and the first electrode 2001 is connected to the other end.

  The first electrode 2001 is made of, for example, a metal to be plated (hereinafter referred to as a plating metal) and serves as an elution electrode. However, the present invention is not limited to this, and the first electrode 2001 may be an insoluble electrode. In the present embodiment, the first electrode 2001 is made of copper.

  In the laminated plate 1000, the metal foils 1001 and 1002 and the power feeding layer 1003 are each a second electrode that makes a pair with the first electrode 2001. The second electrode corresponds to a material to be plated.

The solution 2002 contains plating metal ions. In the present embodiment, the solution 2002 is a copper sulfate solution, the plating metal is copper, and the ions of the plating metal are Cu ²⁺ . Moreover, additives, such as an inhibitor or a promoter, are added to the solution 2002 as necessary. In the solution 2002 of the present embodiment, a leveler is added as an inhibitor and a brightener is added as an accelerator.

  As shown in FIG. 9, the power supply 2003 performs pulse control on the voltage waveform between the first electrode 2001 and the second electrode (the metal foils 1001 and 1002, and the power feeding layer 1003), and switches the polarity at a constant cycle. The power supply 2003 is composed of a rectifier or the like. In the present embodiment, the voltage waveform between the first electrode 2001 and the second electrode is a rectangular wave as shown in FIG. However, the voltage waveform is not limited to this, and the voltage waveform is arbitrary.

At time T1, the following precipitation reaction R1 proceeds at the second electrode, and at time T2, the following decomposition reaction R2 proceeds at the second electrode.
(Precipitation reaction R1) Cu ²⁺ + 2e ⁻ → Cu
(Decomposition reaction R2) Cu → Cu ²⁺ + 2e ⁻
At time T1, a deposition voltage V1 (> 0V) is applied between the first electrode 2001 and the second electrode, the deposition reaction R1 proceeds, and a plating metal (for example, copper) is deposited on the second electrode.

  At time T2, a separation voltage V2 (<0V) is applied between the first electrode 2001 and the second electrode, the decomposition reaction R2 proceeds, and the plating metal (for example, copper) is separated (detached) from the second electrode. .

  In the present embodiment, the polarities of the first electrode 2001 and the second electrode are switched at a constant period T3 (= time T1 + time T2).

  In the present embodiment, as shown in FIG. 10, while the deposition voltage V1 and the separation voltage V2 are alternately applied between the first electrode 2001 (FIG. 9) and the second electrode, the second electrode (metal foil 1001). , 1002 and the power feeding layer 1003), the plating metal 1004a is deposited. Thereby, as shown in FIG. 11, the connection hole 12a (bottomed hole) is filled with the plating metal 1004a. Further, at the same time when the plating metal 1004a is filled in the connection hole 12a, the plating metal 1004a is deposited on the metal foils 1001 and 1002, respectively. As a result, as shown in FIG. 5D, the connection hole 12a is filled with the power feeding layer 1003 and the electrolytic plating 1004, and the connection conductor 12 is formed in the core insulating layer 10a. Also, as shown in FIG. 5D, electrolytic plating 1004 and 1005 are formed on the metal foils 1001 and 1002, respectively. In the connection conductor 12, the power feeding layer 1003 corresponds to the graphite film 220 shown in FIG. 4C, and the electrolytic plating 1004 corresponds to the electrolytic plating 222b shown in FIG. 4C. The bottom surface of the connection conductor 12 is connected to the metal foil 1002. Note that the electrolytic plating 1005 may be formed simultaneously with the electrolytic plating 1004 or separately.

  As shown in FIG. 11, the wall surface F21 and the bottom surface F22 of the connection hole 12a serve as the low potential portion R11, and the top surface F23 (surface layer and shoulder) of the metal foil 1001 serves as the high potential portion R12. In the present embodiment, since the plating metal 1004a is deposited while alternately applying the deposition voltage V1 and the separation voltage V2 between the first electrode 2001 (FIG. 9) and the second electrode, a thick plating is applied to the low potential portion R11. Thus, it is possible to form a thin plating on the high potential portion R12. Specifically, during the decomposition reaction, the higher the deposition portion (high potential portion R12), the faster the decomposition, so as the deposition and decomposition are repeated, the difference in the area around the plating becomes smaller, and proper plating is achieved even inside the via. (Precipitation of plating metal 1004a) becomes possible.

  FIGS. 12 and 13 show the voltage between the first electrode and the second electrode (FIG. 12) for an example in which electrolytic plating is performed by a DC power source on a wiring board having a power feeding layer 1003b made of copper electroless plating (chemical copper). 12) and a state in which the connection hole 12a (bottomed hole) is filled with the plating metal 1004a by electrolytic plating (FIG. 13).

  In this example, as shown in FIG. 12, a constant voltage V0 is applied between the anode (anode) and the power feeding layer 1003b (cathode: cathode), and as shown in FIG. The plating metal 1004a (copper) is deposited on the substrate. For this reason, thin plating (copper) is formed in the low potential portion R11, and thick plating (copper) is formed in the high potential portion R12.

  In the present embodiment, the power feeding layer 1003 is made of a material that is less soluble in the solution 2002 than the plated metal 1004a. The ease of melting can be compared, for example, with a standard electrode potential. Specifically, the larger the standard electrode potential is, the more difficult it is to dissolve. In the present embodiment, the power feeding layer 1003 is made of graphite, and the plated metal 1004a is made of copper. The standard electrode potential of graphite is larger than the standard electrode potential of copper.

  The separation voltage V2 (FIG. 10) in the present embodiment is set in a range where the plating metal 1004a is dissolved in the solution 2002 and the power feeding layer 1003 is not dissolved in the solution 2002. Thereby, the decomposition reaction R2 proceeds with almost no melting of the power feeding layer 1003.

  When the power feeding layer 1003 is melted and thinned, there is a possibility that the resistance value becomes high and the rate of electrolytic plating becomes slow, or the plating metal 1004a is not uniformly deposited. Further, when the power feeding layer 1003 is completely melted and disappears, it is impossible to perform electroplating. For this reason, when the power feeding layer 1003 is easily melted, it is difficult to increase the separation voltage V2 or lengthen the separation time (time T2) of the plated metal 1004a. In this regard, in the present embodiment, the power feeding layer 1003 is made of a material that is less soluble in the solution 2002 than the plated metal 1004a. As a result, the separation voltage V2 can be increased, or the detachment time (time T2) of the plated metal 1004a can be increased. As a result, a filled conductor can be formed with high productivity. Further, by increasing the separation voltage V2, it is possible to suppress seam generation between the metal foil 1002 and the connection conductor 12. For this reason, even when electrolytic plating is performed on a small diameter via hole, it becomes easy to be seamless.

  FIG. 14 compares the characteristics when chemical copper is used as a power supply layer for electrolytic plating and the characteristics when each conductive material having a higher standard electrode potential than copper is used as the power supply layer for electrolytic plating. Show.

  As shown in FIG. 14, the resistance value of chemical copper having a thickness of 50 nm is 0.008Ω, the resistance value of graphite having a thickness of 300 nm is 0.08Ω, and the resistance value of carbon black having a thickness of 50 nm is 5Ω. The resistance value of palladium having a thickness of about 1 nm is 3Ω, and the resistance value of a conductive polymer having a thickness of about 1 nm is 50Ω.

  In the present embodiment, the feed layer of the via conductor 82 formed in the insulating layer 80a (first surface side interlayer insulating layer) under the conductor layer 81 (first surface side conductive layer to which one end of the through-hole conductor 102 is connected). (Electroless plated film 202d) and via formed in insulating layer 90a (second surface side interlayer insulating layer) under conductor layer 91 (second surface side conductor layer to which the other end of through-hole conductor 102 is connected) The material (chemical copper) that constitutes the power supply layer (electroless plating film 202d) of the conductor 92 is the power supply layer of the via conductors 22, 32, 42, 52, 62, 72 formed in other build-up portions ( The resistance value is lower than that of the material (graphite) constituting the graphite film 210).

  In the present embodiment, as shown in FIGS. 5C and 7, the power feeding layer 1003 is selectively formed only on the wall surface F <b> 21 of the connection hole 12 a. For this reason, it is possible to deposit the plating metal 1004a directly on the metal foil 1002 without the power feeding layer 1003 interposed. Thereby, since the coupling | bonding of the metal foil 1002 and the plating metal 1004a turns into a coupling | bonding of metals, joining strength improves.

  However, if the material of the power feeding layer 1003 remains between the metal foil 1002 and the connection conductor 12, a seam is likely to occur. In this regard, chemical copper, which is the same metal as the material (copper) constituting the metal foil 1002, is substantially indistinguishable from (or can be identified with) the metal foil 1002, so that it does not remain on the metal foil 1002. Conceivable. In addition, graphite that is a non-metal is easily removed completely, and thus hardly remains on the metal foil 1002.

  In the present embodiment, the power feeding layer 1003 is made of graphite. Since graphite hardly remains on the metal foil 1002, it is suitable for suppressing seam generation between the metal foil 1002 and the connection conductor 12. Further, as shown in FIG. 14, graphite has a lower resistance than carbon black, palladium, and a conductive polymer. For this reason, the power feeding layer 1003 made of graphite is suitable as a second electrode (material to be plated) for electrolytic plating.

  Further, when the power feeding layer 1003 is formed of chemical copper, in order to obtain a high quality electroless copper plating film, formalin or the like is required as a reducing agent, and palladium (Pb) that is a rare metal is required as a catalyst. Become. In this regard, in this embodiment, since the power feeding layer 1003 is formed of graphite, a good quality power feeding layer can be obtained without using formalin and palladium. As a result, it is possible to reduce the environmental load (for example, reduce the amount of waste liquid) or reduce material costs.

  In the present embodiment, the metal foils 1001 and 1002 are each made of the same metal (copper) as the plating metal 1004a. Thereby, mismatching of the plating interface is suppressed, and seam generation between the metal foils 1001 and 1002 and the connection conductor 12 is suppressed. In the present embodiment, the power feeding layer 1003 is made of a conductive material different from any of the metal foils 1001 and 1002. Specifically, the environmental impact or the material cost is reduced by forming the power feeding layer 1003 from graphite.

  Subsequently, the conductor layers (metal foils 1001 and 1002 and electrolytic plating 1004 and 1005) on the core insulating layer 10a shown in FIG. 5D are patterned by a lithography technique.

  Specifically, as illustrated in FIG. 15A, an etching resist 1006 having an opening 1006a is formed on the electrolytic plating 1004, and an etching resist 1007 having an opening 1007a is formed on the electrolytic plating 1005. The openings 1006a and 1007a are disposed at portions where the conductor layers (metal foils 1001 and 1002 and electrolytic plating 1004 and 1005) are to be etched, respectively.

  Subsequently, as shown in FIG. 15B, the conductor layers (metal foils 1001 and 1002 and electrolytic plating 1004 and 1005) on the core insulating layer 10a are etched by, for example, cupric chloride or ferric chloride. Of the conductor layer on the core insulating layer 10a, the portions covered with the etching resists 1006 and 1007 remain without being etched, and the portions exposed from the openings 1006a and 1007a are removed by etching. Thereby, the conductor layer 11a composed of the metal foil 1001 (lower layer) and the electrolytic plating 1004 (upper layer) is formed on the first surface F1 of the core insulating layer 10a, and on the second surface F2 of the core insulating layer 10a. A conductor layer 11b composed of a metal foil 1002 (lower layer) and electrolytic plating 1005 (upper layer) is formed. The connection conductor 12 electrically connects the conductor layer 11a and the conductor layer 11b to each other.

  In the conductor layer 11a, the metal foil 1001 corresponds to the copper foil 221a shown in FIG. 4C, and the electrolytic plating 1004 corresponds to the electrolytic plating 222a shown in FIG. 4C. In the conductor layer 11b, the metal foil 1002 corresponds to the copper foil 231a shown in FIG. 4C, and the electrolytic plating 1005 corresponds to the electrolytic plating 232a shown in FIG. 4C.

  The minimum thickness of the conductor layer 11a is preferably in the range of 10 to 30 μm. In the present embodiment, by applying the above-described deposition voltage and separation voltage, the connection hole 12a (bottomed hole) is filled with the plating metal 1004a, and at the same time, the plating metal 1004a is deposited on the metal foil 1001 to provide core insulation. A conductor layer 11a having a minimum thickness in the range of 10 to 30 μm is formed on the layer 10a. If the minimum thickness of the conductor layer 11a is smaller than the lower limit (10 μm), the recess of the via cannot be eliminated and the flatness is easily lost.

  Subsequently, for example, as shown in FIG. 16A, the insulating layer 20a and the metal foil 1011 (for example, copper foil) are laminated in this order on the first surface F1 and the conductor layer 11a of the core insulating layer 10a, and the core insulation is performed. The insulating layer 30a and the metal foil 1012 (for example, copper foil) are laminated in this order on the second surface F2 of the layer 10a and the conductor layer 11b. At this stage, the insulating layers 20a and 30a are, for example, prepregs (semi-cured adhesive sheets). However, RCF (Resin Coated copper Foil) or the like can be used instead of the prepreg. Each of the metal foils 1011 and 1012 may be attached with a predetermined thickness (thin state) from the beginning, or after a relatively thick metal foil is attached to the insulating layer, the metal foil is thinned by etching or the like. The thickness may be adjusted to a predetermined thickness.

  Subsequently, the laminate is heated and pressed in the Z direction. That is, pressing and heat treatment are performed simultaneously. The prepreg (insulating layers 20a and 30a) is cured by pressing and heating, and the members adhere to each other. As a result, the laminate is integrated. Note that the pressing and heat treatment may be performed in a plurality of times. Moreover, although heat processing and a press may be performed separately, it is more efficient to perform it simultaneously. You may perform the heat processing for integration separately after a heat press.

Subsequently, as shown in FIG. 16B, for example, via holes 22a are formed in the insulating layer 20a, and via holes 32a are formed in the insulating layer 30a, for example, by a CO ₂ laser. The via holes 22a and 32a for forming the filled stack S are formed on the same axis (Z axis) as the connection conductor 12 constituting the filled stack S. In addition, it is preferable to perform a blackening process before drilling (laser irradiation) as needed. In addition, after drilling, desmear or soft etch is performed as necessary.

  Subsequently, as shown in FIG. 16C, in the same manner as the method of forming the connection conductor 12 and the conductor layers 11a and 11b (see FIGS. 6 to 11) described above, power supply made of graphite is provided in the via holes 22a and 32a, respectively. The layers 1013 and 1014 are formed, and electrolytic plating is performed using the power feeding layers 1013 and 1014, whereby the electrolytic plating 1015 and 1016 are formed. As a result, the via holes 22a and 32a are filled with the electrolytic plating 1015 and 1016, respectively. As a result, via conductors 22 and 32 are formed in the insulating layers 20a and 30a, respectively. The via conductors 22 and 32 constituting the filled stack S are stacked on the same axis (Z axis) as the other connection conductors 12 constituting the filled stack S. In the via conductors 22 and 32, the power supply layers 1013 and 1014 respectively correspond to the graphite film 210 shown in FIG. 4B, and the electrolytic plating 1015 and 1016 correspond to the electrolytic plating 212b shown in FIG. 4B.

  Subsequently, as shown in FIG. 16D, the conductive layers (metal foils 1011 and 1012 and electrolytic plating 1015 and 1016) on both sides are patterned in the same manner as the patterning of the conductive layers 11a and 11b (see FIGS. 15A and 15B), for example. To do. Thereby, the conductor layer 21 is formed on the insulating layer 20a, and the conductor layer 31 is formed on the insulating layer 30a. In the conductor layers 21 and 31, the metal foils 1011 and 1012 each correspond to the copper foil 211a shown in FIG. 4B, and the electroplating 1015 and 1016 each correspond to the electroplating 212a shown in FIG. 4B.

  Subsequently, in the same manner as the method of forming the via conductors 22 and 32 and the conductor layers 21 and 31 (see FIGS. 16A to 16D), as shown in FIG. 17, the insulating layers 40a and 50a and the via holes 42a and 52a are formed. The via conductors 42 and 52 and the conductor layers 41 and 51 are formed. The via conductors 42 and 52 constituting the filled stack S are stacked on the same axis (Z axis) as the other connection conductors 12 constituting the filled stack S.

  Subsequently, in the same manner as the method of forming the via conductors 22 and 32 and the conductor layers 21 and 31 (see FIGS. 16A to 16D), as shown in FIG. 18, the insulating layers 60a and 70a and the via holes 62a and 72a are formed. The via conductors 62 and 72 and the conductor layers 61 and 71 are formed. The via conductors 62 and 72 constituting the filled stack S are stacked on the same axis (Z axis) as the other connection conductors 12 constituting the filled stack S and the like.

  Subsequently, for example, as shown in FIG. 19, an insulating layer 80a and a metal foil 1021 (for example, copper foil) are laminated in this order on the insulating layer 60a and the conductor layer 61, and on the insulating layer 70a and the conductor layer 71. On top of this, an insulating layer 90a and a metal foil 1022 (for example, copper foil) are laminated in this order. At this stage, the insulating layers 80a and 90a are, for example, prepregs (semi-cured adhesive sheets). However, RCF (Resin Coated copper Foil) or the like can be used instead of the prepreg. Each of the metal foils 1021 and 1022 may be attached with a predetermined thickness (thin state) from the beginning, or after a relatively thick metal foil is attached to the insulating layer, the metal foil is thinned by etching or the like. The thickness may be adjusted to a predetermined thickness.

  Subsequently, the laminate is heated and pressed in the Z direction. That is, pressing and heat treatment are performed simultaneously. The prepreg (insulating layers 80a and 90a) is cured by pressing and heating, and the members adhere to each other. As a result, the laminate is integrated. Note that the pressing and heat treatment may be performed in a plurality of times. Moreover, although heat processing and a press may be performed separately, it is more efficient to perform it simultaneously. You may perform the heat processing for integration separately after a heat press.

Subsequently, as shown in FIG. 20, a via hole 82a that penetrates the insulating layer 80a, a via hole 92a that penetrates the insulating layer 90a, and a through hole 102a that penetrates all layers are formed by, for example, a CO ₂ laser. The via holes 82a and 92a for forming the filled stack S are formed on the same axis (Z axis) as the connection conductors 12 and the like constituting the filled stack S. In addition, it is preferable to perform a blackening process before drilling (laser irradiation) as needed. In addition, after drilling, desmear or soft etch is performed as necessary.

  In laser irradiation, for example, the entire surface of the irradiated object is irradiated with laser light in a state where a light-shielding mask is provided. However, the present invention is not limited to this, and the laser irradiation may be stopped in the non-irradiated portion without using the light shielding mask, and the laser beam may be irradiated only on the portion to be irradiated. Further, during the scanning of the laser beam, the via holes 82a and 92a and the through holes are increased by increasing the intensity (light quantity) of the laser beam applied to the site where the through holes 102a are formed rather than the site where the via holes 82a and 92a are formed. 102a can be formed by one scan. At this time, the laser intensity (light quantity) is preferably adjusted by pulse control. Specifically, for example, when changing the laser intensity, the number of shots (number of irradiations) is changed without changing the laser intensity per shot (one irradiation). That is, when a desired laser intensity cannot be obtained with one shot, the same irradiation position is irradiated with laser light again. According to such a control method, the time for changing the irradiation condition can be omitted, so that it is considered that the throughput is improved. However, the method is not limited to this, and the laser intensity adjustment method is arbitrary. For example, the irradiation conditions may be determined for each irradiation position, and the number of irradiations may be fixed (for example, one shot for one irradiation position). The through hole 102a can be formed by irradiating laser light only from one side of the wiring board or by simultaneously irradiating laser light from both sides of the wiring board. Furthermore, after forming a bottomed hole (non-through hole) by irradiating a laser beam from one side of the wiring board, a through hole 102a is formed by irradiating the laser beam from the other side and penetrating the bottom. May be. The via holes 82a and 92a may be formed by laser, and the through hole 102a may be formed by a drill separately from the via holes 82a and 92a.

  In the present embodiment, the inner conductor layer 11a (first surface side conductor layer), the inner conductor layer 11b (second surface side conductor layer), and the like are removed by forming the through hole 102a (laser, drill, or the like). As shown in FIG. 21, each of the cut conductor layers (specifically, the side surface F20) is exposed on the wall surface F10 of the through hole. The conductor layer 11a and the like to be scraped here are composed of a planar conductor pattern, for example, as shown in FIG. However, the present invention is not limited to this, and the linear conductor pattern may be removed by forming the through hole 102a. In the present embodiment, the inner conductor layer 11a exposed on the wall surface F10 of the through hole and the metal foils 1021 and 1022 are made of the same metal material (copper).

  Subsequently, as shown in FIG. 23A, for example, copper electroless plating film is formed on the metal foil 1021, the via hole 82a, the metal foil 1022, the via hole 92a, and the through hole 102a by, for example, copper panel plating. 1023 (feeding layer) is formed. The electroless plating is performed by, for example, a chemical plating method. As a plating solution for electroless plating, for example, a copper sulfate solution to which a reducing agent or the like is added can be used.

  Subsequently, for example, the electroless plating film 1023 is immersed in a plating solution, and electrolytic plating is performed using, for example, a DC power source (see FIG. 12). As shown in FIG. 23B, for example, copper electroplating is performed on the electroless plating film 1023. 1024 is formed. As a plating solution for electrolytic plating, for example, a copper sulfate solution, a copper pyrophosphate solution, a blue (cyanide) copper solution, or a copper borofluoride solution can be used. The method of electrolytic plating is not limited to electrolytic plating with a DC power source, and horizontal pulse plating or the like may be used, for example.

  Thus, the via holes 82a and 92a are filled with the electroless plating film 1023 and the electrolytic plating 1024, respectively, and the electroless plating film 1023 and the electrolytic plating 1024 are formed on the wall surface F10 of the through hole 102a. As a result, via conductors 82 and 92 and through-hole conductor 102 are formed. In the via conductors 82 and 92, the electroless plating film 1023 corresponds to the electroless plating film 202a shown in FIG. 4A, and the electrolytic plating 1024 corresponds to the electrolytic plating 203d shown in FIG. 4A. In the through-hole conductor 102, the electroless plating film 1023 corresponds to the electroless plating film 202b shown in FIG. 3, and the electrolytic plating 1024 corresponds to the electrolytic plating 203b shown in FIG.

  Each conductor layer (inner conductor layers 11a and 11b, etc.) exposed on the wall surface F10 of the through hole is in contact with and electrically connected to the through hole conductor 102 on the wall surface F10 of the through hole 102a.

  The via conductors 82 and 92 constituting the filled stack S are stacked on the same axis (Z axis) as the other connection conductors 12 constituting the filled stack S.

  The method for manufacturing a wiring board according to the present embodiment prepares a core insulating layer 10a having a first surface F1 and a second surface F2 on the opposite side, and is formed on the first surface F1 side of the core insulating layer 10a. A plurality of first surface side conductor layers (conductor layers 11a, 21, 41, 61, 81) and a first surface side interlayer insulating layer (insulating layers 20a, 40a) formed between the first surface side conductor layers. , 60a, 80a), a plurality of second surface side conductor layers (conductor layers 11b, 31, 51, 71, 91) formed on the second surface F2 side of the core insulating layer 10a, Forming a second surface side interlayer insulating layer (insulating layers 30a, 50a, 70a, 90a) formed between the two surface side conductor layers, and the first surface side interlayer insulating layer and the second surface side interlayer; Via conductor 2 including a power feeding layer and electrolytic plating formed on the power feeding layer on each of the insulating layers. Comprises, forming a 32,42,52,62,72,82,92. In the method for manufacturing a wiring board according to the present embodiment, in each of the first surface side interlayer insulating layer and the second surface side interlayer insulating layer, the power supply layers of the outermost via conductors 82 and 92 are electroless plated. The power supply layers of the via conductors 22, 32, 42, 52, 62, 72 in the other layers are made of graphite.

  For this reason, according to the method for manufacturing a wiring board according to the present embodiment, when the through-hole conductor 102 is formed on the wall surface F10 of the through-hole 102a penetrating the wiring board 100, it is easy to obtain a good quality through-hole conductor 102. .

  Specifically, when graphite is used as the power feeding layer in the outermost layer in the same manner as the inner layer, for example, as shown in FIG. 24A, a graphite film 1023a is formed on the wall surface F10 of the through hole 102a and the metal foils 1021, 1022. . Then, the graphite film 1023a (only the wall surface F10 of the through hole 102a is removed by removing the graphite film 1023a on the metal foils 1021 and 1022 by etching using, for example, an etchant (for example, copper etchant) of the metal foils 1021 and 1022. Leave the power feeding layer). However, at this time, for example, as shown in FIG. 24B, not only the graphite film 1023a on the metal foils 1021 and 1022, but also the graphite formed on the side surface F20 of the inner conductor layer flush with the wall surface F10 of the through hole 102a. There is a concern that the film 1023a is also etched, and the power supply layer formed on the wall surface F10 of the through hole 102a becomes discontinuous. When the through-hole conductor 102 is formed by such a discontinuous power feeding layer, the through-hole conductor 102 is likely to be discontinuous due to poor deposition of electrolytic plating. As the wiring board becomes multilayer, such electrolytic plating deposition defects are more likely to occur.

  In this regard, in the method of manufacturing the wiring board according to the present embodiment, the power supply layers of the via conductors 82 and 92 in the outermost layer are electroless in each of the first surface side interlayer insulating layer and the second surface side interlayer insulating layer. The power supply layers of the via conductors 22, 32, 42, 52, 62, 72 made of plating and other layers are made of graphite. For this reason, it becomes easy to obtain the through-hole conductor 102 without a break.

  In the present embodiment, plating on the through hole 102a and plating on the outermost via holes 82a and 92a are performed simultaneously. For this reason, it is thought that reduction of the number of processes and by extension, cost reduction can be achieved. However, it is not limited to this, and may be performed separately.

  Subsequently, the conductor layers (metal foils 1021, 1022, electroless plating film 1023, and electrolytic plating 1024) on the insulating layers 80a and 90a shown in FIG. 23B are patterned by lithography.

  Specifically, as shown in FIG. 25A, an etching resist 1031 having an opening 1031a is formed on a conductor layer on the insulating layer 80a, and etching having an opening 1032a is formed on the conductor layer on the insulating layer 90a. A resist 1032 is formed. Each of the openings 1031a and 1032a is disposed at a portion where the conductor layer is to be etched.

  Subsequently, as shown in FIG. 25B, each conductor layer is etched by, for example, cupric chloride or ferric chloride. Of the conductor layer, portions covered with the etching resists 1031 and 1032 remain without being etched, and portions exposed from the openings 1031a and 1032a are removed by etching. Thereby, the conductor layer 81 composed of the metal foil 1021 (lower layer), the electroless plating film 1023 (intermediate layer), and the electrolytic plating 1024 (upper layer) is formed on the insulating layer 80a, and on the insulating layer 90a, A conductor layer 91 composed of metal foil 1022 (lower layer), electroless plating film 1023 (intermediate layer), and electrolytic plating 1024 (upper layer) is formed. As a result, the wiring board 100 of this embodiment is completed. In the conductor layers 81 and 91, the metal foils 1021 and 1022 correspond to the copper foil 201a shown in FIG. 4A, the electroless plating film 1023 corresponds to the electroless plating film 202a shown in FIG. This corresponds to the electrolytic plating 203a shown in FIG. 4A.

  After that, for example, by forming external connection terminals in the outermost layer, the wiring board 100 can be connected to other wiring boards or electronic components can be mounted on the wiring board 100 through the external connection terminals. . Specifically, for example, as shown in FIG. 26, a solder resist 1033 having an opening 1033a and a solder resist 1034 having an opening 1034a are formed on the surface of the wiring board 100, and the openings 1033a and 1034a are respectively formed. For example, the electronic component 200 may be mounted using the solder 1033b and 1034b. Each of the solder resists 1033 and 1034 can be formed by, for example, screen printing, spray coating, roll coating, or lamination.

  In the example of FIG. 26, the electronic components 200 are mounted on both sides of the wiring board 100, but a plurality of electronic components 200 may be mounted only on one side of the wiring board 100. Moreover, the number of electronic components is arbitrary. For example, only one electronic component may be mounted on the wiring board 100.

  Further, for example, as shown in FIG. 27, an electronic component 200 may be built in the wiring board 100. In the example of FIG. 27, two electronic components 200 are incorporated, but the number of electronic components is arbitrary. For example, only one electronic component may be built in the wiring board 100. According to the wiring board 100 incorporating the electronic component, it is possible to enhance the functionality of the electronic device.

(Embodiment 2)
The second embodiment of the present invention will be described focusing on the differences from the first embodiment. Here, the same elements as those shown in FIG. 1 and the like are denoted by the same reference numerals, and the description of the already explained common parts, that is, the duplicated explanations, is omitted or simplified. .

  In the wiring board 100a of the present embodiment, as shown in FIG. 28A, the through-hole conductor 102 does not penetrate the entire wiring board 100a. That is, the wiring board 100a has the through-hole conductor 102 in the inner layer.

  Hereinafter, the first surface side conductor layer to which one end of the through hole conductor 102 is connected is referred to as a first surface side through hole conductor layer, and the second surface side conductor layer to which the other end of the through hole conductor 102 is connected, This is referred to as a second surface side through-hole conductor layer. The first surface side interlayer insulating layer below the first surface side through-hole conductor layer is referred to as a first surface side through-hole insulating layer, and the second surface side interlayer insulating layer below the second surface side through-hole conductor layer. This is referred to as a second surface side through-hole insulating layer. Of the first surface side interlayer insulating layer and the second surface side interlayer insulating layer, those other than the first surface side through hole insulating layer and the second surface side through hole insulating layer are referred to as non-through hole insulating layers. In the present embodiment, the conductor layer 21 corresponds to the first surface side through-hole conductor layer, the conductor layer 31 corresponds to the second surface side through-hole conductor layer, and the insulating layer 20a corresponds to the first surface side through-hole conductor layer. The insulating layer 30a corresponds to the second surface side through-hole insulating layer, and the insulating layers 40a, 50a, 60a, 70a, 80a, and 90a correspond to the non-through-hole insulating layers.

  FIG. 28B shows an enlarged part of FIG. 28A (near the through hole).

  As shown in FIG. 28B, in the present embodiment, the through-hole conductor 102 is formed on the wall surface F10 of the through-hole 102a. The through-hole conductor 102 is made of a conformal conductor. However, the present invention is not limited to this, and a filled conductor may be used instead of the conformal conductor.

  In the present embodiment, one end of the through-hole conductor 102 is connected to the inner conductor layer 21 (specifically, the land 21a included in the conductor layer 21), and the other end of the through-hole conductor 102 is connected to the inner conductor layer 31 ( Specifically, it is connected to a land 31a) included in the conductor layer 31. The through-hole conductor 102 electrically connects the conductor layer 21 (first surface side through-hole conductor layer) and the conductor layer 31 (second surface side through-hole conductor layer). In addition, in the wall surface F10 of the through hole 102a, the conductor layer 11a (first surface side conductor layer) positioned below the conductor layer 21 (first surface side through hole conductor layer) and the conductor layer 31 (second surface side) The conductor layer 11b (second surface side conductor layer) positioned below the through-hole conductor layer) and the through-hole conductor 102 are in contact with each other and are electrically connected. However, on the wall surface F10 of the through hole 102a, the conductor layer and the through hole conductor 102 located on the side of the through hole conductor 102 (lower than the first surface side through hole conductor layer or the second surface side through hole conductor layer) However, it is not essential that they are in contact with each other.

  The conductor layer 21 (first surface side through-hole conductor layer) is formed on the insulating layer 20a (first surface side through-hole insulating layer) with a copper foil 201a, an electroless plating film 202a of copper, for example, and an electrolysis of copper. The plating 203a is laminated in this order. That is, the conductor layer 21 includes a power feeding layer composed of the copper foil 201a and the electroless plating film 202a, and an electrolytic plating 203a formed on the power feeding layer.

  The through-hole conductor 102 is configured, for example, by laminating, for example, a copper electroless plating film 202b and, for example, a copper electrolytic plating 203b in this order on the wall surface F10 of the through-hole 102a. That is, the through-hole conductor 102 includes a power feeding layer made of the electroless plating film 202b and an electrolytic plating 203b formed on the power feeding layer.

  The conductor layer 31 (second surface side through-hole conductor layer) is formed on the insulating layer 30a (second surface side through-hole insulating layer) with a copper foil 201c, for example, an electroless plating film 202c of copper, and an electrolytic layer of copper, for example. The plating 203c is laminated in this order. That is, the conductor layer 31 includes a power feeding layer composed of the copper foil 201c and the electroless plating film 202c, and an electrolytic plating 203c formed on the power feeding layer.

  The via conductor 22 formed in the insulating layer 20a (first surface side through-hole insulating layer) and the via conductor 32 formed in the insulating layer 30a (second surface side through-hole insulating layer) are shown in FIG. 29A, for example. Thus, the via holes 22a and 32a are filled with, for example, copper electroless plating film 202d and, for example, copper electrolytic plating 203d. Specifically, the electroless plating film 202d is formed on the inner surfaces (wall surface and bottom surface) of the via holes 22a and 32a, and the inner side thereof is filled with the electrolytic plating 203d. That is, each of the via conductors 22 and 32 includes a power feeding layer made of an electroless plating film 202d and an electrolytic plating 203d formed on the power feeding layer.

  The conductor layers 41, 51, 61, 71, 81, 91 formed on the insulating layers 40a, 50a, 60a, 70a, 80a, 90a (each non-through-hole insulating layer) are, for example, as shown in FIG. On each insulating layer, copper foil 211a and, for example, copper electrolytic plating 212a are laminated in this order. That is, each of the conductor layers 41, 51, 61, 71, 81, 91 includes a power feeding layer made of the copper foil 211a and an electrolytic plating 212a formed on the power feeding layer.

  Via conductors 42, 52, 62, 72, 82, and 92 formed in the insulating layers 40a, 50a, 60a, 70a, 80a, and 90a (non-through hole insulating layers) are respectively formed in via holes 42a as shown in FIG. 29B, for example. 52a, 62a, 72a, 82a, and 92a are filled with a graphite film 210 and, for example, copper electrolytic plating 212b. Specifically, the graphite film 210 is formed on the inner surfaces (specifically, wall surfaces) of the via holes 42a, 52a, 62a, 72a, 82a, and 92a, and the inner side thereof is filled with the electrolytic plating 212b. That is, each of the via conductors 42, 52, 62, 72, 82, 92 includes a power feeding layer made of the graphite film 210 and an electrolytic plating 212 b formed on the power feeding layer.

  The configuration of the core part is the same as that of the first embodiment, for example (see FIG. 4C).

  In this embodiment, each of the insulating layers 20a, 40a, 60a, and 80a (first surface side interlayer insulating layer) and the insulating layers 30a, 50a, 70a, and 90a (respectively second surface side interlayer insulating layer) are provided with a power feeding layer. Via conductors 22, 32, 42, 52, 62, 72, 82, 92 including (electroless plating film 202 d, graphite film 210) and electrolytic plating 203 d, 212 b formed on the power feeding layer are formed. (See FIGS. 29A and 29B). The through-hole conductor 102 includes a power feeding layer (electroless plating film 202b) made of electroless plating and an electrolytic plating 203b formed on the power feeding layer, and includes an insulating layer 20a (first surface side through-hole). The feed layer (electroless plating film 202d) of the via conductor 22 formed in the hole insulating layer) and the feed layer (electroless plating) of the via conductor 32 formed in the insulating layer 30a (second surface side through-hole insulating layer). Each of the films 202d) is made of electroless plating, and is formed of via conductors 42, 52, 62, 72, 82 formed in the insulating layers 40a, 50a, 60a, 70a, 80a, 90a (respective non-through hole insulating layers). Each of the 92 power supply layers (graphite film 210) is made of a material (for example, graphite) different from electroless plating (particularly, electroless plating of copper).

  Thereby, it becomes possible to improve the reliability of electrical connection (particularly, interlayer connection) in the build-up portion of the wiring board 100a of the present embodiment (for details, refer to the description of the manufacturing method of the first embodiment). .

  In addition, although the through-hole conductor 102 of this embodiment has one end connected to the conductor layer 21 and the other end connected to the conductor layer 31, it is not limited to this. One end is connected to the first surface side conductor layer (for example, any one of the conductor layers 21, 41, 61, 81), and the other end is connected to the second surface side conductor layer (for example, any one of the conductor layers 31, 51, 71, 91). If the through-hole conductor is connected to (), an effect similar to the above effect can be obtained.

  The wiring board 100a of this embodiment can be manufactured by the method according to the manufacturing method of Embodiment 1.

  That is, the graphite film 210 can be formed by a method similar to the method shown in FIGS. 6 and 7, for example. The via conductors 42, 52, 62, 72, 82, and 92 can be formed by performing electrolytic plating while supplying power to the graphite film 210, for example (see, for example, FIGS. 9 to 11). The conductor layers 41, 51, 61, 71, 81, 91 are patterned by etching the conductor layers on both sides formed together with the via conductors 42, 52, 62, 72, 82, 92 by, for example, electrolytic plating. This can be formed (see, for example, FIGS. 15A and 15B).

  The electroless plating films 202b and 202d can be formed by a method similar to the method shown in FIG. 23A, for example. Further, the through-hole conductor 102 and the via conductors 22 and 32 can be formed, for example, by performing electroplating while supplying power to each of the electroless plating films 202b and 202d (see, for example, FIG. 23B). The conductor layers 21 and 31 can be formed by patterning the conductor layers on both sides formed together with the through-hole conductor 102 and the via conductors 22 and 32 by, for example, electrolytic plating (for example, FIG. 25A and FIG. 25B). In the present embodiment, after the through-hole conductor 102 is formed in the inner layer, the upper layer is subsequently formed, and the build-up portion is formed up to the outermost layer.

  With regard to the same configuration and processing as in the first embodiment, an effect similar to the effect of the first embodiment described above can also be obtained in this embodiment.

(Other embodiments)
In the above embodiment, a material different from electroless plating other than graphite is adopted as the material for the power supply layer of the via conductor formed in the first surface side through-hole insulating layer or the second surface side through-hole insulating layer. be able to. For example, if the material of these power supply layers is a material that is less soluble in the solution 2002 than the plating metal, it is possible to increase the separation voltage V2 or to increase the separation time (time T2) of the plating metal. Further, if the material of the power feeding layer is a non-metallic conductive material, it becomes easy to completely remove the unnecessary material of the power feeding layer that tends to remain on the conductive layer made of metal. Further, if the material of the power feeding layer is a non-metallic conductive material containing carbon such as graphite or carbon black, it becomes easy to impart high conductivity, and high adhesion with the interlayer insulating layer made of resin. It is easy to obtain. Further, if a material different from the electroless plating of copper is adopted as a material for these power supply layers and the power supply layer is formed without using formalin or palladium, it is advantageous in terms of environmental load or cost. Moreover, it is preferable that the material of these electric power feeding layers is a material whose resistance value is higher than the material of the electric power feeding layer of the via conductor formed in the non-through-hole insulating layer.

  Instead of the through hole 102a made of the hole used in the wiring board 100 (FIG. 1) of the above embodiment, as shown in FIG. 30A, the through hole 102b made of a notch penetrating the wiring board 100 in the Z direction (stacking direction). May be used. The through hole 102b is formed on the side surface of the wiring board, for example. Also in this case, a through-hole conductor is formed on the wall surface of the through-hole 102b as in the above embodiment. As shown in FIG. 30B, a through hole 102a made of a hole and a through hole 102b made of a notch may be used in combination. For example, as shown in FIG. 31, the through hole 102b made of a notch can be formed by dividing (cutting) the through hole 102a with a line L10 after forming the through hole 102a made of a hole.

  The connection conductor 12 is not limited to a via conductor, and may be a through-hole conductor, for example, as shown in FIG. In this case, the connection conductor 12 is continuous with the conductor layers 11a and 11b at least partially (for example, a plating layer). The connection conductor 12 can be manufactured by a method according to the manufacturing method of the through-hole conductor 102, for example.

  The shape of the through-hole conductor 102 is not limited to a cylindrical shape, and is arbitrary. For example, even if it has a drum shape (hourglass shape) that narrows from both ends toward the inside (for example, the core insulating layer 10a), it extends from one end to the other end. It may be tapered (conical or truncated pyramid). The drum-shaped through-hole conductor 102 can be formed, for example, by irradiating laser light from both sides of the insulating layer. The tapered through-hole conductor 102 can be formed, for example, by irradiating laser light from one side of the insulating layer.

  With respect to other points as well, the configuration of the wiring board 100 of the above embodiment, in particular, the type, performance, dimensions, material, shape, number of layers, arrangement, etc. of the components are arbitrary within the scope of the present invention. Can be changed.

  For example, as shown in FIG. 33 (a diagram corresponding to FIG. 4A), the conductor layers 81 and 91 may be configured by an electroless plating film 202 a and an electrolytic plating 203 a without having a copper foil.

  In the first or second embodiment, the power feeding layer of the connection conductor 12 may be formed by electroless plating.

  The planar shape (XY plane) of the connecting conductor 12, the via conductors 22, 32, 42, 52, 62, 72, 82, 92, the through-hole conductors 102, and their openings (holes) is a circle (perfect circle). Or an ellipse or the like. These planar shapes may be substantially square as shown in FIG. 34A, for example. Further, it may be a substantially regular polygon other than a substantially square, such as a substantially regular hexagon or a substantially regular octagon. In addition, the shape of the polygonal corner is arbitrary, and may be rounded, for example, substantially right angle, acute angle, obtuse angle. However, in order to prevent concentration of thermal stress, it is preferable that the corners are rounded.

  Further, each of the planar shapes may be a substantially rectangular shape or a substantially triangular shape, or a shape in which a straight line is drawn radially from the center, such as a substantially cross shape shown in FIG. 34B or a substantially regular polygonal star shape shown in FIG. 34C. (A shape in which a plurality of blades are arranged radially) may be used.

  Moreover, the side surface (or the wall surface of each opening) of each conductor (such as the connection conductor 12) may be tapered. It does not have to be tapered.

  The method for manufacturing a wiring board according to the present invention is not limited to the order and contents shown in the embodiment, and the order and contents can be arbitrarily changed without departing from the gist of the present invention. Moreover, you may omit the process which is not required according to a use etc.

  The said embodiment and modification can be combined arbitrarily. It is preferable to select an appropriate combination according to the application.

  The embodiment of the present invention has been described above. However, various modifications and combinations required for design reasons and other factors are not limited to the invention described in the “claims” or the “mode for carrying out the invention”. It should be understood that it is included in the scope of the invention corresponding to the specific examples described in the above.

  The wiring board according to the present invention is suitable for a circuit board such as a mobile phone. The method for manufacturing a wiring board according to the present invention is suitable for manufacturing such a wiring board.

10a Core insulating layer 11a, 11b Conductor layer 12 Connection conductor 12a Connection hole 20a, 40a, 60a, 80a Insulation layer 21, 41, 61, 81 Conductor layer 22, 42, 62, 82 Via conductor 22a, 42a, 62a, 82a Via hole 30a, 50a, 70a, 90a Insulating layer 31, 51, 71, 91 Conductor layer 32, 52, 72, 92 Via conductor 32a, 52a, 72a, 92a Via hole 100, 100a Wiring board 102 Through-hole conductor 102a Through hole 102b Through hole 200 Electronic component 201a, 201c Copper foil 202a, 202b, 202c, 202d Electroless plating film 203a, 203b, 203c, 203d Electroplating 210 Graphite film 211a Copper foil 212a, 212b Electroplating 220 Graphite film 221 231a Copper foil 222a, 222b, 232a Electroplating 1000 Laminate plate 1001, 1002 Metal foil 1003 Power feeding layer 1003a Graphite film 1003b Power feeding layer 1004a Metal 1006, 1007 Etching resist 1006a, 1007a Opening 1011, 1012 Metal foil 1013, 1014 Power feeding layer 1021, 1022 Metal foil 1023 Electroless plating film 1023a Graphite film 1031, 1032 Etching resist 1031a, 1032a Opening 1033, 1034 Solder resist 1033a, 1034a Opening 1033b, 1034b Solder 2001 First electrode 2002 Solution 2002a Container 2003 Power supply F1 First Surface F2 Second surface F10 Wall surface F20 Side surface F21 Wall surface F22 Bottom surface F23 Top surface R11 Potential portion R12 high potential portion S-filled stack

Claims (13)

A core insulating layer having a first surface and a second surface opposite thereto;
A plurality of first surface side conductor layers formed on the first surface side of the core insulating layer;
A plurality of second surface side conductor layers formed on the second surface side of the core insulating layer;
A first surface side interlayer insulating layer formed between the first surface side conductor layers;
A second surface side interlayer insulating layer formed between the second surface side conductor layers,
A through hole conductor having one end connected to the first surface side conductor layer and the other end connected to the second surface side conductor layer;
A wiring board having
Via conductors including a power supply layer and electrolytic plating formed on the power supply layer are formed in each of the first surface side interlayer insulating layer and the second surface side interlayer insulating layer,
The through-hole conductor includes a power feeding layer made of electroless plating, and electrolytic plating formed on the power feeding layer,
The feed layer of the via conductor formed in the first surface side interlayer insulating layer below the first surface side conductor layer to which one end of the through hole conductor is connected is connected to the other end of the through hole conductor. Each of the power supply layers of the via conductor formed in the second surface side interlayer insulating layer under the second surface side conductor layer is made of electroless plating, and the other power supply layers of the via conductor are Each is made of a material different from electroless plating.
A wiring board characterized by that. The material different from the electroless plating is graphite,
The wiring board according to claim 1. The through-hole conductor penetrates the wiring board and electrically connects the first surface side conductor layer of the outermost layer and the second surface side conductor layer of the outermost layer to each other.
The wiring board according to claim 1 or 2, wherein The number of layers of the first surface side conductor layer and the number of layers of the second surface side conductor layer are each 5 or more,
The wiring board as described in any one of Claims 1 thru | or 3 characterized by the above-mentioned. In the wall surface of the through hole, at least one of the first surface side conductor layer of the inner layer and the second surface side conductor layer of the inner layer and the through hole conductor are electrically connected to each other.
The wiring board as described in any one of Claims 1 thru | or 4 characterized by the above-mentioned. A hole penetrating the core insulating layer is formed in the core insulating layer,
On the wall surface of the hole, the first surface side conductor layer formed on the first surface of the core insulating layer and the second surface side conductor layer formed on the second surface of the core insulating layer; Having connection conductors that are electrically connected to each other,
The connection conductor includes a power feeding layer made of graphite, and electrolytic plating formed on the power feeding layer.
The wiring board according to any one of claims 1 to 5, wherein The hole penetrating the core insulating layer is filled with the power feeding layer and the electrolytic plating,
The wiring board according to claim 6. The via conductor formed in each of the first surface side interlayer insulating layer and the second surface side interlayer insulating layer is formed in each of the first surface side interlayer insulating layer and the second surface side interlayer insulating layer. The via hole filled with the power supply layer and the electrolytic plating,
The wiring board according to any one of claims 1 to 7, wherein The first surface-side conductor layer and the second surface-side conductor layer each include a power feeding layer made of at least one of electroless plating and metal foil, and electrolytic plating formed on the power feeding layer.
The wiring board according to any one of claims 1 to 8, wherein Providing a core insulating layer having a first surface and a second surface opposite the first surface;
Forming a plurality of first surface-side conductor layers formed on the first surface side of the core insulating layer and a first surface-side interlayer insulating layer formed between the first surface-side conductor layers; When,
Forming a plurality of second surface side conductor layers formed on the second surface side of the core insulating layer and a second surface side interlayer insulating layer formed between the second surface side conductor layers; When,
Forming a via hole in each of the first surface side interlayer insulating layer and the second surface side interlayer insulating layer, and forming a via conductor in the via hole;
A through hole is formed in the core insulating layer, the first surface side interlayer insulating layer, and the second surface side interlayer insulating layer, and one end is connected to the first surface side conductor layer in the through hole, Forming a through-hole conductor having the other end connected to the second surface side conductor layer;
A method of manufacturing a wiring board including:
Formation of the through-hole conductor, formation of the via conductor formed in the first-surface-side interlayer insulating layer under the first-surface-side conductor layer to which one end of the through-hole conductor is connected, and the through-hole conductor In the formation of the via conductors formed in the second surface side interlayer insulating layer below the second surface side conductor layer to which the other end is connected, after forming a power supply layer made of electroless plating, the power supply layer Electrolytic plating is performed while supplying power to the electroplating layer on the power supply layer,
In the formation of the other via conductors, after forming a power feeding layer made of a material different from electroless plating, electrolytic plating is performed while feeding the power feeding layer to form electrolytic plating on the power feeding layer.
A method for manufacturing a wiring board. The material different from the electroless plating is graphite,
The method for manufacturing a wiring board according to claim 10. The through-hole conductor penetrates the wiring board and electrically connects the first surface side conductor layer of the outermost layer and the second surface side conductor layer of the outermost layer to each other.
The method for manufacturing a wiring board according to claim 10 or 11, wherein: By forming the through hole, at least one of the first surface side conductor layer of the inner layer and the second surface side conductor layer of the inner layer is scraped, and the scraped conductor layer is exposed on the wall surface of the through hole.
The method for manufacturing a wiring board according to any one of claims 10 to 12, wherein:

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