JP5163863B2 - クロック信号発生装置 - Google Patents
クロック信号発生装置 Download PDFInfo
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- JP5163863B2 JP5163863B2 JP2007286319A JP2007286319A JP5163863B2 JP 5163863 B2 JP5163863 B2 JP 5163863B2 JP 2007286319 A JP2007286319 A JP 2007286319A JP 2007286319 A JP2007286319 A JP 2007286319A JP 5163863 B2 JP5163863 B2 JP 5163863B2
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- clock signal
- signal
- value
- transmission
- processing apparatus
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Description
また、本発明の目的は、多値レベル信号を伝送する際のクロック信号としても好適なクロック信号を発生するクロック信号発生装置を提供することである。
Claims (5)
- 正弦波信号からなる第1クロック信号を出力する信号発生部と、
前記第1クロック信号の振幅値内に設定された複数の閾値と前記第1クロック信号の瞬時値とを比較して前記第1クロック信号の位相を判別し、当該位相に対応して信号の立ち上がり又は立ち下がりを決定して第2クロック信号を形成する位相角度検出部と、を備え、
前記位相角度検出部は、前記第1クロック信号の前半周期においては第1の閾値群を使用し、前記第1クロック信号の後半周期においては当該第1の閾値群と閾値にずれがある第2の閾値群を使用して前記第2クロック信号の立ち上がり又は前記立ち下がりを決定し、前記第1クロック信号の一周期分に相当する前記第2クロック信号の信号波形を前記前半周期と前記後半周期とで左右非対称に形成する、クロック信号発生装置。 - 前記複数の閾値と前記第1クロック信号の瞬時値との比較がウインドコンパレータによって行われる、請求項1に記載のクロック信号発生装置。
- 前記第2クロック信号は信号バスの伝送クロック信号として使用され、
前記第1クロック信号の波形の最大振幅値が前記信号バスのデータ線を伝送する多値レベル信号の最大値に応じて設定される、請求項1に記載のクロック信号発生装置。 - 請求項1乃至3のいずれかに記載のクロック信号発生装置を備える情報処理装置。
- 前記情報処理装置が携帯電話機である、請求項4に記載の情報処理装置。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007286319A JP5163863B2 (ja) | 2006-12-14 | 2007-11-02 | クロック信号発生装置 |
US12/001,875 US7755409B2 (en) | 2006-12-14 | 2007-12-13 | Clock signal generator |
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006336494 | 2006-12-14 | ||
JP2006336494 | 2006-12-14 | ||
JP2007286319A JP5163863B2 (ja) | 2006-12-14 | 2007-11-02 | クロック信号発生装置 |
Publications (3)
Publication Number | Publication Date |
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JP2008171394A JP2008171394A (ja) | 2008-07-24 |
JP2008171394A5 JP2008171394A5 (ja) | 2010-12-16 |
JP5163863B2 true JP5163863B2 (ja) | 2013-03-13 |
Family
ID=39699390
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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JP2007286319A Expired - Fee Related JP5163863B2 (ja) | 2006-12-14 | 2007-11-02 | クロック信号発生装置 |
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JP (1) | JP5163863B2 (ja) |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63294012A (ja) * | 1987-05-26 | 1988-11-30 | Nec Ic Microcomput Syst Ltd | ヒステリシス回路 |
JPH02105715A (ja) * | 1988-10-14 | 1990-04-18 | Nec Corp | シュミットトリガ回路 |
JP4245136B2 (ja) * | 2002-07-29 | 2009-03-25 | 富士通マイクロエレクトロニクス株式会社 | ジッター発生回路及び半導体装置 |
JP3692418B2 (ja) * | 2002-10-09 | 2005-09-07 | 沖電気工業株式会社 | 半導体装置の誤動作防止回路 |
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2007
- 2007-11-02 JP JP2007286319A patent/JP5163863B2/ja not_active Expired - Fee Related
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JP2008171394A (ja) | 2008-07-24 |
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