JP5144542B2 - アドレス変換バイパスを有するデータ処理システム及びその方法 - Google Patents

アドレス変換バイパスを有するデータ処理システム及びその方法 Download PDF

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JP5144542B2
JP5144542B2 JP2008556490A JP2008556490A JP5144542B2 JP 5144542 B2 JP5144542 B2 JP 5144542B2 JP 2008556490 A JP2008556490 A JP 2008556490A JP 2008556490 A JP2008556490 A JP 2008556490A JP 5144542 B2 JP5144542 B2 JP 5144542B2
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address
logical address
bypass
logical
translation
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JP2009527861A5 (enExample
JP2009527861A (ja
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シー． モイヤー、ウィリアム
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ラムバス・インコーポレーテッド
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/0292—User address space allocation, e.g. contiguous or non contiguous base addressing using tables or multilevel address translation means

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
JP2008556490A 2006-02-23 2007-01-29 アドレス変換バイパスを有するデータ処理システム及びその方法 Expired - Fee Related JP5144542B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/360,926 US7376807B2 (en) 2006-02-23 2006-02-23 Data processing system having address translation bypass and method therefor
US11/360,926 2006-02-23
PCT/US2007/061191 WO2007117746A2 (en) 2006-02-23 2007-01-29 Data processing system having address translation bypass and method therefor

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JP2009527861A JP2009527861A (ja) 2009-07-30
JP2009527861A5 JP2009527861A5 (enExample) 2010-03-04
JP5144542B2 true JP5144542B2 (ja) 2013-02-13

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US (2) US7376807B2 (enExample)
JP (1) JP5144542B2 (enExample)
CN (1) CN101390062B (enExample)
TW (1) TW200817900A (enExample)
WO (1) WO2007117746A2 (enExample)

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Also Published As

Publication number Publication date
WO2007117746A2 (en) 2007-10-18
US7447867B2 (en) 2008-11-04
US7376807B2 (en) 2008-05-20
CN101390062B (zh) 2011-02-23
WO2007117746A3 (en) 2008-10-30
US20070198804A1 (en) 2007-08-23
US20070198805A1 (en) 2007-08-23
TW200817900A (en) 2008-04-16
JP2009527861A (ja) 2009-07-30
CN101390062A (zh) 2009-03-18

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