TW200817900A - Data processing system having address translation bypass and method therefor - Google Patents

Data processing system having address translation bypass and method therefor Download PDF

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Publication number
TW200817900A
TW200817900A TW096103283A TW96103283A TW200817900A TW 200817900 A TW200817900 A TW 200817900A TW 096103283 A TW096103283 A TW 096103283A TW 96103283 A TW96103283 A TW 96103283A TW 200817900 A TW200817900 A TW 200817900A
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TW
Taiwan
Prior art keywords
address
logical
logical address
processing system
control
Prior art date
Application number
TW096103283A
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English (en)
Chinese (zh)
Inventor
William C Moyer
Original Assignee
Freescale Semiconductor Inc
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Application filed by Freescale Semiconductor Inc filed Critical Freescale Semiconductor Inc
Publication of TW200817900A publication Critical patent/TW200817900A/zh

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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/0292—User address space allocation, e.g. contiguous or non contiguous base addressing using tables or multilevel address translation means

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
TW096103283A 2006-02-23 2007-01-30 Data processing system having address translation bypass and method therefor TW200817900A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11/360,926 US7376807B2 (en) 2006-02-23 2006-02-23 Data processing system having address translation bypass and method therefor

Publications (1)

Publication Number Publication Date
TW200817900A true TW200817900A (en) 2008-04-16

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Family Applications (1)

Application Number Title Priority Date Filing Date
TW096103283A TW200817900A (en) 2006-02-23 2007-01-30 Data processing system having address translation bypass and method therefor

Country Status (5)

Country Link
US (2) US7376807B2 (enExample)
JP (1) JP5144542B2 (enExample)
CN (1) CN101390062B (enExample)
TW (1) TW200817900A (enExample)
WO (1) WO2007117746A2 (enExample)

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TWI719786B (zh) * 2019-12-30 2021-02-21 財團法人工業技術研究院 資料處理系統與方法

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI719786B (zh) * 2019-12-30 2021-02-21 財團法人工業技術研究院 資料處理系統與方法
US11609559B2 (en) 2019-12-30 2023-03-21 Industrial Technology Research Institute Data processing system and method

Also Published As

Publication number Publication date
WO2007117746A2 (en) 2007-10-18
JP5144542B2 (ja) 2013-02-13
US7447867B2 (en) 2008-11-04
US7376807B2 (en) 2008-05-20
CN101390062B (zh) 2011-02-23
WO2007117746A3 (en) 2008-10-30
US20070198804A1 (en) 2007-08-23
US20070198805A1 (en) 2007-08-23
JP2009527861A (ja) 2009-07-30
CN101390062A (zh) 2009-03-18

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