JP5140508B2 - Gaming machine and confirmation system for gaming machine - Google Patents

Description

  The present invention relates to a gaming machine and a gaming machine confirmation system for confirming the operation of a light emitting means.

Conventionally, a pachinko machine, which is a kind of gaming machine, includes, for example, a liquid crystal display type variable display, and a symbol combination game in which a plurality of types of symbols are changed in the variable display to derive a combination of symbols (symbol changing game) Has been done. Then, the player can recognize the big hit or miss from the symbol combination derived in the symbol combination game and finally stopped and displayed. In such a pachinko machine, in order to enhance the fun of the game, a lot of effect execution means such as LEDs are used. At the time of shipment, it is necessary to perform operation confirmation for confirming whether or not various effect execution means are normally controlled, such as confirmation of connection between the LED and the effect control board. A technique for confirming this operation is described in Patent Document 1, for example. In this Patent Document 1, the test relay terminal board receives data signals DA0 to DA7, chip select signals CSSG1 and CSSG2, and detection signals SG2 to SG6 from the main control device, processes the input signals, and outputs data signals. DC0 to DC7, DD0 to DD7, and detection signals SG2 to SG6 are generated and output to the performance tester. The performance tester can perform a performance test based on the input signal.
JP 2006-141459 A (paragraph numbers [0246] to [0255])

  By the way, in patent document 1, the relay terminal board for a test is outputting the signal to a performance testing machine instead of the control board for presentation in a game machine. However, in order to check whether the LED for control is connected to the production control board and the LED is lit, it is necessary to directly input a signal from the production control board. At this time, the output data signals DC0 to DC7 and DD0 to DD7 are processed and increased from the data signals DA0 to DA7 output from the main control board in order to correspond to the types of LEDs. If the number of LED types is small, the number of data signals DC0 to DC7 and DD0 to DD7 to be inspected is small, and the time for checking can be reduced accordingly. It takes time to check whether the data signal is normally output, and there is a problem that the efficiency is low.

  The present invention has been made paying attention to such problems existing in the prior art. An object of the present invention is to provide a gaming machine and a gaming machine confirmation system capable of shortening the time for operation confirmation.

  In order to achieve the above object, the invention according to claim 1 comprises a main control means for executing control of a gaming machine and a plurality of integrated circuits, and a light emission effect based on a control signal input from the main control means. In the gaming machine in which the effect control means turns on the light emitting means with a predetermined light emission pattern when confirming the operation, the light emitting means is controlled by a dynamic drive system. The lighting means specified by the first signal and the second signal is supplied with a voltage to be lit, and the effect control means is data that is a part of the control signal input from the main control means. Based on the signal, it is configured to generate a first signal that switches in order for each cycle and a second signal that switches for each cycle, and output the generated first signal and second signal to the light emitting means. Each of the integrated circuits is configured to be capable of inputting / outputting a plurality of predetermined control signals, and a chip select signal for designating an integrated circuit that is a part of the control signal from the main control means. When the input is specified by the chip select signal, a plurality of types of first signals or a plurality of types of second signals are generated based on a data signal that is a part of the control signal input from the main control means. The main control means outputs a plurality of types of data signals to the effect control means and outputs a chip select signal to the effect control means to output the effect control means. By switching the integrated circuit, one or more types of second signals are generated from the one type of data signal by the effect control means, and the generated second signals are sent to the light emitting means. The main control means changes the chip select signal so as to switch the integrated circuit that outputs the second signal when switching the light emitting means to be lit when checking the operation. And outputting all types of chip select signals at least once before the operation confirmation is completed, and the effect control means is for switching the light emitting means to be lit during the operation confirmation. When there are a plurality of unconfirmed data signals that are generation sources of the first signal of the type that has not been output at the same time as the second signal and that have not yet been output, The first signal generated based on one data signal is output from the unconfirmed data signals, and at the same time, When the second signal generated based on a data signal different from the data signal that is the source of the first signal to be output is output, and when the light emitting means to be lit is switched during operation check, the unconfirmed data signal is When there is one, a predetermined second signal is output when a first signal generated based on the unconfirmed data signal is output, or a second signal generated based on the unconfirmed data signal is output as a predetermined first signal The output control means is configured to output at the time of output, and the effect control means inputs all kinds of chip select signals at least once and performs operation confirmation until the unconfirmed data signal disappears.

  The invention according to claim 2 includes a main control means for executing control of the gaming machine and a plurality of integrated circuits, and the light emission effects for the effects are generated based on the control signals input from the main control means. A game machine having an effect control means to be executed by the means, and an inspection light emitting means connected to the game machine at the time of confirming the operation and receiving a control signal from the effect control means, and the effect control means at the time of confirming the operation In the confirmation system for gaming machines that turns on the light-emitting means for inspection with a predetermined light-emitting pattern, the light-emitting means for effect is controlled by a dynamic drive system, and for the effect specified by the first signal and the second signal A voltage is supplied to the light emitting means to emit light, and the inspection light emitting means has the same configuration as the effect light emitting means, and the effect control means includes the main control means. Based on the data signal that is a part of the control signal that has been input, a first signal that switches in turn for each cycle and a second signal that switches in each cycle are generated, and the generated first signal and second signal are used as the effects. Each integrated circuit is configured to be capable of inputting and outputting a plurality of predetermined control signals, and from the main control means. When a chip select signal that designates an integrated circuit that is a part of the control signal is input and is specified by the chip select signal, it is based on a data signal that is a part of the control signal input from the main control means. A plurality of types of first signals or a plurality of types of second signals are generated and output to the effect light-emitting means or the inspection light-emitting means, and the main control means includes a plurality of types A data signal is output to the effect control means, and a chip select signal is output to the effect control means to switch an integrated circuit of the effect control means, thereby switching one or more types of second signals from one type of data signal. Is generated in the production control means, and the produced second signal can be output to the production light emission means or the inspection light emission means. When switching the inspection light-emitting means to be lit, the chip select signal is changed and output so as to switch the integrated circuit that outputs the second signal. It is configured to output at least once. However, when there are a plurality of unconfirmed data signals that are generation sources of the first signal of the type that is not output at the same time as the second signal and that are not yet output, A data signal that is different from a data signal that is the source of the first signal that is simultaneously output from the unconfirmed data signal, at the same time that the first signal generated based on one data signal is output from the data signal In the case of switching the inspection light-emitting means to be turned on during operation confirmation, when there is one unconfirmed data signal, the first signal generated based on the unconfirmed data signal is output. When a signal is output, a predetermined second signal is output, or a second signal generated based on the unconfirmed data signal is output when the predetermined first signal is output Configured urchin, the presentation control means inputs at least once all types of chip select signal, and the gist of performing the operation check to said unconfirmed data signal is eliminated.

  According to the present invention, the operation confirmation time can be shortened.

Hereinafter, an embodiment in which the present invention is embodied in a pachinko gaming machine (hereinafter referred to as a “pachinko machine”) which is a kind of gaming machine will be described with reference to FIGS.
In FIG. 1, the front side of the pachinko machine 10 is schematically shown, and a vertical rectangular middle frame 12 for setting various game components is opened and closed on the front side of the opening of the outer frame 11 that forms the outline of the machine And is detachably assembled. Further, on the front side of the middle frame 12, a front frame 14 and a top ball tray 15 each having a glass frame for protecting the game board 13 disposed inside the machine in a see-through manner are assembled so as to be openable and closable in a laterally open state. ing. In addition, a speaker 17 that outputs various sounds (sound effects) and performs sound effects based on the sound output is provided below the outer frame 11. A lower ball tray 18 and a launching device 19 are attached to the lower part of the middle frame 12.

  A display decoration member C with various decorations is provided in the approximate center of the game area 13a of the game board 13, and a display provided with a liquid crystal display type variable display H at the window CW of the decoration member C. A device 20 is provided.

  The display decorative member C is made of a translucent material that transmits light. In FIG. 2, on the left side of the variable display H, a rope decoration portion C1 is arranged as a display decorative member C simulating a longline. Also, on the upper side of the variable display H, a thousand box decoration part C2 is arranged as a display decorative member C imitating a thousand box. Further, on the right side of the variable display H, a lantern decoration portion C3 is arranged as a display decorative member C imitating a lantern. Further, a cloud decoration portion C4 as a display decoration member C imitating a cloud is arranged on the outer periphery of the display device 20 (outside of the thousand-thousand box decoration portion C2 and the lantern decoration portion C3).

  In the variable display H, a game effect (display effect) based on a varying image (or image display) is performed. In the variable display H, a symbol combination game (symbol variation game) is displayed in which a plurality of types of symbols are varied and displayed in a plurality of columns. In the present embodiment, combinations of three columns of symbols are derived in the symbol combination game, and the types of symbols of each column forming the combination are eight types of 1-8.

  Then, the player can recognize a big hit or loss from the symbol combination finally displayed in the symbol combination game. When the symbols of all the columns displayed on the variable display H are of the same type, the big hit can be recognized from the symbol combination ([222] [777], etc.). The symbol combination that can recognize the jackpot is a jackpot symbol combination. When the jackpot symbol combination is displayed, the player is given a jackpot gaming state. On the other hand, when the symbols of all the columns displayed on the variable display H are of different types, or when the symbols of one column are different from the symbols of the other two columns, the symbol combination ([123] [122] [767] etc.) can be recognized. A symbol combination that can recognize this deviation is a symbol combination that is out of sync. Further, in the pachinko machine 10 of the present embodiment, when the symbol combination game starts (when the symbols in each column start to change), the left column (left symbol) → the right column (right symbol) → middle as viewed from the player side The symbols are displayed in the order of columns (middle symbols). When the displayed left symbol and right symbol are of the same type, the reach can be recognized from the symbol combination ([↓] indicates that the symbol is changing, such as [1 ↓ 1]). The symbol combination that can recognize this reach is the symbol combination of the reach.

  As shown in FIG. 1, a start winning opening 22 including an opening / closing blade 21 that opens and closes by the operation of an actuator (solenoid, motor, etc.) not shown is disposed below the display device 20. Behind the start winning opening 22 is provided a start opening sensor SE1 (shown in FIG. 3) as a winning detection means for detecting a winning game ball. The start winning opening 22 can give a start condition for the symbol combination game in response to detection of winning of a game ball. Also, below the start winning port 22, a large winning port 24 having a large winning port door 23 that opens and closes by the operation of an actuator (solenoid, motor, etc.) (not shown) is disposed. When the big hit gaming state is given, the big winning opening 24 is opened by the opening operation of the big winning opening door 23 so that the game ball can be won, so that the player has a chance to acquire a large number of winning balls. Can be obtained. In FIG. 1, cloud decoration portions C5 and C6 are arranged on the left and right sides of the start winning opening 22 as decoration members C for the game board 13 simulating clouds.

  In addition, on the front side of the front frame 14 and the game area 13 a of the game board 13, a decoration lamp 16 that is turned on (flashes) or turned off and performs a light emission effect based on the light emission decoration is provided. More specifically, the decorative lamp 16 includes a game board lamp 16 a disposed on the game board 13 and a frame lamp 16 b disposed on the front frame 14.

  First, the game board lamp 16a will be described. The game board lamp 16a is composed of a plurality of light emitting elements (in this embodiment, light emitting diodes). In the light emitting diode, the lightness (luminance) of light emission is changed according to the time when the voltage is applied. The game board lamps 16a are respectively arranged on a plurality of lamp circuit boards 25 as shown in FIG. 4, and a decorative member C is covered thereon.

  More specifically, as shown in FIG. 4, a vertically long lamp circuit board 25 a is arranged on the left side of the variable display H in the display device 20. On the lamp circuit board 25a, ropes 1a, 1b, 1c, 2a, 2b, 2c, 3a, 3b, 3c, 4a, 4b and 4c are arranged. The ropes 1a, 1b, 1c, 2a, 2b, 2c, 3a, 3b, 3c, 4a, 4b and 4c are covered with a rope decoration portion C1. Therefore, when the leash lamps 1a, 1b, 1c, 2a, 2b, 2c, 3a, 3b, 3c, 4a, 4b, and 4c emit light, the leash decoration portion C1 appears to emit light. The ropes 1a, 2a, 3a, 4a, 1b, 2b, 3b, 4b emit red light, and the ropes 1c, 2c, 3c, 4c emit white light.

  In the display device 20, a vertically long lamp circuit board 25b is arranged on the left side of the variable display H and on the right side of the lamp circuit board 25a. On the lamp circuit board 25b, the rope right side lamps 1d, 2d, 3d, and 4d are arranged. The rope right side lamps 1d, 2d, 3d, and 4d are covered with a rope decoration portion C1. Therefore, when the rope right side lamps 1d, 2d, 3d, and 4d emit light, the rope decoration portion C1 appears to emit light. The rope right lateral lamps 1d, 2d, 3d, and 4d emit red light.

  As shown in FIG. 4, the display device 20 is provided with a horizontally long lamp circuit board 25 c above the variable display H. On the lamp circuit board 25c, thousand-car box lower lamps 1p, 2p, 3p, 4p are horizontally arranged. The thousand box lower lamps 1p, 2p, 3p, and 4p are covered with the thousand box decoration portion C2. Therefore, when the thousand-car box lower lamps 1p, 2p, 3p, and 4p emit light, the thousand-car box decoration portion C2 appears to emit light.

  In the display device 20, a horizontally long lamp circuit board 25d is disposed above the variable display H and above the lamp circuit board 25c. On the lamp circuit board 25d, thousand-car box upper lamps 1o, 2o, 3o, 4o are arranged horizontally. The thousand-yen box upper lamps 1o, 2o, 3o, 4o are covered with a thousand-yen box decoration part C2. Accordingly, when the thousand-yen box upper lamps 1o, 2o, 3o, and 4o emit light, it appears that the thousand-yen box decoration portion C2 emits light. The thousand-car box upper lamps 1o, 2o, 3o, 4o and the thousand-car box lower lamps 1p, 2p, 3p, 4p emit white light.

  Further, the display device 20 is provided with a curved horizontally long lamp circuit board 25e above the variable display H and further above the lamp circuit board 25d. On the lamp circuit board 25e, outer peripheral upper lamps 1e, 2e, 3e, and 4e are horizontally arranged. The outer peripheral upper lamps 1e, 2e, 3e, 4e are covered with a cloud decoration portion C4. More specifically, outer peripheral upper lamps 1e, 2e, 3e, 4e are accommodated inside the cloud decoration portion C4. Therefore, when the outer peripheral upper lamps 1e, 2e, 3e, 4e emit light, the upper part of the cloud decoration portion C4 appears to emit light. The outer peripheral upper lamps 1e, 2e, 3e, and 4e emit red light.

  In the display device 20, a substantially triangular lamp circuit board 25f is disposed on the right side of the variable display H. On the lamp circuit board 25f, right inner peripheral lamps 1l, 1m, 2l, 3l, 2m, 4l, 3m, 1n, 2n, 4m, 3n and 4n are arranged in a plurality of rows. The right inner peripheral lamps 1l, 1m, 2l, 3l, 2m, 4l, 3m, 1n, 2n, 4m, 3n, and 4n are substantially covered with the cloud decoration portion C4. More specifically, right inner peripheral lamps 11, 1 m, 2 l, 3 l, 2 m, 4 l, 3 m, 1 n, 2 n, 4 m, 3 n, 4 n are accommodated inside the cloud decoration portion C4. Therefore, when the right inner peripheral lamps 1l, 1m, 2l, 3l, 2m, 4l, 3m, 1n, 2n, 4m, 3n, and 4n emit light, the right side of the cloud decoration portion C4 appears to emit light. The right inner peripheral lamps 1m, 2m, 3m, and 4m emit red light, the right inner peripheral lamps 1l, 2l, 3l, and 4l emit green light, and the right inner peripheral lamp. 1n, 2n, 3n, and 4n emit blue light.

  A substantially lantern-shaped lamp circuit board 25g is disposed on the lamp circuit board 25f and inside the lantern decoration portion C3. In other words, the lamp circuit board 25g is disposed so as to overlap the lamp circuit board 25f. In FIG. 4, for the sake of convenience, the lamp circuit board 25f is shown shifted to the left (on the variable display H). On the upper side of the lamp circuit board 25g, lantern upper lamps 1g, 2g, 3g, 4g, and in the center, lantern middle lamps 1i, 1j, 1k, 2i, 2j, 2k, 3i, 3j, 3k, 4i, On the lower side of 4j and 4k, lantern lower lamps 1h, 2h, 3h and 4h are arranged, respectively. Lantern upper lamps 1g, 2g, 3g, 4g, lantern middle lamps 1i, 1j, 1k, 2i, 2j, 2k, 3i, 3j, 3k, 4i, 4j, 4k, lantern lower lamps 1h, 2h, 3h, 4h Covered by the lantern decoration C3. Accordingly, the lantern upper lamps 1g, 2g, 3g, 4g, the lantern middle lamps 1i, 1j, 1k, 2i, 2j, 2k, 3i, 3j, 3k, 4i, 4j, 4k, the lantern lower lamps 1h, 2h, 3h, 4h When is emitted, the lantern decoration part C3 appears to emit light.

  The lantern upper lamps 1g, 2g, 3g, 4g and the lantern middle lamps 1i, 2i, 3i, 4i emit red light. The lantern middle lamps 1j, 2j, 3j, 4j emit green light. The lantern middle lamps 1k, 2k, 3k, and 4k and the lantern lower lamps 1h, 2h, 3h, and 4h emit blue light.

  In the display device 20, a curved lamp circuit board 25h is disposed on the right side of the variable display H and further on the right side of the lamp circuit board 25f. On the lamp circuit board 25h, outer peripheral right lamps 1f, 2f, 3f and 4f are vertically arranged. The outer peripheral right lamps 1f, 2f, 3f, 4f are covered with a cloud decoration portion C4. More specifically, the outer right lamps 1f, 2f, 3f, 4f are housed inside the right side of the outer periphery of the cloud decoration portion C4. Accordingly, when the outer right lamps 1f, 2f, 3f, and 4f emit light, the right side of the cloud decoration portion C4 appears to emit light. The outer right lamps 1f, 2f, 3f, 4f emit red light.

  A plurality of upper gradation lamps 5a to 5e, 6a to 6e, 7a to 7e, and 8a to 8e are disposed on the lamp circuit boards 25c, 25d, and 25e disposed above the variable display H. . The upper gradation lamps 5a to 5e, 6a to 6e, 7a to 7e, and 8a to 8e are arranged so as to be arranged in a plurality of rows horizontally. More specifically, the upper gradation lamps 5a to 8a are disposed on the lamp circuit board 25c above the thousand box lower lamps 1p, 2p, 3p, and 4p. Further, the upper gradation lamps 5b to 8b and 5c to 8c are arranged on the upper side of the thousand-car box upper lamps 1o, 2o, 3o and 4o in the lamp circuit board 25d. The upper gradation lamps 5d to 8d and 5e to 8e are arranged near or alternately with the outer peripheral upper lamps 1e, 2e, 3e, and 4e in the lamp circuit board 25e. The upper gradation lamps 5a to 5e, 6a to 6e, 7a to 7e, and 8a to 8e are covered with the upper part of the thousand-thousand box decoration part C2 and the cloud decoration part C4.

  A plurality of right gradation lamps 5f to 5j, 6f to 6j, 7f to 7j, and 8f to 8j are disposed on the lamp circuit boards 25f and 25h disposed on the right side of the variable display H. The right gradation lamps 5f to 5j, 6f to 6j, 7f to 7j, and 8f to 8j are arranged in a plurality of rows in the vertical direction. More specifically, the right gradation lamps 5f to 8f, 5g to 8g, and 5h to 8h are arranged on the lamp circuit board 25f with the right inner peripheral lamps 1l, 1m, 2l, 3l, 2m, 4l, 3m, 1n, 2n, and 4m. , 3n, 4n. Further, the right gradation lamps 5i to 8i and 5j to 8j are arranged near or alternately with the outer peripheral right lamps 1f to 4f in the lamp circuit board 25h. The right gradation lamps 5f to 5j, 6f to 6j, 7f to 7j, and 8f to 8j are covered with the right part of the cloud decoration portion C4.

  The game board 13 on the left side of the start winning opening 22 is provided with a substantially linear ramp circuit board 25i as shown in FIG. A plurality of lower gradation lamps 5k to 8k, 5l to 8l, 5m, and 6m are arranged on the lamp circuit board 25i. The lower gradation lamps 5k to 8k, 5l to 8l, 5m, and 6m arranged on the lamp circuit board 25i are covered with the cloud decoration portion C5. Further, on the game board 13 on the right side of the start winning opening 22, a ramp circuit board 25j having a substantially L shape as shown in FIG. 5B is arranged. A plurality of lower gradation lamps 7m, 8m, 5n to 8n, 5o, 6o are disposed on the lamp circuit board 25j. The lower gradation lamps 7m, 8m, 5n-8n, 5o, 6o arranged on the lamp circuit board 25j are covered with the cloud decoration portion C6.

  Next, the frame lamp 16b will be described. The frame lamp 16b is composed of a plurality of light emitting elements (in the present embodiment, light emitting diodes). In the light emitting diode, the lightness (luminance) of light emission is changed according to the time when the voltage is applied. As with the game board lamp 16a, the frame lamp 16b is disposed on each of the plurality of lamp circuit boards 25, and the decorative member C for the front frame 14 is covered thereon. The decorative member C for the front frame 14 is made of a translucent material that transmits light.

  More specifically, a vertically long lamp circuit board (not shown) is disposed on the left side of the front frame 14. As shown in FIG. 6, on the lamp circuit board, a plurality of frame left lamps 7o are arranged in a plurality of rows vertically. The frame left lamp 7o is covered with a decorative member C7 for the left side of the front frame 14. Accordingly, when the frame left lamp 7o emits light, the decorative member C7 on the left side of the front frame 14 appears to emit light. The frame left lamp 7o emits white light.

  Similarly, a vertically long lamp circuit board (not shown) is disposed on the right side of the front frame 14. On this lamp circuit board, a plurality of frame right lamps 8o are arranged in a plurality of rows vertically. The frame right lamp 8o is covered with a decorative member C8 for the right side of the front frame 14. Therefore, when the frame right lamp 8o emits light, the right decorative member C8 of the front frame 14 appears to emit light. The frame right lamp 8o emits white light.

  A horizontally long lamp circuit board (not shown) is disposed on the upper portion of the front frame 14. On the lamp circuit board, a plurality of top lamps 5p are arranged in a plurality of rows horizontally. The top lamp 5p is covered with the central portion of the decorative member C9 at the top of the front frame 14. Therefore, when the top lamp 5p emits light, it appears that the central portion of the decorative member C9 at the top of the front frame 14 emits light. A horizontally long lamp circuit board (not shown) is disposed on the front side of the upper ball tray 15. In this lamp circuit board, a plurality of rows of upper plate lamps 6p, 7p, 8p are arranged horizontally. The upper plate lamps 6p, 7p, and 8p emit white light.

Next, the control configuration of the pachinko machine 10 will be described with reference to FIG.
On the back side of the pachinko machine 10, a power supply board 26 that supplies a power source (for example, AC 24 V) of the game hall to various components constituting the pachinko machine 10 is mounted. A main control board 30 that controls the entire pachinko machine 10 is mounted on the back side of the pachinko machine 10. The main control board 30 executes various processes for controlling the entire pachinko machine 10, performs arithmetic processing on various control signals (control commands) for controlling the game according to the processing results, and outputs the control signals ( Control command). On the rear side of the machine, a general / lamp control board (hereinafter simply referred to as a general control board) 31, a display control board 32, and a sound control board 33 are mounted. The overall control board 31 comprehensively controls the display control board 32 and the audio control board 33 based on the control signal (control command) output from the main control board 30. The overall control board 31 controls the light emission mode (lighting (flashing) / lighting off timing, etc.) of the decorative lamp 16 based on a control signal (control command) output from the overall control board 31. In addition, the display control board 32 controls the display mode (display images such as symbols, backgrounds, and characters) of the variable display H based on the control signal (control command) output from the overall control board 31. The voice control board 33 controls the voice output mode (sound output timing, etc.) of the speaker 17 based on the control signal (control command) output from the overall control board 31.

Hereinafter, specific configurations of the power supply board 26, the main control board 30, the overall control board 31, the display control board 32, and the audio control board 33 will be described.
The power supply board 26 is provided with a power supply circuit 27 that converts the power supply of the game hall into a power supply voltage V0 (for example, DC 24V) as a supply voltage to the pachinko machine 10. The control boards 30 to 33 are connected to the power supply circuit 27. Then, the power supply circuit 27 further converts the converted power supply voltage V0 into predetermined power supply voltages V1 to V4 to be supplied corresponding to the control boards 30 to 33, and the converted power supply voltages V1 to V4. Is supplied to each of the control boards 30-33.

  Next, the main control board 30 will be described. As shown in FIG. 3, the main control board 30 is provided with a main CPU 30a, a ROM 30b, and a RAM 30c. The main CPU 30a updates the values of various random numbers in processing executed at predetermined intervals. The ROM 30b stores a main control program for controlling the pachinko machine 10 and a plurality of types of variation patterns. The RAM 30c stores (sets) various information (random number values and the like) that are appropriately rewritten during the operation of the pachinko machine 10.

  The variation pattern is a game effect (display effect, light effect, sound effect) from when the symbol starts to change (start of the symbol combination game) to when all the symbols are displayed (the symbol combination game ends). The pattern used as the base of this is shown, and the production time of the game effect is determined at least. Further, the plurality of types of variation patterns are classified into a variation pattern for a big hit effect, a variation pattern for a loss reach effect, and a variation pattern for a loss effect.

  The jackpot effect is an effect that the symbol combination game is developed so as to finally display the symbol combination of the jackpot through the reach effect. The outlier reach effect is an effect in which the symbol combination game is developed so as to finally display the symbol combination that has gone through the reach effect. The outlier effect is an effect that the symbol combination game is developed so as to finally display the symbol combination that is out of reach without undergoing the reach effect. In the reach production, after the reach symbol combination is displayed (in this embodiment, the right symbol of the same type as the left symbol once displayed is displayed once), the jackpot symbol combination or the off symbol combination is displayed. It is an effect performed until it is stopped.

  The main CPU 30a executes various processes such as jackpot determination, final stop symbol determination to be finally displayed, and variation pattern determination based on the main control program. For example, the main CPU 30a executes a winning process. In this winning process, the main CPU 30a determines whether or not winning of a game ball is detected at predetermined time intervals. When winning is detected, the main CPU 30a determines whether or not the number of reserved storage stored in the RAM 30c is less than the upper limit (4 in the present embodiment). When the number of reserved memories <4, the main CPU 30a adds (+1) to the number of reserved memories stored in the RAM 30c (+1) to rewrite the number of reserved memories. Subsequently, the main CPU 30a reads and acquires the value of the big hit random number from the RAM 30c, and sets the read value in a predetermined storage area of the RAM 30c associated with the reserved storage number. The big hit random number is a random number that is sequentially updated every predetermined cycle by the main CPU 30a, and the main CPU 30a rewrites the value before update by setting the updated value in the setting area of the RAM 30c. Then, the main CPU 30a ends the winning process.

  Then, the main CPU 30a determines whether or not the number of reserved memories is greater than “0” at predetermined time intervals. When the number of reserved memories is greater than 0, the main CPU 30a determines whether or not the symbol is in a variable display, that is, whether or not the symbol combination game is being performed. If the symbol combination game is not in progress, the main CPU 30. a determines whether or not the jackpot random number stored in the RAM 30c in association with the number of stored storage matches the jackpot determination value stored in the ROM 30b. In the present embodiment, the probability that the determination result of the jackpot determination is affirmative (the jackpot probability) is 1/300. When the determination result of the jackpot determination is affirmative (in the case of a jackpot), the main CPU 30a determines the final stop symbols so that all the columns are the same type, and also determines the variation pattern from the variation patterns for the jackpot effect. To do.

  On the other hand, when the determination result of the big hit determination is negative (in the case of loss), the main CPU 30a executes reach determination. When the determination result of reach determination is affirmative (when the reach effect is executed), the main CPU 30a finally stops so that the symbols in the left and right columns are the same type and the symbols in the middle row are not the same type as the symbols in the left and right columns. Determine the design. At the same time, the main CPU 30a determines a variation pattern from the variation patterns for the outlier reach effect. On the other hand, when the determination result of the reach determination is negative (when the reach effect is not executed), the main CPU 30a determines the final stop symbol so that the symbols on the left and right columns are not the same type. At the same time, the main CPU 30a determines a variation pattern from the variation patterns for the offending effect.

  The main CPU 30a that has determined the variation pattern and the final stop symbol outputs a predetermined control command to the overall control board 31 (overall CPU 31a) at a predetermined timing. Specifically, the main CPU 30a first outputs a variation pattern designation command that designates a variation pattern and instructs the start of symbol variation. Next, the main CPU 30a outputs a symbol designation command for designating a final stop symbol for each column. After that, the main CPU 30a instructs a change stop based on the change time set in the specified change pattern, and outputs an all symbol stop command for ending the symbol combination game.

  Next, the overall control board 31 will be described. As shown in FIG. 3, the overall control board 31 is provided with an overall CPU 31a. The overall CPU 31a sequentially updates the values of various random numbers in processing executed at predetermined intervals. Further, a ROM 31b and a RAM 31c are connected to the overall CPU 31a. The ROM 31b stores an overall control program for comprehensively controlling the control boards 32 to 33, a light emission control program for performing light emission control, and the like. The RAM 31c stores (sets) various information that can be appropriately rewritten during the operation of the pachinko machine 10.

  When a predetermined control command is input from the main CPU 30a at a predetermined timing, the overall CPU 31a outputs a predetermined control command at a predetermined timing accordingly. More specifically, when the general CPU 31a inputs a variation pattern designation command, the overall CPU 31a outputs the variation pattern designation command to each of the control boards 32-33. In addition, when the overall CPU 31 a inputs a symbol designation command or an all symbol stop command, the overall CPU 31 a outputs each command to the display control board 32.

  Further, when the general CPU 31a of the general control board 31 receives the control command, the general CPU 31a performs control according to the input control command based on the light emission control program. Specifically, the overall CPU 31a controls the light emission mode of the decoration lamp 16 according to the display content of the variable display H by outputting a control signal.

Next, the display control board 32 will be described.
As shown in FIG. 3, the display control board 32 includes a sub CPU 32a, and a ROM 32b and a RAM 32c are connected to the sub CPU 32a. The ROM 32b stores a display control program for controlling the display content of the variable display H. The RAM 32c stores (sets) various information that can be appropriately rewritten during the operation of the pachinko machine 10.

  When the sub CPU 32a receives a control command from the overall control board 31 (overall CPU 31a), the sub CPU 32a performs control according to the input control command based on the display control program. Specifically, when the sub CPU 32a inputs the variation pattern designation command, the variable display H is configured so that the symbol combination game is started based on the variation pattern designated by the variation pattern designation command and the symbol combination game is started. Control display content. When the sub CPU 32a inputs the all symbol stop command, the sub CPU 32a controls the display content of the variable display H so that the symbol combination designated by the input symbol designation command is displayed on the variable display H. By this control, the symbol combination game is performed on the variable display H.

Next, the voice control board 33 will be described.
As shown in FIG. 3, the audio control board 33 includes a sub CPU 33a, and a ROM 33b and a RAM 33c are connected to the sub CPU 33a. The ROM 33b stores a voice control program and the like for controlling the contents of voice presentation by the speaker 17. The RAM 33c stores (sets) various information that can be appropriately rewritten during the operation of the pachinko machine 10.

  When the sub CPU 33a inputs a control command from the overall control board 31 (overall CPU 31a), the sub CPU 33a performs control according to the input control command based on the voice control program. Specifically, the sub CPU 33a controls the audio output content by the speaker 17 in accordance with the display content of the variable display H.

Next, a detailed configuration of a substrate for causing the decorative lamp 16 to emit light will be described.
As shown in FIG. 3, a drive board 41 is connected to the overall control board 31 via a relay board AK. The relay board AK is configured to relay a control signal from the overall control board 31 to the drive board 41. The relay board AK converts the power supply voltage V2 supplied from the power supply board 26 via the overall control board 31 into a voltage having a predetermined value and supplies it to the drive board 41 as power. That is, since the value of the power supply voltage V2 supplied from the power supply board 26 varies (for example, DC 23 to 26V), the power supply voltage V2 supplied by the conversion circuit included in the relay board AK is stepped up and down to be determined in advance. Converted to a value (for example, 24 V) and supplied to the drive substrate 41. Thereby, when the decoration lamp 16 is turned on, it is possible to eliminate variations in luminance.

  Further, the drive board 41 generates four types of common signals COM1 to COM4 to be output to the drive circuit 50 of the lamp circuit board 25 based on the control signal relayed from the relay board AK, and sequentially and alternatively for a certain period ( In this embodiment, it is output every 2 ms). The drive board 41 outputs 16 types of segment signals ASEGA to ASEGp and 16 types of segment signals BSEGa to BSEGp based on the control signal relayed from the relay board AK.

  Specifically, as shown in FIG. 7, the drive substrate 41 includes an integrated circuit IC4 that outputs common signals COM1 to COM4, an integrated circuit IC5 that outputs eight types of segment signals ASEGa to ASEGh, and eight types of segments. An integrated circuit IC6 that outputs signals ASEGi to ASEGp is provided. The drive board 41 includes an integrated circuit IC8 that outputs eight types of segment signals BSEGa to BSEGh and an integrated circuit IC9 that outputs eight types of segment signals BSEGi to BSEGp.

  The integrated circuit IC4 is configured to input data signals D0 to D3 of a plurality of predetermined types (four types in the present embodiment) among a plurality of types of control signals to be input. Then, the integrated circuit IC4 generates the common signal COM1 when the data signal D0 is input when the chip select signal designating the integrated circuit IC4 is input from the relay substrate AK, and the driving circuit for the ramp circuit substrate 25 50 is output. Similarly, the integrated circuit IC4 generates the common signal COM2 when the chip select signal designating the integrated circuit IC4 is input from the relay substrate AK and the data signal D1 is input, and drives the lamp circuit substrate 25. It outputs to the circuit 50. Similarly, when the data signal D2 is input when the chip select signal designating the integrated circuit IC4 is input from the relay substrate AK, the integrated circuit IC4 generates the common signal COM3, and the driving circuit for the lamp circuit substrate 25 50 is output. Similarly, the integrated circuit IC4 generates the common signal COM4 when the chip select signal designating the integrated circuit IC4 is input from the relay substrate AK, and generates the common signal COM4, and the driving circuit for the ramp circuit substrate 25 50 is output.

  The chip select signal is a signal for designating which of the plurality of integrated circuits IC4 to IC6, IC8, and IC9 included in the drive substrate 41 is outputting a data signal. The chip select signal is generated based on a control signal input from the overall control board 31 by a decoder circuit included in the relay board AK.

  Further, the integrated circuit IC5 is configured to input data signals D0 to D7 of a plurality of predetermined types (eight types in the present embodiment) among a plurality of types of control signals to be input. The integrated circuit IC5 generates the segment signal ASEGa and inputs the ramp circuit at a predetermined timing when the data signal D0 is input when the chip select signal designating the integrated circuit IC5 is input from the relay substrate AK. The signal is output to the drive circuit 50 of the substrate 25. Further, the integrated circuit IC5 generates a segment signal ASEGb when the chip select signal designating the integrated circuit IC5 is input from the relay substrate AK, and generates the segment signal ASEGb, and the ramp circuit substrate 25 at a predetermined timing. Is output to the driving circuit 50. Similarly, when the data signal D2 is input when the chip select signal designating the integrated circuit IC5 is input from the relay substrate AK, the integrated circuit IC5 generates the segment signal ASEGc and drives the drive circuit 50 at a predetermined timing. To output. Similarly, when the data signal D3 is input when the chip select signal designating the integrated circuit IC5 is input from the relay substrate AK, the integrated circuit IC5 generates the segment signal ASEGd, and drives the drive circuit 50 at a predetermined timing. To output. Similarly, the integrated circuit IC5 generates the segment signal ASEGe when the chip select signal designating the integrated circuit IC5 is input from the relay substrate AK, and generates the segment signal ASEGe, and the drive circuit 50 at a predetermined timing. To output. Similarly, the integrated circuit IC5 generates the segment signal ASEGf when the chip select signal designating the integrated circuit IC5 is input from the relay substrate AK, and generates the segment signal ASEGf, and the drive circuit 50 at a predetermined timing. To output. Similarly, the integrated circuit IC5 generates the segment signal ASEGg when the chip select signal designating the integrated circuit IC5 is input from the relay substrate AK, and generates the segment signal ASEGg, and the drive circuit 50 at a predetermined timing. To output. Similarly, the integrated circuit IC5 generates the segment signal ASEGh when the chip select signal designating the integrated circuit IC5 is input from the relay board AK, and generates the segment signal ASEGh, and the drive circuit 50 at a predetermined timing. To output.

  Similarly, the integrated circuit IC6 is configured to input data signals D0 to D7 determined in advance (eight types in the present embodiment) from among a plurality of types of control signals to be input. Then, the integrated circuit IC6 generates the segment signal ASEGi when the chip select signal designating the integrated circuit IC6 is input from the relay board AK, and generates the segment signal ASEGi at a predetermined timing. Output to 50. Further, when the data signal D1 is inputted when the chip select signal designating the integrated circuit IC6 is inputted, the integrated circuit IC6 generates the segment signal ASEGj and outputs it to the drive circuit 50 at a predetermined timing. Similarly, when the data signal D2 is input when the chip select signal designating the integrated circuit IC5 is input from the relay substrate AK, the integrated circuit IC5 generates the segment signal ASEGk, and drives the drive circuit 50 at a predetermined timing. To output. Similarly, when the data signal D3 is input when the chip select signal designating the integrated circuit IC6 is input from the relay board AK, the integrated circuit IC6 generates the segment signal ASEGl and drives the drive circuit 50 at a predetermined timing. To output. Similarly, the integrated circuit IC6 generates the segment signal ASEGm when the chip select signal designating the integrated circuit IC6 is input from the relay board AK, and generates the segment signal ASEGm, and the drive circuit 50 at a predetermined timing. To output. Similarly, when the data signal D5 is input when the chip select signal designating the integrated circuit IC6 is input from the relay substrate AK, the integrated circuit IC6 generates the segment signal ASEGn, and drives the drive circuit 50 at a predetermined timing. To output. Similarly, when the data signal D6 is input when the chip select signal designating the integrated circuit IC6 is input from the relay substrate AK, the integrated circuit IC6 generates the segment signal ASEGO and drives the drive circuit 50 at a predetermined timing. To output. Similarly, the integrated circuit IC6 generates the segment signal ASEGp when the chip select signal designating the integrated circuit IC6 is input from the relay board AK, and generates the segment signal ASEGp at a predetermined timing. To output.

  Similarly, the integrated circuit IC8 is configured to input data signals D0 to D7 determined in advance (eight types in the present embodiment) from among a plurality of types of control signals to be input. Then, the integrated circuit IC8 generates the segment signal BSEGa when receiving the data signal D0 when the chip select signal designating the integrated circuit IC8 is input from the relay substrate AK, and the drive circuit at a predetermined timing. 50 is output. Further, the integrated circuit IC8 generates the segment signal BSEGb when the chip select signal designating the integrated circuit IC8 is input from the relay substrate AK, and generates the segment signal BSEGb, and sends it to the drive circuit 50 at a predetermined timing. It is designed to output. Similarly, the integrated circuit IC8 generates the segment signal BSEGc when the chip select signal designating the integrated circuit IC8 is input from the relay substrate AK, and generates the segment signal BSEGc, and the drive circuit 50 at a predetermined timing. To output. Similarly, the integrated circuit IC8 generates the segment signal BSEGd when the chip select signal designating the integrated circuit IC8 is input from the relay substrate AK, and generates the segment signal BSEGd, and the drive circuit 50 at a predetermined timing. To output. Similarly, the integrated circuit IC8 generates the segment signal BSEGe when the chip select signal designating the integrated circuit IC8 is input from the relay substrate AK, and generates the segment signal BSEGe, and the drive circuit 50 at a predetermined timing. To output. Similarly, the integrated circuit IC8 generates the segment signal BSEGf when the chip select signal designating the integrated circuit IC8 is input from the relay substrate AK, and generates the segment signal BSEGf, and the drive circuit 50 at a predetermined timing. To output. Similarly, the integrated circuit IC8 generates the segment signal BSEGg when the chip select signal designating the integrated circuit IC8 is input from the relay substrate AK, and generates the segment signal BSEGg, and the drive circuit 50 at a predetermined timing. To output. Similarly, the integrated circuit IC8 generates the segment signal BSEGh when the chip select signal designating the integrated circuit IC8 is input from the relay substrate AK, and generates the segment signal BSEGh, and the drive circuit 50 at a predetermined timing. To output.

  Similarly, the integrated circuit IC9 is configured to input data signals D0 to D7 determined in advance (eight types in the present embodiment) from among a plurality of types of control signals to be input. The integrated circuit IC9 generates the segment signal BSEGi when the chip select signal designating the integrated circuit IC9 is input from the relay substrate AK, and generates the segment signal BSEGi, and the driving circuit at a predetermined timing. Output to 50. Further, when the data signal D1 is input when the chip select signal designating the integrated circuit IC9 is input, the integrated circuit IC9 generates the segment signal BSEGj and outputs it to the drive circuit 50 at a predetermined timing. Similarly, the integrated circuit IC9 generates the segment signal BSEGk when the chip select signal designating the integrated circuit IC9 is input from the relay board AK, and generates the segment signal BSEGk, and the drive circuit 50 at a predetermined timing. To output. Similarly, when the integrated circuit IC9 receives the data signal D3 when the chip select signal designating the integrated circuit IC9 is input from the relay board AK, the integrated circuit IC9 generates the segment signal BSEGl and drives the drive circuit 50 at a predetermined timing. To output. Similarly, the integrated circuit IC9 generates the segment signal BSEGm when the chip select signal designating the integrated circuit IC9 is input from the relay substrate AK, and generates the segment signal BSEGm, and the drive circuit 50 at a predetermined timing. To output. Similarly, the integrated circuit IC9 generates the segment signal BSEGn when the chip select signal designating the integrated circuit IC9 is input from the relay substrate AK, and generates the segment signal BSEGn, and the drive circuit 50 at a predetermined timing. To output. Similarly, when the data signal D6 is input when the integrated circuit IC9 receives the chip select signal designating the integrated circuit IC9 from the relay substrate AK, the integrated circuit IC9 generates the segment signal BSEGo, and drives the drive circuit 50 at a predetermined timing. To output. Similarly, the integrated circuit IC9 generates the segment signal BSEGp when receiving the data signal D7 when the chip select signal designating the integrated circuit IC9 is input from the relay substrate AK, and drives the drive circuit 50 at a predetermined timing. To output.

  Next, the drive circuit 50 of the lamp circuit board 25 will be described. The drive circuit 50 of the lamp circuit board 25 is a dynamic drive circuit for lighting each light emitting diode constituting the decorative lamp 16 by a dynamic drive method. The drive circuit 50 includes a common driver 51 to which common signals COM1 to COM4 are input, and a segment driver 52 to which 16 types of segment signals ASEGa to ASEGp and 16 types of segment signals BSEGa to BSEGp are input. Hereinafter, the drive circuit 50 will be described in detail with reference to FIG. For convenience of explanation and drawings, a part of the drive circuit 50 (the ropes 1a to 4a, 1c to 4c, 1b to 4b, the ropes right lateral lamps 1d to 4d, the outer peripheral upper lamps 1e to 4e, the outer peripheral right lamp 1f -4f, lantern upper lamps 1g-4g, and lantern lower lamps 1h-4h) will be described only. In the following, the ropes 1a to 4a, 1c to 4c, 1b to 4b, the rope right lateral lamps 1d to 4d, the outer peripheral upper lamps 1e to 4e, the outer peripheral right lamps 1f to 4f, the lantern upper lamps 1g to 4g, the lantern The lower lamps 1h to 4h are simply indicated as lamps 1a to 1h, 2a to 2h, 3a to 3h, and 4a to 4h.

  The common driver 51 of the drive circuit 50 includes a plurality (four in this embodiment) of pnp transistors TR1 to TR4. The emitter sides of the pnp transistors TR1 to TR4 are connected to the positive terminal of the power supply VB, and the drive substrate 41 is connected to the base side so that common signals COM1 to COM4 are input. Common lines CL1 to CL4 as scanning lines are connected to the collector sides of the pnp transistors TR1 to TR4, respectively. Accordingly, the pnp transistors TR1 to TR4 are switched from off to on when the common signals COM1 to COM4 are input (the common signals COM1 to COM4 are changed to H level (high level, hereinafter the same)), and are connected to the collector side. The power supply voltage V2 (24V in this embodiment) of the power supply is applied to each of the common lines CL1 to CL4. The common lines CL1 to CL4 are connected to the first output terminal P1 to the fourth output terminal P4, respectively.

Next, the segment driver 52 will be described. The segment driver 52 includes npn transistors TR11 to TR18.
The collector side of the npn transistor TR11 is connected to a signal line SL1 as a signal line. The emitter side of the npn transistor TR11 is connected to the ground terminal, and the base side is connected to the drive substrate 41 so that the segment signal ASEGa is input. Similarly, the collector sides of the npn transistors TR12 to TR18 are connected to signal lines SL2 to SL8 as signal lines, respectively. The emitter sides of the npn transistors TR12 to TR18 are connected to the ground terminal, the base side is connected to the drive substrate 41, and the segment signals ASEGb to ASEGh are input thereto. Therefore, when the segment signals ASEGa to ASEGh are input (the segment signals ASEGa to ASEGh become H level), the npn transistors TR11 to TR18 are switched from off to on, and the signal lines SL1 to SL8 connected to the collector side are connected. It will be grounded to the ground terminal. The signal lines SL1 to SL8 are connected to the eleventh output terminal P11 to the eighteenth output terminal P18, respectively.

  Accordingly, the common lines CL1 to CL4 are scanning lines to which power supply voltage is supplied, and the signal lines SL1 to SL8 are signal lines that are grounded to the ground terminal. The pnp transistors TR1 to TR4 are switching elements (first switching elements) that are turned on / off by the input of the common signals COM1 to COM4, and the npn transistors TR11 to TR18 are turned on by the input of the segment signals ASEGa to ASEGh. A switching element (second switching element) that switches off. The light emitting diodes LED1a to 1h, 2a to 2h, 3a to 3h, and 4a to 4h are light emitting elements that emit light due to a potential difference generated between the scanning line and the signal line. Further, since the common signals COM1 to COM4 are input to the pnp transistors TR1 to TR4, they become the first signal, and the segment signals ASEGA to ASEGh are input to the npn transistors TR11 to TR18, so that they become the second signal. . The common driver 51 serves as a first output driver, and the segment driver 52 serves as a second output driver.

Next, the connection mode of the drive circuit 50 and the lamps 1a to 1h, 2a to 2h, 3a to 3h, 4a to 4h will be described.
The first output terminal P1 to the fourth output terminal P4 of the common driver 51 are connected to the lamps 1a to 1h, 2a in order to drive the lamps 1a to 1h, 2a to 2h, 3a to 3h, 4a to 4h by a dynamic driving method. A plurality of anode side connection terminals of ˜2h, 3a to 3h, and 4a to 4h are respectively connected.

  More specifically, the anode side connection terminals of the lamps 1a to 1h are connected to the first output terminal P1 connected to the common line CL1. Connection terminals on the anode side of the lamps 2a to 2h are connected to the second output terminal P2 connected to the common line CL2. Connection terminals on the anode side of the lamps 3a to 3h are connected to the third output terminal P3 connected to the common line CL3. Connection terminals on the anode side of the lamps 4a to 4h are connected to the fourth output terminal P4 connected to the common line CL4.

  The eleventh output terminal P11 to the eighteenth output terminal P18 of the segment driver 52 are configured to drive the lamps 1a to 1h, 2a to 2h, 3a to 3h, and 4a to 4h of the decorative lamp 16 by a dynamic driving method. A plurality of cathode side connection terminals of lamps 1a to 1h, 2a to 2h, 3a to 3h, and 4a to 4h are connected to each other.

  More specifically, the eleventh output terminal P11 connected to the signal line SL1 is connected to the cathode side connection terminals of the lamps 1a to 4a via the resistor R11. The connection terminals on the cathode side of the lamps 1b to 4b are connected to the twelfth output terminal P12 connected to the signal line SL2 via the resistor R12. The cathode-side connection terminals of the lamps 1c to 4c are connected to the thirteenth output terminal P13 connected to the signal line SL3 via a resistor R13. A connection terminal on the cathode side of the lamps 1d to 4d is connected to the fourteenth output terminal P14 connected to the signal line SL4 via a resistor R14. Connection terminals on the cathode side of the lamps 1e to 4e are connected to the fifteenth output terminal P15 connected to the signal line SL5 via a resistor R15. The 16th output terminal P16 connected to the signal line SL6 is connected to the cathode side connection terminals of the lamps 1f to 4f via the resistor R16. The cathode-side connection terminals of the lamps 1g to 4g are connected to the seventeenth output terminal P17 connected to the signal line SL7 via a resistor R17. Connection terminals on the cathode side of the lamps 1h to 4h are connected to the eighteenth output terminal P18 connected to the signal line SL8 via a resistor R18.

  Next, the operation of the drive circuit 50 when the lamps 1a to 1h, 2a to 2h, 3a to 3h, 4a to 4h are turned on will be described with reference to FIG. FIG. 9 shows the light emission timing of the common signal and the segment signal when the lamp 1a is caused to emit light.

  The drive board 41 that has received a control signal from the overall control board 31 sequentially outputs various signals to the drive circuit 50 based on the control signal. More specifically, when a control signal is input from the overall control board 31, the driving board 41 sequentially selects the common signals COM1 to COM4 in one direction from the pnp transistors TR1 to TR4 in a certain period (horizontal). (Scanning period) is output (the common signals COM1 to COM4 are set to the H level). Therefore, the power supply voltage V2 is applied to the common lines CL1 to CL4 alternately and sequentially in one direction for a certain period. Then, within each horizontal scanning period, the drive substrate 41 sets the segment signals ASEGA to ASEGh for causing the desired lamps 1a to 1h, 2a to 2h, 3a to 3h, and 4a to 4h to emit light based on the control signal to H level. To do. In addition, the drive board 41 of this embodiment switches and outputs each common signal COM1-COM4 for every 2 ms based on a control signal. Further, the drive board 41 outputs 1.5 ms at a time when outputting each of the common signals COM1 to COM4.

  As a result, the npn-type lamps 1a to 1h, 2a to 2h, 3a to 3h, and 4a to 4h of the common lines CL1 to CL4 to which the power supply voltage V2 is applied, in which the segment signals ASEGa to ASEGh are set to the H level. Lamps 1a to 1h, 2a to 2h, 3a to 3h, and 4a to 4h connected to the transistors TR11 to TR18 via signal lines SL1 to SL8 emit light. That is, the drive board 41 is configured such that the lamps specified by the common signals COM1 to COM4 and the segment signals ASEGa to ASEGh (the common signals COM1 to COM4 and the segment signals ASEGa to ASEGh are output simultaneously) are lit. . Thereby, desired lamps 1a-1h, 2a-2h, 3a-3h, 4a-4h can be made to emit light. In addition, lamps 1i-1p, 2i-2p, 3i-3p, 4i-4p, 5a-5p, 6a-6p, 7a-7p, 8a other than lamps 1a-1h, 2a-2h, 3a-3h, 4a-4h The drive circuit for emitting ~ 8p also has the same configuration.

  In the present embodiment, the lamp circuit board 25 is provided with a discharge circuit 55 for discharging charges accumulated in the common lines CL1 to CL4. The discharge circuit 55 is connected to each of the common lines CL1 to CL4. By inputting a discharge signal from the drive substrate 41, the common lines CL1 to CL4 are grounded to the ground terminal so as to discharge the accumulated charges. It is configured. The general CPU 31a outputs a discharge signal until a predetermined time elapses after the voltage is applied before the voltage is applied to the common lines CL1 to CL4. Thus, by applying a voltage to the common lines CL1 to CL4 during discharging, the ON / OFF switching of the transistors is accelerated, and the voltage can be quickly applied to the common lines CL1 to CL4. Further, the overall CPU 31a outputs a discharge signal and discharges it every switching period (2 ms) of the common signals COM1 to COM4. By discharging in this way, erroneous lighting of the light emitting diode due to the accumulated charge can be prevented, and flickering can be prevented.

  As described above, in the present embodiment, the lamp circuit board 25 including the decorative lamp 16 and the drive circuit 50 serves as the light emitting means and the effect light emitting means. The main control board 30 and the overall control board 31 serve as main control means for controlling the pachinko machine 10. The drive board 41 and the relay board AK serve as effect control means.

  Next, it is confirmed whether or not the data signal is normally output from the overall control board 31 to the drive board 41, and whether the integrated circuits IC4 to IC6, IC8, and IC9 constituting the drive board 41 are operating normally. A method for confirming whether the operation is negative will be described.

  First, the gaming machine confirmation system 70 will be described. When the operation is confirmed, a confirmation lamp circuit board 71 is connected to the drive board 41 as shown in FIG. The confirmation lamp circuit board 71 includes a confirmation drive circuit 72 and confirmation lamps 101a to 101p, 102a to 102p, 103a to 103p, and 104a to 104p. The confirmation drive circuit 72 has the same circuit configuration as the drive circuit 50 provided on the lamp circuit board 25.

  The confirmation lamps 101a to 101p, 102a to 102p, 103a to 103p, and 104a to 104p correspond to the lamps 1a to 1p, 2a to 2p, 3a to 3p, and 4a to 4p constituting the decorative lamp 16, respectively. The confirmation lamps 101a to 101p, 102a to 102p, 103a to 103p, and 104a to 104p are arranged in a matrix.

  Specifically, in FIG. 11, the light emitting diodes are arranged so that four horizontal lines (four rows) correspond to common lines and vertical lines (8 columns × 4) correspond to signal lines. For this reason, when all the light emitting diodes in the horizontal line are not lit, it is understood that there is some abnormality in the common signal corresponding to the line. Further, when all the light emitting diodes in the vertical line are not lit, there is a possibility that there is some abnormality in the segment signal corresponding to the line. Further, the blocks are divided for each integrated circuit that outputs the segment signal. In this embodiment, the light emitting diodes are classified into four blocks so as to correspond to the integrated circuits IC5, IC6, IC8, and IC9. For this reason, when all the light emitting diodes of the entire block are not lit, it is considered that there is an abnormality in the integrated circuits IC5, IC6, IC8, and IC9 corresponding to the non-lit block.

  Further, the confirmation lamp circuit board 71 is provided with a discharge circuit 74 for discharging the charges accumulated in the common lines CL1 to CL4 of the confirmation drive circuit 72. The discharge circuit 74 is connected to each of the common lines CL1 to CL4 of the confirmation drive circuit 72. By inputting a discharge signal from the drive substrate 41, each of the common lines CL1 to CL4 of the confirmation drive circuit 72 is connected to the ground terminal. It is configured to discharge the electric charge accumulated by grounding.

  The overall control board 31 is connected to a test command transmitter 75 that can output a control signal when confirming the operation. A test command is output from the test command transmitter 75 to the overall control board 31.

As described above, in this embodiment, the confirmation lamp circuit board 71 serves as the light emitting means and the inspection light emitting means.
Next, a control method for confirming the operation will be described.

  When the overall CPU 31a of the overall control board 31 receives a test command, it outputs predetermined control signals in order based on the light emission control program stored in the ROM 31b. More specifically, when the overall CPU 31a of the overall control board 31 inputs a test command, first, a discharge signal for discharging the charges accumulated in the common lines CL1 to CL4 of the confirmation drive circuit 72 is transmitted to the relay board AK and the drive. Output to the discharge circuit via the substrate 41. As shown in FIG. 9, the general CPU 31a outputs a discharge signal from before the voltage is applied to the common lines CL1 to CL4 of the confirmation drive circuit 72 until a predetermined time elapses after the voltage is applied. It has become. As described above, by applying the voltage to the common lines CL1 to CL4 during the discharge, the ON / OFF switching of the transistors is accelerated, and the voltage can be quickly applied to the common lines CL1 to CL4. The general CPU 31a outputs a discharge signal every 2 ms to discharge. Below, since it is the same, description about the output timing of a discharge signal is abbreviate | omitted.

  Next, the overall CPU 31a outputs a control signal that causes the relay substrate AK to output a chip select signal designating the integrated circuit IC5. As a result, when the control signal is input, the relay board AK generates a chip select signal designating the integrated circuit IC5 and outputs the chip select signal to the drive board 41. Further, the general CPU 31a is configured such that when the integrated circuit IC5 is designated by the chip select signal and the common signal COM1 is output from the drive substrate 41, the data signal D4 is input to the integrated circuit IC5. Data signal D4 is output to relay substrate AK (data signal D4 is set to H level).

  When the data signal D4 is input to the drive board 41 via the relay board AK, the integrated circuit IC5 is designated by the chip select signal, and thus the integrated circuit IC5 inputs the data signal D4. Then, as shown in FIG. 12, the integrated circuit IC5 outputs the segment signal ASEGe generated based on the data signal D4 while the common signal COM1 is output from the integrated circuit IC4 (for 1.5 ms) (time point T1). ).

  Thereby, the drive substrate 41 outputs the segment signal ASEGe to the confirmation lamp circuit substrate 71 when the common signal COM1 is output. When the common signal COM1 and the segment signal ASEGe are input to the confirmation drive circuit 72 of the confirmation lamp circuit board 71, the confirmation lamp 101e corresponding to the common signal COM1 and the lamp 1e specified by the segment signal ASEGe is obtained. Illuminated. However, if the data signals D0 and D4 are not normally input from the overall control board 31 to the relay board AK and the drive board 41, or if there is a malfunction in the integrated circuit IC4 that outputs the common signal COM1, or the segment signal ASEGe is If the output integrated circuit IC5 has a problem, the confirmation lamp 101e is not turned on. In the present embodiment, the time from the start of the discharge signal output to the end of the output of the common signal COM1 is 2 ms.

  Then, the overall CPU 31a outputs a control signal so that the common signal COM1 and the segment signal ASEGe are repeatedly output to the check lamp circuit board 71 every 1.5 ms for 200 ms every 8 ms. As a result, if there is no abnormality, the confirmation lamp 101e blinks every 8 ms, but it appears to be continuously lit by human eyes due to an afterimage.

  After completing the lighting of the confirmation lamp 101e for 200 ms, the overall CPU 31a outputs a control signal for outputting a chip select signal designating the integrated circuit IC6 to the relay substrate AK. As a result, when the control signal is input, the relay board AK generates a chip select signal designating the integrated circuit IC 6 and outputs the chip select signal to the drive board 41.

  Further, the integrated CPU 31a is configured such that when the integrated circuit IC6 is designated by the chip select signal and the common signal COM2 is output from the drive substrate 41, the data signal D5 is input to the integrated circuit IC6. Data signal D5 is output to relay substrate AK (data signal D5 is set to H level).

  When the data signal D5 is input to the drive board 41 via the relay board AK, the integrated circuit IC6 is specified by the chip select signal, and thus the integrated circuit IC6 inputs the data signal D5. Then, as shown in FIG. 13, the integrated circuit IC6 outputs the segment signal ASEGn generated based on the data signal D5 while the common signal COM2 is output from the integrated circuit IC4 (for 1.5 ms) (time point T2). ).

  Thus, the drive board 41 outputs the segment signal ASEGn to the confirmation lamp circuit board 71 when the common signal COM2 is output. When the common signal COM2 and the segment signal ASEGn are input to the confirmation drive circuit 72 of the confirmation lamp circuit board 71, the confirmation lamp 102n corresponding to the common signal COM2 and the lamp 2n specified by the segment signal ASEGn is obtained. Illuminated. However, if the data signals D1 and D5 are not normally input from the overall control board 31 to the relay board AK and the drive board 41, or if there is a malfunction in the integrated circuit IC4 that outputs the common signal COM2, or the segment signal ASEGn is When the output integrated circuit IC6 has a problem, the confirmation lamp 102n is not turned on. In the present embodiment, the time from the start of the discharge signal output to the end of the output of the common signal COM2 is 2 ms.

  Then, the overall CPU 31a outputs a control signal so that the common signal COM2 and the segment signal ASEGn are repeatedly output to the confirmation lamp circuit board 71 every 1.5 ms for 200 ms every 8 ms. Accordingly, if there is no abnormality, the confirmation lamp 102n blinks every 8 ms, but it appears to be continuously lit by human eyes due to the afterimage.

  Then, after the lighting of the confirmation lamp 102n for 200 ms is finished, the overall CPU 31a outputs a control signal for outputting a chip select signal designating the integrated circuit IC8 to the relay substrate AK. As a result, when the control signal is input, the relay board AK generates a chip select signal designating the integrated circuit IC8 and outputs it to the drive board 41.

  Further, the general CPU 31a is configured such that when the integrated circuit IC8 is designated by the chip select signal and the common signal COM3 is output from the drive substrate 41, the data signal D6 is input to the integrated circuit IC8. Data signal D6 is output to relay board AK (data signal D6 is set to H level).

  When the data signal D6 is input to the drive board 41 via the relay board AK, the integrated circuit IC8 is specified by the chip select signal, and therefore the integrated circuit IC8 inputs the data signal D6. Then, as shown in FIG. 14, the integrated circuit IC8 outputs the segment signal BSEGg generated based on the data signal D6 (time T3) while the common signal COM3 is output from the integrated circuit IC4 (for 1.5 ms). ).

  Thus, the drive board 41 outputs the segment signal BSEGg to the confirmation lamp circuit board 71 when the common signal COM3 is output. When the common signal COM3 and the segment signal BSEGg are input to the confirmation drive circuit 72 of the confirmation lamp circuit board 71, the confirmation lamp 107g corresponding to the common signal COM3 and the lamp 7g specified by the segment signal BSEGg is obtained. Illuminated. However, if the data signals D2 and D6 are not normally input from the overall control board 31 to the relay board AK and the drive board 41, or if there is a malfunction in the integrated circuit IC4 that outputs the common signal COM3, or the segment signal BSEGg is If the output integrated circuit IC8 has a problem, the confirmation lamp 107g is not turned on. In the present embodiment, the time from the start of the discharge signal output to the end of the output of the common signal COM3 is 2 ms.

  Then, the overall CPU 31a outputs a control signal so that the common signal COM3 and the segment signal BSEGg are repeatedly output to the check lamp circuit board 71 by 1.5 ms every 8 ms for 200 ms. As a result, if there is no abnormality, the confirmation lamp 107g blinks every 8 ms, but it appears to be continuously lit by human eyes due to an afterimage.

  After the lighting of the confirmation lamp 107g for 200 ms is finished, the overall CPU 31a outputs a control signal for outputting a chip select signal designating the integrated circuit IC9 to the relay board AK. As a result, when the control board receives the control signal, the relay board AK generates a chip select signal designating the integrated circuit IC9 and outputs it to the drive board 41.

  Further, the general CPU 31a is configured such that when the integrated circuit IC9 is designated by the chip select signal and the common signal COM4 is output from the drive substrate 41, the data signal D7 is input to the integrated circuit IC9. The data signal D7 is output to the relay board AK (the data signal D7 is set to H level).

  When the data signal D7 is input to the drive board 41 via the relay board AK, the integrated circuit IC9 is designated by the chip select signal, and thus the integrated circuit IC9 inputs the data signal D7. Then, as shown in FIG. 15, the integrated circuit IC9 outputs the segment signal BSEGp generated based on the data signal D7 while the common signal COM4 is output from the integrated circuit IC4 (for 1.5 ms) (time point T4). ).

  Thus, the drive board 41 outputs the segment signal BSEGp to the confirmation lamp circuit board 71 when the common signal COM4 is output. When the common signal COM4 and the segment signal BSEGp are input to the confirmation drive circuit 72 of the confirmation lamp circuit board 71, the confirmation lamp 108p corresponding to the common signal COM4 and the lamp 8p specified by the segment signal BSEGp is obtained. Illuminated. However, if the data signals D3 and D7 are not normally input from the overall control board 31 to the relay board AK and the drive board 41, or if there is a malfunction in the integrated circuit IC4 that outputs the common signal COM4, or the segment signal BSEGp is If the output integrated circuit IC9 has a problem, the confirmation lamp 108p is not turned on. In the present embodiment, the time from the start of the discharge signal output to the end of the output of the common signal COM4 is 2 ms.

  Then, the overall CPU 31a outputs a control signal so that the common signal COM4 and the segment signal BSEGp are repeatedly output to the confirmation lamp circuit board 71 every 1.5 ms for 200 ms every 8 ms. Thus, if there is no abnormality, the confirmation lamp 108p blinks every 8 ms, but it appears to be continuously lit by human eyes due to an afterimage.

  As described above, whether all the data signals D0 to D7 are normally input from the overall CPU 31a to the drive board 41 by sequentially lighting the four lamps of the confirmation lamps 101e, 102n, 107g, and 108p in order. And whether or not the integrated circuits IC4 to IC6, IC8, and IC9 are operating normally can be confirmed.

As described above in detail, the present embodiment has the following effects.
(1) Whether the control signals (data signals D0 to D7) are normally output from the overall control board 31 to the drive board 41 via the relay board AK and whether the integrated circuits IC4 to IC6, IC8, and IC9 function normally In order to confirm whether or not each of the integrated circuits IC5, IC6, IC8, and IC9, all of the eight types of segment signals generated based on the data signals D0 to D7 have been output. When all the eight types of segment signals generated based on the data signals D0 to D7 are output for each of the integrated circuits IC5, IC6, IC8, and IC9, the segments output by one integrated circuit IC5, IC6, IC8, and IC9 The lamp was lit for the number of types of signals (eight types) × the number of types of chip select signals (four types). That is, 32 confirmation lamps are turned on. For this reason, in order to check whether one confirmation lamp is lit or not, if 200 ms is spent, a total of 6400 ms, which is 32 × 200 ms, is consumed, and the efficiency for checking the operation is poor.

  Therefore, when the number of segment signals ASEGA to ASEGp and BSEGa to BSEGp is larger than the types of common signals COM1 to COM4 as in the present embodiment, the drive board 41 is provided with a confirmation lamp that is turned on when the operation is confirmed. At the time of switching, not the data signals D0 to D3 that are the generation sources of the common signals COM1 to COM4 but the unconfirmed second signal dedicated data signal D4 that is the generation source of the segment signals ASEGe to ASEGp, BSEGe to BSEGp that have not been output yet. To D7, and when there are unconfirmed data signals D0 to D3 that are generation sources of the common signals COM1 to COM4 of the types not yet output at the same time as the segment signals ASEGe to ASEGp and BSEGe to BSEGp, 2-signal dedicated data signals D4 to D7 Based generated segment signals ASEGe～ASEGp, the BSEGe～BSEGp, and to output at the output of the common signal COM1~COM4 generated based on unconfirmed data signals D0 to D3. Then, the drive board 41 inputs all kinds of chip select signals at least once, and performs the operation confirmation until the unconfirmed second signal dedicated data signals D4 to D7 and the unconfirmed data signals D0 to D3 disappear. did. That is, in this embodiment, the overall CPU 31a outputs the segment signal ASEG when outputting the common signal COM1, outputs the segment signal ASEGn when outputting the common signal COM2, and outputs the segment signal BSEGg when outputting the common signal COM3. The segment signal BSEGp was output when the common signal COM4 was output. Thus, if the lighting of the confirmation lamp is confirmed only four times, whether or not the control signals (data signals D0 to D7) are normally output from the overall control board 31 to the drive board 41, and the integrated circuit IC5, It can be confirmed whether IC6, IC8, and IC9 are functioning normally. In other words, when spending 200 ms to check whether or not one confirmation lamp is lit, the operation can be confirmed by spending a total of 800 ms of 4 × 200 ms, which greatly increases the time for confirmation. It can be shortened. This can be confirmed more efficiently as the number of lamps to be confirmed is larger than in the conventional case.

  (2) Since the confirmation lamp circuit board 71 is provided outside the pachinko machine 10, the operation can be easily confirmed. Even if the type of gaming machine is changed and the arrangement of the light emitting diodes constituting the decorative lamp 16 is changed, the arrangement of the confirmation lamps on the confirmation lamp circuit board 71 is not changed. Confirmation is easy.

  (3) Confirmation lamp The confirmation lamps on the circuit board 71 are arranged in a matrix corresponding to the common line and the signal line. For this reason, the confirmer can identify where the defect exists by confirming which confirmation lamp is not lit.

In addition, the said embodiment can be embodied in another embodiment (another example) as follows.
In the above embodiment, the number of common signals COM1 to COM4 and common lines CL1 to CL4 may be arbitrarily changed. For example, six types of common signals and common lines may be used. Similarly, the number of segment signals ASEGA to ASEGp, BSEGa to BSEGp, and signal lines SL1 to SL4 may be arbitrarily changed. For example, the number of segment signals and signal lines may be six.

  When the types of the common signal and the segment signal are changed, the drive board 41 is the time when there is an unconfirmed second signal dedicated data signal and the generation source of the common signal of the type not yet output at the same time as the segment signal. When there is no data signal, a segment signal generated based on the unconfirmed second signal dedicated data signal is output when a predetermined common signal is output.

In the above embodiment, the number of light emitting diodes constituting the decorative lamp 16 may be arbitrarily changed. For example, the number may be 32.
In the above embodiment, when the operation is confirmed, the confirmation lamp circuit board 71 is connected and the confirmation lamps 101e, 102n, 107g, and 108p are turned on for confirmation. For example, the confirmation lamp circuit board 71 may not be connected.

  In the above embodiment, the test command transmitter 75 is connected, but it may be omitted as long as the test command can be transmitted to the overall control board 31 by a switch or the like.

  In the above embodiment, the number of integrated circuits IC5, IC6, IC8, and IC9 that output segment signals ASEGA to ASEGp and BSEGa to BSEGp may be arbitrarily changed. For example, the number of integrated circuits that output segment signals may be three. Further, the number of integrated circuits IC4 that output the common signals COM1 to COM4 may be arbitrarily changed. For example, the number of integrated circuits that output common signals may be two.

In the above embodiment, the types of the data signals D0 to D7 may be arbitrarily changed. For example, six types may be used.
In the above embodiment, the drive board 41 is a data signal that is a source for generating a common signal of a type that has not been output at the same time as the segment signal when switching the confirmation lamp to be lit when checking the operation. When there are a plurality of unconfirmed data signals that are generation sources of unconfirmed segment signals, a common signal generated based on one data signal is output from the unconfirmed data signals, and at the same time, Therefore, a segment signal generated based on a data signal different from the data signal that is the generation source of the common signal that is output simultaneously may be output. At the time of operation confirmation, when switching the confirmation lamp to be lit, the drive board 41 outputs the segment signal when outputting the common signal generated based on the unconfirmed data signal when there is one unconfirmed data signal. A segment signal generated based on the unconfirmed data signal is output when the common signal is output.

  For example, the drive board 41 outputs the segment signal ASEGb when the common signal COM1 is output, and outputs the segment signal ASEGd when the common signal COM3 is output. Thereafter, the drive substrate 41 outputs a segment signal BSEGe generated based on the data signal D4 by the integrated circuit IC8 when any common signals COM1 to COM4 are output. Further, the drive substrate 41 outputs a segment signal BSEGn generated based on the data signal D5 by the integrated circuit IC9 when any common signals COM1 to COM4 are output. Then, the drive substrate 41 sequentially outputs segment signals generated based on the data signals D6 and D7 when any common signals COM1 to COM4 are output. In this way, if the lighting check is performed fewer times (6 times in this example) than the number of types (8 types) of the data signals D0 to D7, data is normally transmitted from the overall control board 31 to the drive board 41. It can be confirmed whether the signals D0 to D7 are output and whether the integrated circuits IC5, IC6, IC8, and IC9 are functioning normally. Therefore, the time for confirmation can be greatly shortened.

  In addition, when confirming the operation by the above method, the types of the common signal, the segment signal, and the chip select signal are ideal (for example, the number of types of the segment signal and the common signal is the same, and the chip select signal If the number of types is equal to or less than half of the number of types of common signals), the operation can be confirmed by checking the lighting of the lamp by half the number of types of data signals output from the overall control board 31 to the drive board 41. it can.

Next, a technical idea that can be grasped from the above embodiment and another example will be added below.
(A) When the type of the second signal is greater than the type of the first signal, the effect control unit is a data signal that is a source of the first signal when switching the light-emitting unit to be lit when confirming the operation. In addition, when there is an unconfirmed second signal dedicated data signal that is a generation source of the second signal of the type that has not yet been output, the generation source of the first signal of the type that has not yet been output at the same time as the second signal The second signal generated based on the data signal dedicated to the unconfirmed second signal is based on the data signal that is the source of the first signal of the type that has not been output at the same time as the second signal. A data signal that is output when the generated first signal is output, while there is an unconfirmed data signal dedicated to the second signal, and that is a source of generation of the first signal of the type that has not been output at the same time as the second signal. Absent In this case, the second signal generated based on the data signal dedicated to the unconfirmed second signal is configured to be output when a predetermined first signal is output, and the effect control means outputs at least all types of chip select signals. 2. The gaming machine according to claim 1, wherein operation is confirmed until the unconfirmed data signal and the unconfirmed second signal dedicated data signal are exhausted once every time.

  (B) When the type of the second signal is greater than the type of the first signal, the effect control unit is a data signal that is a generation source of the first signal when switching the light-emitting unit to be lit when confirming the operation. In addition, when there is an unconfirmed second signal dedicated data signal that is a generation source of the second signal of the type that has not yet been output, the generation source of the first signal of the type that has not yet been output at the same time as the second signal The second signal generated based on the data signal dedicated to the unconfirmed second signal is based on the data signal that is the source of the first signal of the type that has not been output at the same time as the second signal. A data signal that is output when the generated first signal is output, while there is an unconfirmed data signal dedicated to the second signal, and that is a source of generation of the first signal of the type that has not been output at the same time as the second signal. Absent In this case, the second signal generated based on the data signal dedicated to the unconfirmed second signal is configured to be output when a predetermined first signal is output, and the effect control means outputs at least all types of chip select signals. 3. The game machine confirmation system according to claim 2, wherein operation confirmation is performed until the unconfirmed data signal and the unconfirmed second signal dedicated data signal are exhausted by inputting the data once each time.

The front view which shows the machine surface side of a pachinko machine. Enlarged view of the center character. The block diagram which shows the control structure of a pachinko gaming machine. The front view which shows arrangement | positioning of a game board lamp. (A) And (b) is a front view which shows arrangement | positioning of a game board lamp. The front view which shows arrangement | positioning of a frame lamp. The block diagram which shows a drive board | substrate. The circuit diagram which shows a drive circuit and a decoration lamp. The timing chart which shows the output timing of a common signal and a segment signal. The block diagram which shows the confirmation system for game machines. The schematic diagram which shows the arrangement | sequence of the lamp for a confirmation. The timing chart which shows the output timing of a common signal and a segment signal. The timing chart which shows the output timing of a common signal and a segment signal. The timing chart which shows the output timing of a common signal and a segment signal. The timing chart which shows the output timing of a common signal and a segment signal.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 ... Pachinko machine (game machine), 16 ... Decoration lamp (light emission means, light emission means for production), 16a ... Game board lamp, 16b ... Frame lamp, 20 ... Display device, 25 ... Lamp circuit board (light emission means, production) Light emitting means), 30 ... main control board (main control means), 30a ... main CPU, 31 ... overall / lamp control board (main control means), 31a ... overall CPU, 32 ... display control board, 41 ... drive board ( Production control means), 50 ... driving circuit, 71 ... confirmation lamp circuit board, 72 ... confirmation driving circuit, 74 ... discharge circuit, 75 ... test command transmitter, 101a-101p, 102a-102p, 103a-103p, 104a to 104p: confirmation lamps (light emitting means, inspection light emitting means), AK: relay board (effect control means), C: decorative member, H: variable display, IC4, IC5, I 6, IC8, CI9 ... integrated circuit.

Claims (2)

A main control means for executing control of the gaming machine and an effect control means having a plurality of integrated circuits and causing the plurality of light emitting means to execute a light emission effect based on a control signal input from the main control means. In the gaming machine in which the effect control means sometimes turns on the light emitting means with a predetermined light emission pattern,
The light emitting means is controlled by a dynamic drive system, and a voltage is supplied to the light emitting means specified by the first signal and the second signal so that the light emitting means is turned on.
The production control unit generates and generates a first signal that switches in order for each cycle and a second signal that switches for each cycle based on a data signal that is a part of the control signal input from the main control unit. The first signal and the second signal are output to the light emitting means,
Each of the integrated circuits is configured to be capable of inputting and outputting a plurality of predetermined control signals, and inputs a chip select signal designating an integrated circuit that is a part of the control signal from the main control means, When oneself is specified by the chip select signal, a plurality of types of first signals or a plurality of types of second signals are generated based on a data signal that is a part of the control signal input from the main control unit, and the light emitting unit Is configured to output to
The main control means outputs a plurality of types of data signals to the effect control means, and outputs a chip select signal to the effect control means to switch the integrated circuit of the effect control means, thereby providing one type of data signal. Is configured so that the production control means can generate one or a plurality of types of second signals, and the generated second signal can be output to the light emitting means.
The main control means changes the chip select signal so as to switch the integrated circuit that outputs the second signal when switching the light emitting means to be lit when checking the operation, until the operation check is completed. All types of chip select signals are output at least once,
The production control means includes
When switching the light-emitting means to be lit at the time of confirming the operation, the second signal of the type that has not yet been output and is the data signal that is the generation source of the first signal of the type that has not been output at the same time as the second signal. When there are a plurality of unconfirmed data signals to be generated, the first signal generated based on one data signal is output from the unconfirmed data signals, and at the same time, the first signal is output from the unconfirmed data signals at the same time. While outputting a second signal generated based on a data signal different from the data signal from which one signal is generated,
When switching the light-emitting means to be lit when confirming the operation, if there is one unconfirmed data signal, a predetermined second signal is output when the first signal generated based on the unconfirmed data signal is output. Alternatively, the second signal generated based on the unconfirmed data signal is configured to be output when the predetermined first signal is output,
The presentation control means inputs all types of chip select signals at least once and performs operation confirmation until the unconfirmed data signal disappears. Main control means for executing control of the gaming machine, and effect control means having a plurality of integrated circuits and causing the plurality of effect light emitting means to execute the effect light emitting effects based on the control signal input from the main control means. And a light emitting device for inspection that is connected to the gaming machine at the time of confirming the operation and inputs a control signal from the effect control means, and the effect control means emits the light emitting device for inspection to a predetermined light emission at the time of confirming the operation. In the game machine confirmation system that lights up with a pattern,
The effect light-emitting means is controlled by a dynamic drive system, and a voltage is supplied to the effect light-emitting means specified by the first signal and the second signal to emit light.
The inspection light-emitting means has the same configuration as the effect light-emitting means,
The production control unit generates and generates a first signal that switches in order for each cycle and a second signal that switches for each cycle based on a data signal that is a part of the control signal input from the main control unit. The first signal and the second signal are output to the effect light-emitting means or the inspection light-emitting means,
Each of the integrated circuits is configured to be capable of inputting and outputting a plurality of predetermined control signals, and inputs a chip select signal designating an integrated circuit that is a part of the control signal from the main control means, When oneself is designated by the chip select signal, a plurality of types of first signals or a plurality of types of second signals are generated based on a data signal that is a part of the control signal input from the main control means, and the effect Configured to output to the light emitting means for inspection or the light emitting means for inspection
The main control means outputs a plurality of types of data signals to the effect control means, and outputs a chip select signal to the effect control means to switch the integrated circuit of the effect control means, thereby providing one type of data signal. 1 or a plurality of types of second signals are generated by the production control means, and the produced second signal can be output to the production light emission means or the inspection light emission means.
The main control means ends the operation confirmation by changing and outputting the chip select signal so as to switch the integrated circuit that outputs the second signal when switching the inspection light-emitting means to be lit when confirming the operation. It is configured to output all types of chip select signals at least once before
The production control means includes
When switching the inspection light-emitting means to be lit when the operation is confirmed, the second type of data signal that has not yet been output and is a data signal that is a generation source of the first signal of the type that has not been output at the same time as the second signal. When there are a plurality of unconfirmed data signals from which signals are generated, the first signal generated based on one data signal is output from the unconfirmed data signals, and at the same time, the first signal generated from the unconfirmed data signals is output simultaneously. While outputting a second signal generated based on a data signal different from the data signal from which the first signal is generated,
When switching the inspection light-emitting means to be lit when confirming the operation, if there is one unconfirmed data signal, a predetermined second signal is output when the first signal generated based on the unconfirmed data signal is output. Or a second signal generated based on the unconfirmed data signal is configured to be output when a predetermined first signal is output,
The game control system is characterized in that the effect control means inputs all kinds of chip select signals at least once and performs an operation check until the unconfirmed data signal disappears.

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