JP5114239B2 - ウェハーをパッケージングする方法 - Google Patents
ウェハーをパッケージングする方法 Download PDFInfo
- Publication number
- JP5114239B2 JP5114239B2 JP2008034468A JP2008034468A JP5114239B2 JP 5114239 B2 JP5114239 B2 JP 5114239B2 JP 2008034468 A JP2008034468 A JP 2008034468A JP 2008034468 A JP2008034468 A JP 2008034468A JP 5114239 B2 JP5114239 B2 JP 5114239B2
- Authority
- JP
- Japan
- Prior art keywords
- wafer
- packaging
- insulating layer
- layer
- exposed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05005—Structure
- H01L2224/05008—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body, e.g.
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/0502—Disposition
- H01L2224/05022—Disposition the internal layer being at least partially embedded in the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/0502—Disposition
- H01L2224/05024—Disposition the internal layer being disposed on a redistribution layer on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05147—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
- H01L2224/05572—Disposition the external layer being disposed in a recess of the surface the external layer extending out of an opening
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01022—Titanium [Ti]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01024—Chromium [Cr]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01047—Silver [Ag]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
- H01L2924/097—Glass-ceramics, e.g. devitrified glass
- H01L2924/09701—Low temperature co-fired ceramic [LTCC]
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
Description
111 貫通孔
12 テープ
13 ウェハー
131 チップ
1311 シリコーン層
1312 保護膜
1313 電極
141 第1感光性絶縁層
142 ドライフィルム
143 第2感光性絶縁層
151 シード層
16 メッキ層
17 アンダバンプメタル
18 ソルダボール
Claims (9)
- (a)複数の貫通孔が形成されたキャリアの一面にテープを付着する段階と、
(b)前記複数の貫通孔の内部の露出されている前記テープに、それぞれの一面に電極が形成された、複数のチップが一定の大きさで区画された集合体であるウェハーの前記電極が露出されるように前記複数のウェハーを付着する段階と、
(c)前記キャリアにパッケージング工程を行い前記複数のウェハーをパッケージングする段階と、
を含むことを特徴とするウェハーをパッケージングする方法。 - 前記(c)段階の以後に、
前記ウェハーをダイシングして複数のチップに分離する段階をさらに含むことを特徴と
する請求項1に記載のウェハーをパッケージングする方法。 - 前記ウェハーの一面には前記電極を選択的に露出させる保護膜が積層されており、
前記(b)段階が、前記ウェハーの他面が前記テープに付着されることを特徴とする請
求項1または請求項2に記載のウェハーをパッケージングする方法。 - 前記(c)段階が、
(c1)前記保護膜の上面に第1感光性絶縁層を積層する段階と、
(c2)前記電極の上部に位置する前記第1感光性絶縁層を露光及び現像工程により除
去する段階と、
(c3)前記電極と前記第1感光性絶縁層の一部分とにメッキ層を積層する段階と、
(c4)前記メッキ層に第2感光性絶縁層を積層する段階と、
(c5)前記第2感光性絶縁層を露光及び現像により除去して前記メッキ層の一部を露
出させる段階と、
(c6)前記露出されたメッキ層にソルダボールを実装する段階と、
を含むことを特徴とする請求項3に記載のウェハーをパッケージングする方法。 - 前記(c5)と前記(c6)との間に、前記露出されたメッキ層の上部にアンダーバン
プメタルを塗布する段階をさらに含むことを特徴とする請求項4に記載のウェハーをパッケージングする方法。 - 前記(c)段階が、
(c7)前記ウェハーの前記電極に導電性バンプを形成する段階と、
(c8)前記ウェハーの上面に第1絶縁層を積層する段階と、
(c9)前記バンプの上部をカバーする前記第1絶縁層の一部を除去する段階と、
(c10)前記バンプと前記第1絶縁層との上部にメッキ層を積層する段階と、
(c11)前記メッキ層に第2絶縁層を積層する段階と、
(c12)前記メッキ層の一部が露出されるように前記第2絶縁層を除去する段階と、
(c13)露出された前記メッキ層に表面処理層を形成する段階と、
(c14)前記表面処理層にソルダボールを実装する段階と、
を含むことを特徴とする請求項3に記載のウェハーをパッケージングする方法。 - 前記第1及び第2絶縁層が、非感光性材質であることを特徴とする請求項6に記載のウ
ェハーをパッケージングする方法。 - 前記(c7)が、電解メッキにより前記バンプを形成することを特徴とする請求項6に
記載のウェハーをパッケージングする方法。 - 前記(c7)が、無電解メッキにより前記バンプを形成することを特徴とする請求項6に
記載のウェハーをパッケージングする方法。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2007-0098379 | 2007-09-28 | ||
KR1020070098379A KR100941984B1 (ko) | 2007-09-28 | 2007-09-28 | 웨이퍼를 패키징하는 방법 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2009088467A JP2009088467A (ja) | 2009-04-23 |
JP5114239B2 true JP5114239B2 (ja) | 2013-01-09 |
Family
ID=40508839
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2008034468A Expired - Fee Related JP5114239B2 (ja) | 2007-09-28 | 2008-02-15 | ウェハーをパッケージングする方法 |
Country Status (4)
Country | Link |
---|---|
US (1) | US7736952B2 (ja) |
JP (1) | JP5114239B2 (ja) |
KR (1) | KR100941984B1 (ja) |
TW (1) | TWI368283B (ja) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101047721B1 (ko) | 2010-03-09 | 2011-07-08 | 엘지이노텍 주식회사 | 발광 소자, 발광 소자 제조방법 및 발광 소자 패키지 |
Family Cites Families (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH11307624A (ja) * | 1998-04-24 | 1999-11-05 | Fujitsu Ltd | 半導体装置用キャリア及びその製造方法 |
JP3439144B2 (ja) * | 1998-12-22 | 2003-08-25 | 三洋電機株式会社 | 半導体装置およびその製造方法 |
JP3629178B2 (ja) * | 2000-02-21 | 2005-03-16 | Necエレクトロニクス株式会社 | フリップチップ型半導体装置及びその製造方法 |
US6528393B2 (en) * | 2000-06-13 | 2003-03-04 | Advanced Semiconductor Engineering, Inc. | Method of making a semiconductor package by dicing a wafer from the backside surface thereof |
JP2002064162A (ja) * | 2000-08-21 | 2002-02-28 | Ibiden Co Ltd | 半導体チップ |
US20030114016A1 (en) * | 2001-12-18 | 2003-06-19 | Tischler Michael A. | Wafer carrier for semiconductor process tool |
JP3639265B2 (ja) * | 2002-05-28 | 2005-04-20 | 松下電器産業株式会社 | 半導体装置及びその製造方法 |
JP2004179345A (ja) * | 2002-11-26 | 2004-06-24 | Fujitsu Ltd | 半導体用基板シート材及びその製造方法、及び基板シート材を用いたモールド方法及び半導体装置の製造方法 |
KR100618543B1 (ko) * | 2004-06-15 | 2006-08-31 | 삼성전자주식회사 | 웨이퍼 레벨 적층 패키지용 칩 스케일 패키지 제조 방법 |
KR100605314B1 (ko) * | 2004-07-22 | 2006-07-28 | 삼성전자주식회사 | 재배선 보호 피막을 가지는 웨이퍼 레벨 패키지의 제조 방법 |
TWI238483B (en) * | 2004-09-01 | 2005-08-21 | Phoenix Prec Technology Corp | Semiconductor electrical connecting structure and method for fabricating the same |
JP2006151398A (ja) | 2004-11-25 | 2006-06-15 | Yamaha Corp | 半導体集積回路用梱包テープキャリア |
JP4676247B2 (ja) * | 2005-05-19 | 2011-04-27 | 株式会社ディスコ | テープ貼り機 |
JP2007073681A (ja) * | 2005-09-06 | 2007-03-22 | Renesas Technology Corp | 半導体装置およびその製造方法 |
KR100746373B1 (ko) * | 2005-12-13 | 2007-08-03 | 주식회사 실트론 | 양면 연마장치의 캐리어 플레이트 구조 |
JP2006203215A (ja) * | 2006-01-23 | 2006-08-03 | Renesas Technology Corp | 半導体集積回路装置およびその製造方法 |
US20080048310A1 (en) * | 2006-08-25 | 2008-02-28 | Phoenix Precision Technology Corporation | Carrier Board Structure Embedded with Semiconductor Component and Method for Fabricating the Carrier Board Structure |
-
2007
- 2007-09-28 KR KR1020070098379A patent/KR100941984B1/ko active IP Right Grant
- 2007-12-19 TW TW096148814A patent/TWI368283B/zh not_active IP Right Cessation
-
2008
- 2008-01-25 US US12/010,544 patent/US7736952B2/en not_active Expired - Fee Related
- 2008-02-15 JP JP2008034468A patent/JP5114239B2/ja not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JP2009088467A (ja) | 2009-04-23 |
KR20090032831A (ko) | 2009-04-01 |
US7736952B2 (en) | 2010-06-15 |
TWI368283B (en) | 2012-07-11 |
KR100941984B1 (ko) | 2010-02-11 |
TW200915444A (en) | 2009-04-01 |
US20090087950A1 (en) | 2009-04-02 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP3813402B2 (ja) | 半導体装置の製造方法 | |
TWI379394B (en) | Substrate having single patterned metal foil, and package applied with the same, and methods of manufacturing the substrate and package | |
JP3925809B2 (ja) | 半導体装置およびその製造方法 | |
US9041211B2 (en) | Semiconductor package and method for manufacturing the semiconductor package embedded with semiconductor chip | |
JP4171499B2 (ja) | 電子装置用基板およびその製造方法、並びに電子装置およびその製造方法 | |
JP2005209689A (ja) | 半導体装置及びその製造方法 | |
JP2008251702A (ja) | 配線基板の製造方法及び半導体装置の製造方法及び配線基板 | |
TWI463928B (zh) | 晶片封裝基板和結構及其製作方法 | |
JP7051508B2 (ja) | 半導体装置および半導体装置の製造方法 | |
JP5406572B2 (ja) | 電子部品内蔵配線基板及びその製造方法 | |
TW201413841A (zh) | 晶片封裝基板和結構及其製作方法 | |
JP4446772B2 (ja) | 回路装置およびその製造方法 | |
JP4170266B2 (ja) | 配線基板の製造方法 | |
JPH07201864A (ja) | 突起電極形成方法 | |
JP2004119729A (ja) | 回路装置の製造方法 | |
JP4420965B1 (ja) | 半導体装置内蔵基板の製造方法 | |
US11869844B2 (en) | Semiconductor device | |
US8062927B2 (en) | Wiring board and method of manufacturing the same, and electronic component device using the wiring board and method of manufacturing the same | |
JP5114239B2 (ja) | ウェハーをパッケージングする方法 | |
TWI599283B (zh) | 印刷電路板及其製作方法 | |
JP2004207278A (ja) | 回路装置およびその製造方法 | |
JP4631223B2 (ja) | 半導体実装体およびそれを用いた半導体装置 | |
JP4549693B2 (ja) | 配線基板の製造方法 | |
TWI399839B (zh) | 內置於半導體封裝構造之中介連接器 | |
JP2005158999A (ja) | 半導体装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20101116 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20101124 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20110223 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20110712 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20111007 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20120710 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20120910 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20121002 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20121015 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20151019 Year of fee payment: 3 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 5114239 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
LAPS | Cancellation because of no payment of annual fees |