JP5107187B2 - 電子部品パッケージの製造方法 - Google Patents

電子部品パッケージの製造方法 Download PDF

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Publication number
JP5107187B2
JP5107187B2 JP2008228204A JP2008228204A JP5107187B2 JP 5107187 B2 JP5107187 B2 JP 5107187B2 JP 2008228204 A JP2008228204 A JP 2008228204A JP 2008228204 A JP2008228204 A JP 2008228204A JP 5107187 B2 JP5107187 B2 JP 5107187B2
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JP
Japan
Prior art keywords
electronic component
support plate
recess
post
component package
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2008228204A
Other languages
English (en)
Japanese (ja)
Other versions
JP2010062430A5 (https=
JP2010062430A (ja
Inventor
秀明 坂口
昌宏 春原
光敏 東
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
Original Assignee
Shinko Electric Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Priority to JP2008228204A priority Critical patent/JP5107187B2/ja
Priority to US12/554,091 priority patent/US7897432B2/en
Publication of JP2010062430A publication Critical patent/JP2010062430A/ja
Priority to US12/979,534 priority patent/US8008120B2/en
Priority to US13/182,923 priority patent/US8183679B2/en
Publication of JP2010062430A5 publication Critical patent/JP2010062430A5/ja
Application granted granted Critical
Publication of JP5107187B2 publication Critical patent/JP5107187B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H10W74/019—Manufacture or treatment using temporary auxiliary substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
    • H10W70/614—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together the multiple chips being integrally enclosed
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7424—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self-supporting substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/093—Connecting or disconnecting other interconnections thereto or therefrom, e.g. connecting bond wires or bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/682—Shapes or dispositions thereof comprising holes having chips therein
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/9413—Dispositions of bond pads on encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/131—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed
    • H10W74/142—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed the encapsulations exposing the passive side of the semiconductor body
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/22—Configurations of stacked chips the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Piezo-Electric Or Mechanical Vibrators, Or Delay Or Filter Circuits (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
JP2008228204A 2008-09-05 2008-09-05 電子部品パッケージの製造方法 Active JP5107187B2 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2008228204A JP5107187B2 (ja) 2008-09-05 2008-09-05 電子部品パッケージの製造方法
US12/554,091 US7897432B2 (en) 2008-09-05 2009-09-04 Method for producing electronic part package
US12/979,534 US8008120B2 (en) 2008-09-05 2010-12-28 Method for producing electronic part package
US13/182,923 US8183679B2 (en) 2008-09-05 2011-07-14 Electronic part package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2008228204A JP5107187B2 (ja) 2008-09-05 2008-09-05 電子部品パッケージの製造方法

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2012153595A Division JP5458398B2 (ja) 2012-07-09 2012-07-09 電子部品パッケージの製造方法および電子部品パッケージ

Publications (3)

Publication Number Publication Date
JP2010062430A JP2010062430A (ja) 2010-03-18
JP2010062430A5 JP2010062430A5 (https=) 2011-08-25
JP5107187B2 true JP5107187B2 (ja) 2012-12-26

Family

ID=41799641

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2008228204A Active JP5107187B2 (ja) 2008-09-05 2008-09-05 電子部品パッケージの製造方法

Country Status (2)

Country Link
US (3) US7897432B2 (https=)
JP (1) JP5107187B2 (https=)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101585216B1 (ko) * 2009-10-28 2016-01-13 삼성전자주식회사 반도체 패키지, 이를 이용한 웨이퍼 스택 패키지 및 그 제조방법
KR101119306B1 (ko) * 2010-11-04 2012-03-16 삼성전기주식회사 회로기판의 제조방법
TWI446501B (zh) * 2012-01-20 2014-07-21 矽品精密工業股份有限公司 承載板、半導體封裝件及其製法
JP5458398B2 (ja) * 2012-07-09 2014-04-02 新光電気工業株式会社 電子部品パッケージの製造方法および電子部品パッケージ
US9412728B2 (en) 2012-08-03 2016-08-09 Ecole Polytechnique Federale De Lausanne (Epfl) Post-CMOS processing and 3D integration based on dry-film lithography
CN103594379B (zh) * 2012-08-14 2016-08-10 钰桥半导体股份有限公司 具有内嵌半导体以及内建定位件的连线基板及其制造方法
US8901435B2 (en) * 2012-08-14 2014-12-02 Bridge Semiconductor Corporation Hybrid wiring board with built-in stopper, interposer and build-up circuitry
US9064878B2 (en) * 2012-08-14 2015-06-23 Bridge Semiconductor Corporation Wiring board with shielding lid and shielding slots as electromagnetic shields for embedded device
US9087847B2 (en) * 2012-08-14 2015-07-21 Bridge Semiconductor Corporation Thermally enhanced interconnect substrate with embedded semiconductor device and built-in stopper and method of making the same
US9351409B2 (en) * 2013-08-06 2016-05-24 Kinsus Interconnect Technology Corp. Method of manufacturing a thin support package structure
CN105161436B (zh) * 2015-09-11 2018-05-22 柯全 倒装芯片的封装方法
CN113544829A (zh) * 2019-03-07 2021-10-22 康宁股份有限公司 用于管芯向上的扇出型封装的玻璃载体及其制造方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3980807B2 (ja) * 2000-03-27 2007-09-26 株式会社東芝 半導体装置及び半導体モジュール
US6586822B1 (en) 2000-09-08 2003-07-01 Intel Corporation Integrated core microelectronic package
JP2002313996A (ja) * 2001-04-18 2002-10-25 Toshiba Chem Corp 半導体パッケージ用基板およびその製造方法
US6701614B2 (en) * 2002-02-15 2004-03-09 Advanced Semiconductor Engineering Inc. Method for making a build-up package of a semiconductor
JP4052955B2 (ja) * 2003-02-06 2008-02-27 Ｎｅｃエレクトロニクス株式会社 半導体装置の製造方法
JP4641820B2 (ja) * 2005-02-17 2011-03-02 三洋電機株式会社 半導体装置の製造方法
JP4819471B2 (ja) * 2005-10-12 2011-11-24 日本電気株式会社 配線基板及び配線基板を用いた半導体装置並びにその製造方法
KR100923501B1 (ko) * 2007-11-13 2009-10-27 삼성전기주식회사 패키지 기판 제조방법

Also Published As

Publication number Publication date
US7897432B2 (en) 2011-03-01
US20110266697A1 (en) 2011-11-03
US20110092020A1 (en) 2011-04-21
US20100062564A1 (en) 2010-03-11
JP2010062430A (ja) 2010-03-18
US8008120B2 (en) 2011-08-30
US8183679B2 (en) 2012-05-22

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