JP5099024B2 - Epitaxial wafer manufacturing method and semiconductor device manufacturing method - Google Patents

Description

  The present invention relates to a method for manufacturing an epitaxial wafer and a method for manufacturing a semiconductor device, and more specifically to a method for manufacturing an epitaxial wafer suitable for manufacturing a semiconductor device, mainly a light receiving element and an imaging element.

  As a semiconductor substrate for forming a semiconductor device, for example, a light receiving element or an imaging element, a CZ substrate grown by the CZ method, an MCZ substrate grown by the MCZ method, and an epitaxial layer on the surface of these CZ substrate or MCZ substrate Conventionally, an epitaxial wafer or the like on which is formed is used.

By the way, since the light receiving element and the image pickup element cannot use a redundant circuit, and their electrical characteristics are very sensitive to impurity contamination, contamination control is strictly performed in the substrate manufacturing and device manufacturing processes.
For this reason, a method is generally used in which the substrate itself has a gettering capability and segregates contaminated metal elements into a gettering layer formed in a region that does not affect device characteristics.

In addition, when an epitaxial wafer is used for a light receiving element or an image pickup element, boron, arsenic, antimony, and the like are directly under the element in order to prevent diffusion of electrons and holes from the substrate side to the element region in order to improve characteristics. Increasingly, an epitaxial layer is formed after a low resistance layer is formed by ion implantation of carbon or the like and a gettering layer is formed.
However, the addition of an ion implantation process increases the chances of contamination, so contamination prevention is an important technology in this process.

On the other hand, it is difficult to measure and evaluate a minute amount of contamination. Furthermore, many evaluations require a relatively long time, and it is difficult to feed back measurement results.
Therefore, wafer lifetime measurement by SPV (surface photovoltage) method or μPCD (microwave photoconductive decay) method that can be measured in a short time is used (for example, see Non-Patent Document 1). In addition, since the measurement is destructive, only the contamination state of the device has been indirectly confirmed.

In addition, the lifetime measurement of a wafer having a diffusion layer (proximity gettering layer, diffusion current blocking layer) is generally very difficult to reliably measure, so it is rarely applied to evaluation of product wafers. It was.
Therefore, it is difficult to accurately grasp the contamination of the epitaxial wafer product itself having the diffusion layer.
Furthermore, the contamination control by the monitor sometimes cannot detect the contamination of the epitaxial wafer itself having the diffusion layer.

"Issues with Silicon Crystal / Wafer Technology" (Realize Inc., issued on January 31, 1994) pp. 265-269

  As advanced integrated circuits and image sensors have become more sophisticated and low-temperature processes have progressed, the use of epitaxial wafers with narrow gettering controllable range due to oxygen precipitation often increases the tendency of products to have poor electrical characteristics. Yes. Correspondingly, an epitaxial wafer obtained by performing epitaxial growth on a substrate on which a diffusion layer (proximity gettering layer, diffusion current blocking layer) is formed by ion implantation or the like has been used.

However, there is also a problem that the chance of contamination of the wafer increases due to the introduction of an ion implantation process involving heat treatment before and after that. It is a new technical challenge to prevent contamination in this process.
Actually, before performing ion implantation on the prepared silicon single crystal substrate, an oxide film of 200 to 300 mm (20 to 30 nm) is formed to prevent channeling or to prevent adhesion of particles, or after ion implantation, A recovery heat treatment is performed to recover the crystallinity deteriorated by the ion implantation.
However, when an epitaxial wafer is manufactured using such a technique, the wafer is contaminated by these heat treatment steps, resulting in a problem that the electrical characteristics of the device are deteriorated.

In the ion implantation process, since the silicon single crystal substrate is in contact with the disk for holding the substrate, some contamination occurs even if the disk is managed.
Further, in order to solve the problem that the charge of the implanted ions is charged up, neutralization of the charge using plasma or the like is widely performed, and therefore, the process is easily contaminated by plasma or the like.

  For example, FIG. 6A shows a lifetime map of a silicon single crystal substrate contaminated by being held by a contaminated chuck. The average lifetime of this silicon single crystal substrate was 365 μsec (maximum 546 μsec · minimum 43 μsec), and the center of the substrate was particularly low. The distribution shape of this lifetime coincides with the size and shape of the chuck. In the lifetime map in the present specification and drawings, a portion with a high lifetime is displayed brightly and a portion with a low lifetime is displayed darkly.

For comparison, FIG. 6B shows a lifetime map of a heat-treated silicon single crystal substrate without contamination. The average lifetime of the silicon single crystal substrate without contamination was 485 μsec (maximum 610 μsec, minimum 177 μsec), which was longer than that of the contaminated silicon single crystal substrate shown in FIG. That is, the silicon single crystal substrate held by the contaminated chuck has a high metal impurity concentration in the portion adsorbed and brought into contact with the chuck, and the lifetime is shortened.
Thus, it can be seen that if the chuck or disk holding the silicon single crystal substrate is contaminated, contamination of the manufactured epitaxial wafer cannot be completely prevented even if the heat treatment furnace is strictly controlled.

  In addition, although information on the impurity element type cannot be obtained, the contamination status during the heat treatment can be detected with relatively high sensitivity by measuring the wafer lifetime as described above. The wafer lifetime is also a parameter that is directly related to junction leakage, and is therefore widely used for contamination evaluation during device processes.

However, the wafer lifetime measurement requires a surface treatment for preventing minority carrier recombination on the wafer surface. For this reason, the wafer must be thermally oxidized or chemically passivated.
Therefore, since the measurement becomes a destructive measurement, it is common to indirectly evaluate the contamination state of the main apparatus using a monitor wafer. Therefore, the contamination caused in the wafer handling process as seen in FIG. 6A is often overlooked in the management of the contamination state of the apparatus.

Preventing contamination in an additional process (ion implantation process) performed to suppress gettering and diffusion current is important to achieve the original purpose of improving the electrical characteristics of the device. At the same time, it is desirable that no contamination occurs in the added process, and that even if it occurs, care should be taken to detect it and take countermeasures.
In addition, the epitaxial process including ion implantation is often performed as a foundry business. For this reason, there is a strong business need to accurately guarantee the quality of the product wafer when the process is completed. Until now, however, warranty replacement has been performed by monitoring (control data) the contamination status of diffusion furnaces and epitaxial devices. When the electrical characteristics of a device can be evaluated after a month or more, a characteristic failure estimated to be caused by contamination is sometimes confirmed, which makes the foundry business difficult.

  The present invention has been made in view of the above problems, and can produce an epitaxial wafer having an ion-implanted layer with a minimum necessary process, and at the same time, achieves both reduction in contamination and cost reduction in an added process, It is another object of the present invention to provide an epitaxial wafer manufacturing method capable of efficiently manufacturing a wafer with less contamination by evaluating and guaranteeing metal impurity contamination during manufacturing with high sensitivity.

In order to solve the above-described problems, in the present invention, at least after preparing a silicon single crystal substrate, ion implantation is performed on the main surface of the silicon single crystal substrate, cleaning is performed, and then an epitaxial layer is formed. In the epitaxial wafer manufacturing method to be performed, the ion implantation is performed by implanting at least one of boron, carbon, aluminum, arsenic, and antimony in a dose range of 1 × 10 ¹⁴ to 1 × 10 ¹⁶ atoms / cm ^2. The epitaxial layer is formed at a temperature of 1080 ° C. or higher using a single wafer epitaxial apparatus, and the metal impurity concentration of the silicon single crystal substrate at any stage after the ion implantation and before the epitaxial layer formation. Evaluation is performed, or the epitaxial layer is partially extracted after the epitaxial layer is formed. It provides a method for producing an epitaxial wafer, characterized in that to evaluate the metal impurity concentration of the silicon single crystal substrate formed with interstitial layer.

As described above, in the present invention, in order to reduce the steps that may be contaminated, the implanted ion species is at least one of boron, carbon, aluminum, arsenic, and antimony, and the dose is 1 × 10 ¹⁴ to 1 ×. The epitaxial layer is formed at a temperature of 1080 ° C. or higher by using a single-wafer epitaxial apparatus without performing a recovery heat treatment independently and at 10 ¹⁶ atoms / cm ² .
As a result, the ion implantation damage can be recovered without performing the recovery heat treatment independently, and therefore the heat treatment can be reduced as much as possible. And since the gettering capability with respect to a metal impurity is high enough, the contamination of the manufactured epitaxial wafer can be reduced as much as possible. In addition, by reducing the number of steps, it is possible to reduce the manufacturing cost of a wafer in which an epitaxial layer is formed on the ion implantation diffusion layer.

  Here, after the ion implantation and before the cleaning before the epitaxial growth, a recovery heat treatment for crystallinity recovery is performed on the silicon single crystal substrate on which the ion implantation has been performed, and in the latter half of the recovery heat treatment After the formation of the passivation oxide film, it is preferable to measure the wafer lifetime of the silicon single crystal substrate by the μPCD method as the metal impurity concentration evaluation.

As described above, by measuring the wafer lifetime by the μPCD method after the ion implantation and evaluating the level of impurity contamination in the ion implantation process, it is possible to perform cleaning and epitaxial layer formation only on a substrate having a low impurity concentration. And an epitaxial wafer having a low impurity concentration can be produced efficiently.
Then, by forming the passivation oxide film in the second half of the recovery heat treatment, the wafer lifetime can be efficiently measured by the μPCD method, so that the manufacturing time can be shortened.

Moreover, it is preferable to remove the passivation film after measuring the wafer lifetime by the μPCD method.
Thus, prior to the pre-epitaxial cleaning, by forming the epitaxial layer after removing the passivation film, metal contamination associated with wafer lifetime measurement can be avoided. Further, an epitaxial layer can be grown on the surface of the substrate where silicon is exposed, and thus an epitaxial wafer having an epitaxial layer with better crystallinity can be obtained.

  Further, the recovery heat treatment is first performed in an inert atmosphere having a nitrogen gas concentration of 97% or more, and then a thermal oxide film having a thickness of 20 nm or more is formed on the surface of the silicon single crystal substrate by switching to an oxidizing atmosphere. In addition, it is preferable that the cleaning also serves to remove the thermal oxide film.

In this way, after performing ion implantation without forming an oxide film on the wafer surface before ion implantation, in order to recover the disorder of crystallinity caused by implantation, recovery is performed, for example, by a diffusion furnace after cleaning the silicon single crystal substrate. Heat treatment is performed. This recovery heat treatment is initially performed in an atmosphere having a nitrogen gas concentration of 97% or more, and after the time necessary for the recovery of crystallinity has elapsed, an oxide film is grown to a thickness of 20 nm or more after switching to an oxidizing atmosphere. By taking out from the above, it is possible to suppress the oxidation during the crystallinity recovery heat treatment and prevent the supply of interstitial silicon, so that the disorder of the crystallinity due to the ion implantation damage can be more reliably recovered at the initial stage. In addition, by switching to an oxidizing atmosphere after crystallinity recovery and forming a thermal oxide film, this oxide film can be used as a passivation film, and measurement by the μPCD method can be performed accurately and efficiently. Can do.
Furthermore, by removing this thermal oxide film by washing, it is possible to steadily remove contaminated metal species adhering to the wafer surface during lifetime measurement, and to grow an epitaxial layer on a clean substrate surface. It is possible to more efficiently manufacture an epitaxial wafer having good properties.

  Then, after performing the passivation oxide film formation process, as a metal impurity concentration evaluation, the silicon single crystal substrate is irradiated with light on the main surface opposite to the ion-implanted surface by the μPCD method. It is preferable to measure the wafer lifetime.

  As described above, in the wafer lifetime measurement by the μPCD method, in order not to be affected by the low resistance diffusion layer, the measurement is performed by irradiating the excitation light from the surface opposite to the surface where the ion implantation is performed. Accordingly, lifetime measurement can be performed with high accuracy even on a substrate having a diffusion layer, and even a trace amount of metal contamination can be evaluated.

In addition, after the ion implantation, the disorder of crystallinity due to the ion implantation can be obtained, for example, the same effect as the recovery process using the temperature rising process or pre-baking process of the epitaxial growth process without performing the recovery heat treatment by a diffusion furnace, When such a process is used, it is not easy to perform lifetime nondestructive measurement by μPCD method of a product itself having an oxide film as a passivation film before epitaxial growth.
In such a case, after removing a part of the silicon single crystal substrate on which the epitaxial layer is formed, chemical passivation is performed, and lifetime measurement is performed by the μPCD method in the same manner as described above, or It is preferable to perform chemical passivation after removing the epitaxial layer and the ion-implanted layer by etching, and perform the wafer lifetime measurement by the μPCD method or the SPV method as the metal impurity concentration evaluation.

  In this way, by etching and removing the epitaxial layer and the ion implantation layer of the silicon single crystal substrate after the epitaxial layer formation, the wafer lifetime of the silicon single crystal substrate after the epitaxial layer formation, which could not be performed in the past, is highly accurate. It is possible to evaluate the presence / absence and level of impurity contamination of the wafer in the heat treatment for forming the epitaxial layer. In addition, it is possible to guarantee the quality of the product with high accuracy compared to a guarantee method in which contamination of the furnace is managed using a monitor wafer.

The present invention also provides a method for manufacturing a semiconductor device, characterized in that a light receiving element or an imaging element is formed in an epitaxial layer of an epitaxial wafer manufactured by any one of the above manufacturing methods.
Generally, in an epitaxial wafer in which epitaxial growth is performed after forming a diffusion layer by ion implantation, the epitaxial wafer manufacturing method of the present invention is to manufacture an epitaxial wafer effective not only for quality assurance but also for process reduction and cost reduction. Can do. In particular, this method is effective as a high-quality and low-cost mass production technique for semiconductor devices such as light receiving elements and imaging elements.

As described above, according to the present invention, in the manufacture of an epitaxial wafer having a low resistance diffusion layer by ion implantation immediately below the epitaxial layer, metal contamination that may occur due to an additional heat treatment step is set as a recovery heat treatment condition after ion implantation. By slightly changing it, it becomes possible to perform wafer lifetime measurement by the μPCD method of the production wafer in a non-destructive stage immediately before epitaxial growth, and metal contamination can be evaluated with high accuracy.
For example, the contamination state of the diffusion furnace can be reliably monitored in contrast to a method of monitoring the contamination state of the diffusion furnace every month or weekly. As a result, process contamination can be managed in real time, and it is possible to grasp the cause of the occurrence of contamination at an early stage and take countermeasures.
In addition, the lifetime of an epitaxial wafer with an embedded diffusion layer can be measured, and the contamination status of the product can be managed with higher accuracy compared to the contamination control method of an epitaxial device using a monitor. In addition, it becomes easier to pursue the cause and take countermeasures, and it becomes possible to manufacture a high-quality epitaxial wafer.

It is the process flow which showed an example of the manufacturing method of the epitaxial wafer of this invention. It is the figure which showed the lifetime map at the time of evaluating a wafer lifetime with a micro PCD method with respect to the silicon single crystal substrate which performed the recovery heat processing after ion implantation. It is the figure which showed the lifetime map of the epitaxial wafer in the experiment example of this invention. It is the figure which showed the lifetime map of the monitor epitaxial wafer in the experiment example of this invention. It is the flowchart which showed the procedure of the standard chemical passivation process. It is the figure which showed an example of the lifetime map of the contaminated silicon single crystal substrate and the uncontaminated silicon single crystal substrate. It is the process flow which showed an example of the manufacturing method of the conventional epitaxial wafer.

Hereinafter, the present invention will be described more specifically.
As described above, an epitaxial wafer having an ion-implanted layer can be manufactured with the minimum necessary process, and it is possible to achieve both reduction of contamination and cost reduction in the added process, and high sensitivity to metal impurity contamination during manufacturing. The development of a method for manufacturing an epitaxial wafer that can efficiently manufacture a wafer with little contamination by evaluating and assuring it has been awaited.

  Accordingly, the present inventors have made extensive studies on the ion implantation conditions, the epitaxial layer formation conditions, the impurity concentration measurement conditions, and the timing thereof.

For example, in the ion implantation process, the crystal structure of the silicon single crystal substrate is disturbed by the implanted ions. When the dose is increased, a locally amorphized region may be formed. Such crystal defects are likely to be a starting point for the generation of new crystal defects in subsequent processes.
Therefore, it is common to recover the crystallinity by performing annealing under appropriate conditions. As a treatment for recovering the crystallinity, a recovery heat treatment is required, and a heat treatment of about 1 hour in a diffusion furnace is generally performed. Has been done. In recent years, RTA (Rapid Thermal Annealing) has also been used, but the reality is that it is limited to processes that require a shallow diffusion layer in terms of cost.

In the manufacture of an integrated circuit that integrates image pickup devices and the like, almost 100% of an epitaxial wafer is used in order to avoid the influence of uneven dopant concentration. However, contamination during the epitaxial layer forming process performed at a high temperature becomes a problem, and the contamination state of the epitaxial device is strictly controlled.
As described above, the number of integrated circuits in an imaging system having an element structure in which ions are implanted into a substrate before epitaxial growth is increasing. For this reason, contamination control is a problem because of the increased chances of contamination.

Since the contamination control of the semiconductor substrate is performed at a level of 1 × 10 ¹⁰ to 1 × 10 ¹¹ atoms / cm ³ , there are many restrictions on the evaluation method. For this reason, not only the product itself but also the contamination state of the device is often monitored. As a result, there were occasional cases where there seemed to be problems with management accuracy.
In particular, there remains a problem in contamination control when ion implantation is performed on an epitaxial substrate.

Therefore, the present inventors have conceived that the contamination of the wafer can be accurately grasped by directly managing the contamination of the product wafer, not the contamination state of the apparatus. As a result of intensive studies, it was conceived that the impurity concentration of the silicon single crystal substrate or the epitaxial wafer is measured at any stage after the ion implantation and after the formation of the epitaxial layer.
In this case, for example, after performing a heat treatment for recovery of crystallinity on the silicon single crystal substrate after the ion implantation and before the pre-epitaxial growth cleaning, the metal is formed after the passivation film is formed during the heat treatment. As a contamination evaluation, the wafer life time of the silicon single crystal substrate is measured by the μPCD method, or the wafer life is measured by the μPCD method on the surface opposite to the surface where the ion implantation is performed on the silicon single crystal substrate after the epitaxial layer is formed. After measuring the time, etching and removing the epitaxial layer and ion implantation layer of the silicon single crystal substrate after the epitaxial layer formation, by measuring by μPCD method or SPV method, grasp the contamination state of the product itself, It is possible to accurately evaluate the metal contamination status during the manufacturing process, And finding that it is possible to remove the high silicon single crystal substrate and an epitaxial wafer of the genus impurity concentration.

  In addition, the epitaxial layer can be formed using a single-wafer epitaxial device to recover the crystallinity due to ion implantation damage almost immediately before epitaxial growth in the temperature rise and pre-bake process, compared with the case where recovery heat treatment is performed using a diffusion furnace. It has also been found that the opportunity for contamination can be reduced. In that case, a method for measuring a wafer lifetime by a μPCD method of a silicon single crystal substrate on which an epitaxial layer has been formed was also devised, and the present invention was completed.

  Hereinafter, the present invention will be described more specifically with reference to the drawings. However, the present invention is not limited to these.

First, the wafer lifetime measurement by the μPCD method and the SPV method will be briefly described.
Wafer lifetime measurement by the μPCD method evaluates metal impurities in a sample by irradiating the sample (wafer) with light and detecting the lifetime of the minority carriers generated by changes in the reflectance of the microwave. It is.
In addition, the SPV method forms a depletion layer or an inversion layer in the vicinity of the substrate surface, and intermittently irradiates monochromatic light with a bandgap energy higher than that of silicon, so that the minority carrier diffusion length and re-generation are re-established from the distribution of excess carriers. This is a method for obtaining the combined lifetime.

  FIG. 1 is a process flow showing an example of a method for producing an epitaxial wafer of the present invention. FIG. 7 shows a manufacturing flow of the epitaxial wafer, which is currently widely used, and a contamination control procedure in the manufacturing process. Hereinafter, reference will be made basically to FIG.

First, a silicon single crystal substrate is prepared.
The silicon single crystal substrate prepared at this time may be a commonly used one, for example, a slice produced from a silicon single crystal rod grown by the CZ method may be used. In addition, electrical characteristics such as conductivity type and resistivity, crystal orientation, crystal diameter, and the like can be appropriately selected so as to be suitable for the semiconductor element to be designed.

Next, ion implantation is performed on the prepared silicon single crystal substrate.
At this time, the ion species to be implanted is at least one of boron, carbon, aluminum, arsenic, and antimony, and the dose is 1 × 10 ¹⁴ to 1 × 10 ¹⁶ atoms / cm ² . For example, a large current ion implantation apparatus may be used for this ion implantation.

In this way, when the implanted ion species is at least one of boron, carbon, aluminum, arsenic, and antimony, and the dose is 1 × 10 ¹⁴ to 1 × 10 ¹⁶ atoms / cm ² , the later single wafer type It is relatively easy to sufficiently recover the ion implantation damage by the heat treatment in the epitaxial apparatus, and an epitaxial wafer having a high gettering ability for metal impurities can be obtained.
Here, when the dose amount is less than 1 × 10 ¹⁴ atoms / cm ² , the gettering ability with respect to metal impurities is low, and the metal impurity concentration cannot be sufficiently reduced. Therefore, the lower limit of the dose amount is 1 × 10 ¹⁴ atoms. / Cm ² . Further, when the dose amount is larger than 1 × 10 ¹⁶ atoms / cm ² , it becomes difficult to sufficiently recover the ion implantation damage by the subsequent heat treatment in the single wafer epitaxial apparatus, so the upper limit of the dose amount is 1 × 10 6. ¹⁶ atoms / cm ² .

Here, after the ion implantation and before the pre-epitaxial growth cleaning, the silicon single crystal substrate subjected to the ion implantation is subjected to a recovery heat treatment for crystallinity recovery, and a passivation oxide film is formed in the latter half of the process. Thereafter, the wafer lifetime of the silicon single crystal substrate can be measured by the μPCD method as the metal impurity concentration evaluation.
In this case, as described later, in wafer lifetime measurement, high sensitivity measurement can be performed by irradiating excitation light from the surface where the ion implantation layer is not formed.

  Thereby, the presence or absence of contamination in the ion implantation process can be evaluated, and a silicon single crystal substrate having a high metal contamination concentration and a silicon single crystal substrate having a low metal contamination concentration can be distinguished. Therefore, cleaning and epitaxial layer formation can be performed only on the substrate having a low metal impurity concentration. Therefore, an epitaxial wafer having a low metal impurity concentration can be manufactured efficiently, and a wasteful process can be omitted and the yield can be improved, so that the manufacturing cost can be reduced.

Further, the passivation film can be removed after the wafer lifetime measurement by the μPCD method and before the cleaning before forming the epitaxial layer.
Thereby, the metal contamination accompanying the wafer lifetime measurement can be surely removed. In addition, the surface of the silicon single crystal substrate with good crystallinity can be exposed, and thus an epitaxial layer with better crystallinity can be formed.

  Then, the recovery heat treatment is first performed in an inert atmosphere with a nitrogen gas concentration of 97% or more, and then, a thermal oxide film having a thickness of 20 nm or more is formed on the surface of the silicon single crystal substrate by switching to an oxidizing atmosphere. The cleaning described later can also serve as the removal of the thermal oxide film.

  The heat treatment performed to recover crystal defects caused by ion implantation is generally a non-oxidizing atmosphere. However, in the latter half of the recovery heat treatment, the wafer lifetime can be efficiently evaluated by oxidizing and manufacturing the silicon single crystal substrate and using it. Also, if there is no problem with the measured wafer, it is easier to grasp the contamination in other than the main process that is overlooked by passing it to the next process and making it usable as a product wafer and managing the contamination status of the equipment. .

Here, in FIG. 2A, after the ion implantation, the double heat treatment is first performed in an inert atmosphere having a nitrogen gas concentration of 97% or more as described above, and then the surface is changed to an oxidizing atmosphere and heat having a thickness of 20 nm or more on the surface. A lifetime map of a silicon single crystal substrate on which an oxide film is formed is shown. The oxide film thickness at this time is 250 mm (25 nm). The average wafer lifetime of the silicon single crystal substrate having such an oxide film thickness was 189 μsec (maximum 265 μsec, minimum 28 μsec).
For comparison, FIG. 2B shows a lifetime map of a wafer that has been subjected to double heat treatment after ion implantation and no oxide film is formed. The wafer lifetime of the silicon single crystal substrate subjected to the recovery heat treatment after the ion implantation with such an oxide film thickness is 26 μsec on average (maximum 37 μsec, minimum 9 μsec), and in order to evaluate the wafer lifetime by the μPCD method It is important to form an oxide film, and it has been found that the wafer lifetime can be easily evaluated with high sensitivity by using an oxide film formed by the method as described above.

After this essential ion implantation process and wafer lifetime measurement by an arbitrary μPCD method, oxide film etching and cleaning are performed.
An example of this cleaning is RCA cleaning. In this case, it is desirable not to perform the SC1 cleaning at a high temperature for a long time so that the ion implantation layer is not etched.

Then, using a single-wafer epitaxial apparatus, an epitaxial layer is formed on the main surface of the previously cleaned silicon single crystal substrate at a temperature of 1080 ° C. or higher, preferably 1100 ° C. or higher.
When the formation temperature of the epitaxial layer is 1080 ° C. or lower, a sufficient growth rate cannot be obtained when trichlorosilane, which is a high-purity raw material gas, is used, and defects occur in the epitaxial layer even for slight defects in the substrate. Since it becomes easy, it shall be 1080 degreeC or more.

  Here, as shown in FIG. 1B, after the epitaxial layer is formed, a part of the silicon single crystal substrate on which the epitaxial layer is formed is extracted and then subjected to chemical passivation, and then the metal impurity concentration As an evaluation, it is possible to measure the wafer lifetime of the silicon single crystal substrate by the μPCD method by irradiating light on the main surface opposite to the surface where the ion implantation is performed.

Further, as shown in FIG. 1B, after the epitaxial layer is formed, a part of the silicon single crystal substrate on which the epitaxial layer is formed is extracted, and then the epitaxial layer and the ion implantation layer are removed by etching. Chemical passivation treatment can be performed, and as a metal impurity concentration evaluation, wafer lifetime measurement by μPCD method or measurement by SPV method can be performed.
Of course, as described above, chemical passivation may be performed without removing the epitaxial layer and the buried diffusion layer by etching. Also in this case, in the wafer lifetime measurement by the μPCD method, when the above-described epitaxial layer and buried diffusion layer are removed by etching by irradiating excitation light from the side opposite to the epitaxial layer forming surface, chemical passivation is performed. Lifetime can be measured with almost the same accuracy.

Here, an example of the chemical passivation process will be briefly described with reference to FIG.
First, the silicon single crystal substrate is treated with an HF solution to remove the natural oxide film on the surface.
Thereafter, it is housed in a laminate bag, and the silicon single crystal substrate to be measured is immersed and sealed in an iodine / ethanol solution having a concentration of 5%. Thereafter, the lifetime of the silicon single crystal substrate subjected to such passivation treatment is measured.

  In the present invention, the crystal defect recovery process by ion implantation can be performed mainly by the temperature rise during epitaxial growth. When recovering the disordered crystallinity caused by ion implantation during the epitaxial layer formation process, if a wafer lifetime evaluation by μPCD method is to be performed on an ion-implanted silicon single crystal substrate before epitaxial growth, a passivation film is prepared. However, since the crystallinity is deteriorated by ion implantation, recombination cannot be suppressed and it may be difficult to perform highly sensitive measurement.

  In such a case, it will be a fracture evaluation, but it is opposite to the surface where the silicon single crystal substrate on which the epitaxial layer is formed is partially extracted and subjected to chemical passivation on the epitaxial wafer body and then ion-implanted. By performing the wafer lifetime evaluation by the μPCD method on the surface of the wafer, contamination of the epitaxial wafer can be surely grasped.

If the surface layer of the epitaxial wafer is removed by 2 to 3 μm more than the thickness of the epitaxial layer, the wafer lifetime can be measured without the influence of the ion implantation diffusion layer.
In this case, if a hydrofluoric acid / nitric acid based etching solution is used, etching can be performed in 1 or 2 minutes. As for the method of forming the passivation film, chemical passivation that facilitates the formation of the passivation film is desirable from the viewpoint of quick feedback of evaluation.

  In this way, rather than managing the contamination state of the vapor phase growth apparatus for forming the epitaxial layer, the contamination state of the product can be more accurately evaluated by evaluating the metal impurity concentration of the silicon single crystal substrate directly subjected to ion implantation. Can be grasped and managed.

  As described above with reference to specific examples, in the present invention, the metal impurity concentration of the silicon single crystal substrate or the epitaxial wafer is evaluated at any stage after the ion implantation and after the formation of the epitaxial layer. Needless to say, the timing and measuring method of the metal impurity concentration evaluation are not limited to the above-described specific examples.

  Currently, the SPV method and μPCD method, which are widely used contamination evaluation methods, are designed to reduce surface recombination after introducing a mirror silicon single crystal wafer of 5 Ω · cm or more into a heat treatment device or epitaxial device and performing a simulation heat treatment. In addition, it is necessary to perform a process of forming a passivation film on the surface of the substrate. Therefore, in most cases, the contamination state of the apparatus accompanied by the main heat treatment is managed, not the contamination control of the product itself.

  Conventionally, in the contamination management of the annealing furnace, as shown in FIG. 7, after the monitor wafer is oxidized, the wafer lifetime is measured by using the oxide film as a passivation film to manage the contamination state of the heat treatment furnace. Also in the contamination management of the epitaxial growth apparatus, the contamination state of the epitaxial apparatus is managed by epitaxially growing on a monitor wafer and performing a passivation treatment to measure the wafer lifetime, or measuring the Fe concentration and the diffusion length by the SPV method.

On the other hand, the contamination state of the product itself can be directly managed by grasping the contamination state of the wafer processed simultaneously with the product as in the present invention.
Since the actual contamination state of the product can be known efficiently, when the product wafer is contaminated, the fact can be surely grasped and a quick countermeasure can be taken. As a result, a highly clean epitaxial wafer can be obtained.

In the management of the contamination state of manufacturing equipment using monitor wafers such as conventional heat treatment furnaces and vapor phase growth furnaces, even though we can confirm that the necessary conditions for not shipping contaminated products are met, It cannot be directly confirmed that the actually manufactured epitaxial wafer is not contaminated (sufficient conditions).
In the present invention, by directly managing the contamination of a silicon single crystal substrate or an epitaxial wafer as a product, the concentration of impurities, particularly metal impurities, can be lowered, and a defective epitaxial wafer having a high impurity concentration can be shipped. Can be prevented.

  Moreover, a light receiving element and an imaging element can be formed on the epitaxial layer of the epitaxial wafer of the present invention. As described above, the epitaxial wafer manufactured and managed according to the present invention has a low impurity concentration, particularly a metal impurity concentration, and a high gettering capability. Therefore, the characteristics of the light receiving element and the imaging element are improved, and the stable yield is improved. An epitaxial wafer as a starting material effective for production can be manufactured at a low cost, and a light receiving element and an imaging element can be manufactured at a high yield and at a low cost.

  Hereinafter, although an example of an experiment is shown and the present invention is explained more concretely, the present invention is not limited to these.

(Experimental example)
First, six polished wafers grown by CZ method having a diameter of 200 mm and a resistivity of 10 Ωcm were prepared as silicon single crystal substrates.
Thereafter, arsenic ions were implanted into the prepared five silicon single crystal substrates using a high current ion implantation apparatus at 90 keV, a dose of 1 × 10 ¹⁵ atoms / cm ² , and an inclination of 0 °. The remaining one was not ion-implanted for monitoring.

Thereafter, the ion-implanted silicon single crystal substrate was washed.
Then, ion implantation damage was recovered by using a vertical diffusion furnace with respect to the silicon single crystal substrate subjected to ion implantation. At that time, air tweezers, which became a source of contamination in the past and became a problem, was transferred to a cassette for a diffusion furnace.
In a stage where nitrogen gas was introduced into a diffusion furnace at 700 ° C. in an atmosphere of 100% and heat treatment was performed at 900 ° C. for 10 minutes, the atmosphere gas was switched to 100% oxygen, heat treatment was performed for 120 minutes, and the gas was taken out from the diffusion furnace at 700 ° C. .

When the oxide film thickness was measured at this stage, the film thickness was 210 mm (21 nm). Further, the sheet resistance was measured with an eddy current measuring device, and found to be 85Ω / □.
The wafer lifetime of this silicon single crystal substrate with an oxide film was measured by the μPCD method. The measurement was performed by irradiating excitation light on the opposite side of the surface where ion implantation was performed.
The results are shown in FIG. As shown in FIG. 2 (a), it was found that ring-shaped contamination by air tweezers occurred.

  Originally, contamination has been confirmed in FIG. 2 (a). Therefore, before proceeding to the next process, the cause of contamination must be investigated and countermeasures must be taken, and the contaminated silicon single crystal substrate must be removed. I must. However, when lifetime measurement is not performed after ion implantation as in the present invention, contamination is not confirmed at this stage and is sent to the next process as it is without contamination. Therefore, in this specific example, these substrates are treated with a 5% HF solution. After removing the oxide film by immersion for 10 minutes, cleaning before epitaxial layer formation was performed by SC1 and SC2 cleaning.

Prior to the formation of the epitaxial layer, a p-type epitaxial layer having a resistivity of 10 Ωcm and a thickness of 5 μm was grown on a monitor p-type mirror wafer having a resistivity of 10 Ωcm and a diameter of 200 mm by an epitaxial apparatus to produce a monitor epitaxial wafer. The monitor wafer was subjected to a standard chemical passivation treatment with an iodine solution, and the wafer lifetime was measured. An example of the procedure of this chemical passivation process is shown in FIG.
A wafer lifetime was measured for the monitor epitaxial wafer by the μPCD method to produce a lifetime map, which is shown in FIG.
As shown in FIG. 4, the wafer lifetime was found to be a very good value of 970 μsec on average (maximum 1590 μsec and minimum 710 μsec).

  Since it was confirmed that there was no contamination by the epitaxial apparatus, a p-type epitaxial layer of 10 Ω · cm and a thickness of 5 μm was grown on the five ion-implanted wafers. Trichlorosilane was used as the silicon source, and the growth temperature was 1130 ° C.

  5 epitaxial wafers having this ion-implanted layer were etched by about 8 μm on the front and back surfaces with a hydrofluoric acid / nitric acid mixed solution to remove the ion-implanted layer and the epitaxial layer, and then subjected to chemical passivation treatment in the same manner. Measurements were made.

The average value of the average value of the lifetime in the wafer of the five wafers, the maximum and minimum average values, and a typical lifetime map are shown in FIG. The average wafer lifetime of such a wafer is 780 μsec (maximum 1370 μsec / minimum 510 μsec), and as shown in FIG. 3, there is a portion with a poor lifetime in the center of the wafer as compared with the periphery, which is contaminated with metal impurities. I found out.
Thus, it was found that even when lifetime measurement is performed after the epitaxial layer forming step, handling contamination due to air tweezers can be found.

Therefore, it was possible to confirm contamination by air tweezers in the ion implantation recovery heat treatment process, whether the wafer was subjected to recovery heat treatment after ion implantation or after the epitaxial layer was formed.
As described above, there are restrictions on the measuring apparatus and differences in the passivation method, and the absolute value of the wafer lifetime varies relatively depending on the process. However, from the in-plane distribution data of the wafer lifetime, it was found that the presence or absence of contamination of the silicon single crystal substrate and the epitaxial wafer and the contamination source in the manufacturing process can be easily grasped.
In addition, when a passivation oxide film is formed in the recovery heat treatment stage after ion implantation and the wafer lifetime is measured, the measured wafer can be passed directly to the next epitaxial process as a product, reducing measurement and manufacturing costs. I found that I can do it.

  The present invention is not limited to the above embodiment. The above-described embodiment is an exemplification, and the present invention has any configuration that has substantially the same configuration as the technical idea described in the claims of the present invention and that exhibits the same effects. Are included in the technical scope.

Claims (6)

At least after preparing a silicon single crystal substrate, ion implantation is performed on the main surface of the silicon single crystal substrate, cleaning is performed thereafter, and an epitaxial layer is formed.
The ion implantation is performed by implanting at least one of boron, carbon, aluminum, arsenic, and antimony in a dose range of 1 × 10 ¹⁴ to 1 × 10 ¹⁶ atoms / cm ² .
The formation of the epitaxial layer is performed at a temperature of 1080 ° C. or higher using a single-wafer epitaxial apparatus,
The silicon single crystal substrate in which the metal impurity concentration of the silicon single crystal substrate is evaluated at any stage after the ion implantation and before the formation of the epitaxial layer, or the epitaxial layer is formed by partial extraction after the formation of the epitaxial layer line evaluation of the metal impurity concentration Uniatari,
After the ion implantation and before the cleaning, the silicon single crystal substrate on which the ion implantation has been performed is subjected to a recovery heat treatment for crystallinity recovery, and a passivation oxide film is formed in the latter half of the recovery heat treatment. Then, a wafer lifetime of the silicon single crystal substrate is measured by μPCD method as the evaluation of the metal impurity concentration . After wafer lifetime measurement by the μPCD method, method for manufacturing an epitaxial wafer according to claim 1, characterized in that the removal of the passivation layer. The recovery heat treatment is first performed in an inert atmosphere with a nitrogen gas concentration of 97% or more, and then the thermal oxidation film having a thickness of 20 nm or more is formed on the surface of the silicon single crystal substrate by switching to an oxidizing atmosphere. 2. The method for producing an epitaxial wafer according to claim 1 , wherein the cleaning also serves to remove the thermal oxide film. After performing the passivation oxide film formation process, as a metal impurity concentration evaluation, the main surface opposite to the ion-implanted surface is irradiated with light, and the wafer of the silicon single crystal substrate is subjected to μPCD method. epitaxial wafer manufacturing method according to any one of claims 1 to 3, characterized in that for measuring the lifetime.   After extracting a part of the silicon single crystal substrate on which the epitaxial layer is formed, the epitaxial layer and the ion implantation layer are removed by etching, and then chemical passivation is performed, and the metal impurity concentration is evaluated by μPCD method. 2. The method for producing an epitaxial wafer according to claim 1, wherein a wafer lifetime measurement or an SPV method is used. The epitaxial layer of the epitaxial wafer produced by the described manufacturing method in any one of claims 1 to 5, a method of manufacturing a semiconductor device characterized by forming a light receiving element or the image pickup device.

Images