JP5089842B2 - マルチバンク、フォルトトレラント、高性能メモリアドレス指定のシステム及び方法 - Google Patents

マルチバンク、フォルトトレラント、高性能メモリアドレス指定のシステム及び方法 Download PDF

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JP5089842B2
JP5089842B2 JP2001549196A JP2001549196A JP5089842B2 JP 5089842 B2 JP5089842 B2 JP 5089842B2 JP 2001549196 A JP2001549196 A JP 2001549196A JP 2001549196 A JP2001549196 A JP 2001549196A JP 5089842 B2 JP5089842 B2 JP 5089842B2
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memory
address
memory device
bank
value
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JP2003520368A (ja
JP2003520368A5 (enExample
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グレゴリー ヴィ チュードノフスキー
ディヴィッド ヴィ チュードノフスキー
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0607—Interleaved addressing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/0292—User address space allocation, e.g. contiguous or non contiguous base addressing using tables or multilevel address translation means

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
JP2001549196A 1999-12-27 2000-12-26 マルチバンク、フォルトトレラント、高性能メモリアドレス指定のシステム及び方法 Expired - Fee Related JP5089842B2 (ja)

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US09/472,930 1999-12-27
US09/472,930 US6381669B1 (en) 1999-12-27 1999-12-27 Multi-bank, fault-tolerant, high-performance memory addressing system and method
PCT/US2000/035209 WO2001048610A1 (en) 1999-12-27 2000-12-26 Multi-bank, fault-tolerant, high-performance memory addressing system and method

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JP2003520368A JP2003520368A (ja) 2003-07-02
JP2003520368A5 JP2003520368A5 (enExample) 2008-05-15
JP5089842B2 true JP5089842B2 (ja) 2012-12-05

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JP2001549196A Expired - Fee Related JP5089842B2 (ja) 1999-12-27 2000-12-26 マルチバンク、フォルトトレラント、高性能メモリアドレス指定のシステム及び方法

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US (2) US6381669B1 (enExample)
EP (1) EP1247185A4 (enExample)
JP (1) JP5089842B2 (enExample)
KR (1) KR100781132B1 (enExample)
CN (1) CN1437728A (enExample)
AU (1) AU2455201A (enExample)
WO (1) WO2001048610A1 (enExample)

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Also Published As

Publication number Publication date
WO2001048610A8 (en) 2001-11-29
JP2003520368A (ja) 2003-07-02
US6519673B1 (en) 2003-02-11
KR100781132B1 (ko) 2007-12-03
AU2455201A (en) 2001-07-09
CN1437728A (zh) 2003-08-20
EP1247185A1 (en) 2002-10-09
KR20020079764A (ko) 2002-10-19
US6381669B1 (en) 2002-04-30
WO2001048610A1 (en) 2001-07-05
EP1247185A4 (en) 2008-01-02

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