AU2455201A - Multi-bank, fault-tolerant, high-performance memory addressing system and method - Google Patents

Multi-bank, fault-tolerant, high-performance memory addressing system and method

Info

Publication number
AU2455201A
AU2455201A AU24552/01A AU2455201A AU2455201A AU 2455201 A AU2455201 A AU 2455201A AU 24552/01 A AU24552/01 A AU 24552/01A AU 2455201 A AU2455201 A AU 2455201A AU 2455201 A AU2455201 A AU 2455201A
Authority
AU
Australia
Prior art keywords
tolerant
bank
fault
memory addressing
addressing system
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU24552/01A
Other languages
English (en)
Inventor
David V. Chudnovsky
Gregory V. Chudnovsky
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Publication of AU2455201A publication Critical patent/AU2455201A/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0607—Interleaved addressing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/0292—User address space allocation, e.g. contiguous or non contiguous base addressing using tables or multilevel address translation means

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
AU24552/01A 1999-12-27 2000-12-26 Multi-bank, fault-tolerant, high-performance memory addressing system and method Abandoned AU2455201A (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09472930 1999-12-27
US09/472,930 US6381669B1 (en) 1999-12-27 1999-12-27 Multi-bank, fault-tolerant, high-performance memory addressing system and method
PCT/US2000/035209 WO2001048610A1 (en) 1999-12-27 2000-12-26 Multi-bank, fault-tolerant, high-performance memory addressing system and method

Publications (1)

Publication Number Publication Date
AU2455201A true AU2455201A (en) 2001-07-09

Family

ID=23877479

Family Applications (1)

Application Number Title Priority Date Filing Date
AU24552/01A Abandoned AU2455201A (en) 1999-12-27 2000-12-26 Multi-bank, fault-tolerant, high-performance memory addressing system and method

Country Status (7)

Country Link
US (2) US6381669B1 (enExample)
EP (1) EP1247185A4 (enExample)
JP (1) JP5089842B2 (enExample)
KR (1) KR100781132B1 (enExample)
CN (1) CN1437728A (enExample)
AU (1) AU2455201A (enExample)
WO (1) WO2001048610A1 (enExample)

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US6791557B2 (en) * 2001-02-15 2004-09-14 Sony Corporation Two-dimensional buffer pages using bit-field addressing
US7379069B2 (en) * 2001-02-15 2008-05-27 Sony Corporation Checkerboard buffer using two-dimensional buffer pages
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US7694193B2 (en) * 2007-03-13 2010-04-06 Hewlett-Packard Development Company, L.P. Systems and methods for implementing a stride value for accessing memory
US7472038B2 (en) * 2007-04-16 2008-12-30 International Business Machines Corporation Method of predicting microprocessor lifetime reliability using architecture-level structure-aware techniques
US20100262751A1 (en) * 2009-04-09 2010-10-14 Sun Microsystems, Inc. Memory Control Unit Mapping Physical Address to DRAM Address for a Non-Power-of-Two Number of Memory Ranks Using Lower Order Physical Address Bits
US9348751B2 (en) * 2009-09-25 2016-05-24 Nvidia Corporation System and methods for distributing a power-of-two virtual memory page across a non-power-of two number of DRAM partitions
CN102035865B (zh) * 2009-09-30 2013-04-17 阿里巴巴集团控股有限公司 数据存储及数据寻址方法、系统和设备
US9268691B2 (en) 2012-06-11 2016-02-23 Intel Corporation Fast mechanism for accessing 2n±1 interleaved memory system
CN103914390B (zh) * 2013-01-06 2016-08-17 北京忆恒创源科技有限公司 存储设备
CN103399827B (zh) 2013-07-25 2015-11-25 华为技术有限公司 存储装置、执行访问操作的系统和方法
US9495291B2 (en) * 2013-09-27 2016-11-15 Qualcomm Incorporated Configurable spreading function for memory interleaving
US10268601B2 (en) 2016-06-17 2019-04-23 Massachusetts Institute Of Technology Timely randomized memory protection
US10310991B2 (en) * 2016-08-11 2019-06-04 Massachusetts Institute Of Technology Timely address space randomization
KR102540964B1 (ko) 2018-02-12 2023-06-07 삼성전자주식회사 입출력 장치의 활용도 및 성능을 조절하는 메모리 컨트롤러, 애플리케이션 프로세서 및 메모리 컨트롤러의 동작
CN110350922A (zh) * 2019-07-18 2019-10-18 南京风兴科技有限公司 一种二进制编码的寻址方法及寻址器
KR102833051B1 (ko) 2020-04-20 2025-07-11 삼성전자주식회사 메모리 모듈 및 적층형 메모리 장치
CN114385089B (zh) * 2022-03-22 2022-08-05 北京清微智能信息技术有限公司 一种基于交叉编址的动态bank存储方法、装置及电子设备

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Also Published As

Publication number Publication date
CN1437728A (zh) 2003-08-20
US6519673B1 (en) 2003-02-11
WO2001048610A8 (en) 2001-11-29
KR20020079764A (ko) 2002-10-19
KR100781132B1 (ko) 2007-12-03
WO2001048610A1 (en) 2001-07-05
JP5089842B2 (ja) 2012-12-05
US6381669B1 (en) 2002-04-30
JP2003520368A (ja) 2003-07-02
EP1247185A1 (en) 2002-10-09
EP1247185A4 (en) 2008-01-02

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Legal Events

Date Code Title Description
MK6 Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase