JP5081240B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device capable of operating a memory as a logic circuit.

  Conventionally, semiconductor devices such as LSI (Large Scale Integration) have been manufactured through many processes such as functional design, logic circuit design, wafer manufacturing, and assembly. The manufacturing process was suitable for mass production of the same product, but was not suitable for production of small quantities of many kinds of products because of the cost.

Therefore, a manufacturing technology such as FPGA (Field Programmable Gate Array) has been developed so that even if a large amount of a single semiconductor device is produced, it can be used as a separate product on the customer side. An FPGA is a semiconductor device such as an LSI that can be programmed with a logic circuit after being manufactured.
However, since the FPGA is composed of various components such as logic circuits, wirings, and switches, there is a problem that a multilayer structure of wirings in a semiconductor process and a high-level manufacturing technique are required.

As one solution, a technique for operating a memory as a logic circuit has been developed.
For example, Patent Document 1 relates to a semiconductor device that operates as a logic circuit by writing a predetermined truth value in a memory so that a plurality of memories are connected by wiring and predetermined data is output in response to a predetermined address input. Is disclosed.

Patent Document 2 discloses a technology related to a semiconductor device that operates as a logic circuit by writing truth table data to a memory such as an SRAM (Static Random Access Memory), using an address as an input, and using an output as an output value. ing.
JP 2003-149300 A JP 2003-224468 A

However, the semiconductor device of Patent Document 1 has a problem in that when the truth value of the memory is rewritten, the wiring must be reconnected.
Further, in the semiconductor device of Patent Document 2, memory cell blocks in which a plurality of memory cells that store a predetermined amount of data are collected are arranged in an array, and data from one memory cell block includes four adjacent memory cell blocks. Since it is output only to two of them (for example, right and bottom of up, down, left and right), it is difficult to operate as a logic circuit that feeds back data (returns to the original memory cell block).

  Therefore, the present invention has been made in view of the above problems, and is a memory that operates as a logic circuit. Even if the truth value of the memory is rewritten, there is no need to reconnect wiring, and data is fed back. An object of the present invention is to provide a semiconductor device that can be used.

  In order to solve the above problems, the present invention is a semiconductor device having a plurality of memory cell blocks each including a plurality of memory cells for storing a predetermined amount of data. Each memory cell block has four or more inputs and outputs, and internally includes a read address decoder for the memory cells and a sense amplifier that amplifies the voltage when output to the outside. Truth table data for outputting a desired logic value is stored in a memory cell and operates as a logic circuit. The memory cell has a read word line corresponding to the read address decoder. When the voltage of the read word line is applied, the data held at that time is read from the read data line. The memory cell blocks are connected such that four or more outputs from one memory cell block are input to the other four or more memory cell blocks via a sense amplifier.

  According to the present invention, it is possible to provide a semiconductor device that is a memory that operates as a logic circuit, does not need to be connected again even if the truth value of the memory is rewritten, and can return data.

It is a block diagram of a semiconductor device and an information processing device. FIG. 2 is a configuration diagram of a memory cell that is a storage element configuring the semiconductor device of FIG. 1. It is a block diagram of a memory cell block. It is the figure which showed the connection condition of the read-out port in a semiconductor device. It is an internal structure figure of a semiconductor device. It is a structural example of a 3-bit adder. (A) is a simplified diagram of the memory cell block 300, and (b) is a truth table stored in the memory cell blocks 300d, 300e, and 300f. (A) is a simplified diagram of the memory cell block 300, and (b) is a truth table stored in the memory cell blocks 300g, 300j, 300k, and 300l. (A) is a simplified diagram of the memory cell block 300, and (b) is a truth table stored in the memory cell blocks 300h and 300i. It is a figure which shows the structural example of a memory cell block in case n value is "2". 2 is a diagram illustrating a configuration example of a semiconductor device 110 when an n value is “2”. FIG. It is a figure which shows the structural example of a memory cell block in case n value is "3". It is a figure which shows the structural example of a memory cell block in case n value is "3". 6 is a diagram illustrating a configuration example of a semiconductor device 110 when an n value is “3”. FIG. It is a figure which shows the structural example of a memory cell block in case n value is "6". 3 is a diagram illustrating a configuration example of a semiconductor device 110 when an n value is “6”. FIG. It is a figure which shows the structural example of a memory cell block in case n value is "8". 3 is a diagram illustrating a configuration example of a semiconductor device 110 when an n value is “8”. FIG. It is a figure which shows the structural example of a memory cell block in case n value is "2.5". 6 is a diagram illustrating a configuration example of a semiconductor device 110 when an n value is “2.5”. FIG. It is a figure which shows the example of algebraic division. It is a table | surface which shows the magnitude comparison of the required memory capacity and the number of cells of a critical path. It is a block diagram of a tester etc. using algebraic division. It is a flowchart which shows the flow of a process when mounting the bit data for operating as a logic circuit in a semiconductor device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 Information processing device 110 Semiconductor device 200 Memory cell 201, 202 Read word line 211 Write word line 221, 222 Read data line 231, 232 Write data line 300 Memory cell block 301 Select line 311 Read address decoder 401 Write / read Circuit 601, 701, 801 Truth table 1400 Large scale memory 1900 Tester

Hereinafter, a semiconductor device according to an embodiment of the present invention will be described with reference to the drawings.
FIG. 1 is a configuration diagram of a semiconductor device and an information processing device. The information processing apparatus 100 is a computer device, and includes an input unit 101 such as a keyboard, a storage unit 102 such as a hard disk, a memory 103 such as a RAM (Random Access Memory), an output unit 104 such as a CRT (Cathode Ray Tube), and a communication device. And a processing unit 106 such as a CPU (Central Processing Unit).
The bit data created by the information processing apparatus 100 (described later in step S1204 in FIG. 18) may be held in a ROM (Read Only Memory) (not shown).

  The semiconductor device 110 is connected to the communication unit 105 of the information processing apparatus 100. The semiconductor device 110 is a storage device similar to a normal SRAM (Static Random Access Memory) in terms of hardware, and will be described in detail later with reference to FIG.

  FIG. 2 is a configuration diagram of a memory cell which is a memory element constituting the semiconductor device 110 of FIG. The memory cell 200 includes a read word line 201, a write word line 211, read data lines 221, 222, write data lines 231, 232, gates 241, 242, 261, 262, and a flip-flop 271.

  The gates 241, 242, 261, and 262 are configured by N-MOS (Negative-Metal Oxide Semiconductor), but may be configured by using P-MOS (Positive-Metal Oxide Semiconductor) instead. In addition, a composite gate of N-MOS and P-MOS may be used. In that case, what is necessary is just to respond | correspond by changing a peripheral circuit suitably as needed.

  The read word line 201 is a wiring to which a voltage is applied when data of the memory cell 200 is read from the outside. When the voltage of the read word line 201 is applied, the gates 241 and 242 are opened.

  The write word line 211 is a wiring to which a voltage is applied when data is written to the memory cell 200 from the outside. When the voltage of the write word line 211 is applied, the gate 261 and the gate 262 are opened.

  The read data lines 221 and 222 are wirings for reading data held in the flip-flop 271 when a predetermined voltage is applied to the read word line 201 and the gates 241 and 242 are opened. When data “0” is read from read data line 221, data “1” is read from read data line 222, and when data “1” is read from read data line 221, data is read. Data “0” is read out from the data line 222, so-called differential signal operation is performed.

The write data lines 231 and 232 are wirings for writing data to the flip-flop 271 when the voltage of the write word line 211 is applied and the gates 261 and 262 are opened. When data “0” is written from the write data line 231, data “1” is written from the write data line 232, and when data “1” is written from the write data line 231, data is written from the write data line 232. "0" is written.
The flip-flop 271 is a storage circuit that holds “0” or “1” data stored in the memory cell 200 in the above sense.

FIG. 3 is a configuration diagram of a part of the memory cell block in the internal structure of the semiconductor device 110 of FIG.
The memory cell block 300 includes a plurality of memory cells 200, a read address decoder 311, and two sense amplifiers 600 that are connected in an array. Note that the sense amplifier 600 is a circuit for amplifying a weak voltage output from the memory cell 200, and the current flowing between the memory cell blocks 300 is thereby stabilized. The sense amplifier 600 also serves as a read address decoder for the y address (horizontal address).

Read address decoder 311 receives a plurality of address differential signals (A0 and / A0, A1 and / A1) from address input line 322.
In the claims, “4” in the number of inputs and outputs corresponds to “4 pairs” in the case of differential signals, and is not in the case of differential signals (single (In the case of wiring) This corresponds to the meaning of “four”. The same applies to other numerical values.

  In the memory cell block 300, the outermost memory cell 200, that is, the upper side of the memory cell 200 (Cell31,0) and the memory cell 200 (Cell31,3), and the innermost memory cell 200, that is, the memory. The read data lines 221 and 222 are connected to another memory cell block 300 (not shown) via the sense amplifier 600 below the cell 200 (Cell0,1) and the memory cell 200 (Cell0,2). It is configured. The sense amplifier 600 receives y-address differential signals (A2 and / A2, A3 and / A3) from the address input line 323.

  In the memory cell block 300, the uppermost inner memory cell 200, that is, the upper side of the memory cell 200 (Cell31,1) and the memory cell 200 (Cell31,2), and the lowermost outer memory cell 200, that is, the memory. The read data lines 221 and 222 are disconnected below the cell 200 (Cell0, 0) and the memory cell 200 (Cell0, 3).

  That is, in the memory cell block 300, the read data lines are configured to output via the sense amplifier 600 with the plurality of outer pairs upward and the inner pairs downward. By doing so, the scale of output (reading) of the memory cell block 300 can be minimized, the burden of various data processing can be reduced, and a plurality of outputs can be performed in a plurality of directions. it can.

  In the memory cell block 300, information in the specific memory cell 200 can be read by input from the address input line 322, the address input line 323, and the select line (specific address selection line) 301 (SEL).

  The select line 301 is provided with an inverter 302. Further, the read address decoder 311 is provided with a plurality of logic circuits (AND circuit, NAND circuit, etc.) 370. The write word line 371 (corresponding to the write word line 211 in FIG. 2) is connected to the write address decoder 411 (see FIG. 5).

  As shown in FIG. 3, for example, when “1” is input from the select line 301, the upper half of the memory cell 200 in the memory cell block 300 operates and “0” is input from the select line 301. The lower half of the memory cell 200 in the memory cell block 300 operates.

  Therefore, for example, if the upper half of the memory cell 200 in the memory cell block 300 is set to operate as an adder and the lower half of the memory cell 200 is operated as a subtractor, only the signal from the select line 301 is switched. Instantaneous switching between adder and subtractor can be performed. The same applies to a multiplier and a divider as well as an adder and a subtracter. Further, similarly, other than that, switching between an adder and a normal storage device can be performed.

  Note that a signal input to the memory cell block 300 and a signal output from the memory cell block 300 may be a differential signal or a single signal.

  FIG. 4 is a diagram showing a connection state of the read ports (each of the two upper and lower outputs of the read data line in FIG. 3 and two inputs from the address input lines 322 and 323) in the semiconductor device 110 (see FIG. 1). 4 shows a part of the upper left when the semiconductor device 110 is viewed in plan.

  In the memory cell blocks 300d to 300l, the input A0 (hereinafter referred to as “A0”: the same applies to A1 to A3) indicates the combination of A0 and / A0 in FIG. Is the same.

In the memory cell blocks 300d to 300l, the output D0 (hereinafter referred to as “D0”: D1 to D3 is also the same) is provided with two read data lines of the memory cell 200 (Cell31,0) of FIG. This is the same for D1 to D3.
A0 to A3 and D0 to D3 of memory cell blocks 300d to 300l are connected as shown in FIG.

  The driver circuit 420 converts a signal input from an external device to the device (semiconductor device 110) into a differential signal. The amplifier 430 amplifies and converts the input differential signal into a normal signal and outputs it to an external device.

  By using such a wiring, the semiconductor device 110 can easily perform data feedback. Specifically, for example, when data is sent from D3 of the memory cell block 300d to A1 of the memory cell block 300g, the memory cell block 300g outputs a truth value to the memory cell block 300g so that data input from A1 is output from D1. If the table is written, the data can be fed back to A3 of the memory cell block 300d.

Further, the semiconductor device 110 can be operated as various logic circuits only by changing the truth table written in the memory cell blocks 300d to 300l without changing the wiring.
Note that the number and condition of such wiring bends are not particularly limited to FIG. 4 and can be changed as appropriate.

  FIG. 5 is an internal structure diagram of the semiconductor device 110 (see FIG. 1). Each memory cell block 300 is arranged in an array, a write address decoder 411 is arranged on the left side, and a write / read circuit 401 is arranged on the lower side, and they are connected as shown in the figure. That is, FIG. 5 is a diagram illustrating a state other than the connection state of the read port in the semiconductor device 110 similar to FIG.

The write address decoder 411 is a device for specifying the x address of the memory cell block 300 (the vertical address of the semiconductor device 110 in FIG. 5) when writing data to the memory cell block 300.
In the write address decoder 411, the x address for specifying which one of the plurality of memory cell blocks 300 is an upper address (in this case, A5w, A6w,... After A4w). The x address for specifying the inside (memory cell 200) of the specified memory cell block 300 is input from the lower address (A0w to A3w in this case).

The write / read circuit 401 is a device that specifies the y address of the memory cell block 300 that reads / writes data, and that reads / writes data from / to the specified memory cell block 300.
Specifically, the write / read circuit 401 has a y address (a horizontal address of the semiconductor device 110 in FIG. 5) for specifying any one of the plurality of memory cell blocks 300. ) Is input (in this case, to Ayw2), and the y address for specifying the inside (memory cell 200) of the specified memory cell block 300 is input (in this case, to Ayw0 and Ayw1). The write / read circuit 401 receives data of a plurality of bits (in this case, 4 bits) from the input 402.

In this manner, the specific memory cell 200 in the specific memory cell block 300 can be selected as appropriate, and truth table data can be rewritten.
That is, when the truth table data stored in the memory cells 200 of some of the memory cell blocks 300 among the plurality of memory cell blocks 300 is rewritten, the semiconductor device 110 follows the rewritten truth table data. You can change the behavior.

Next, an example in which the semiconductor device 110 (see FIG. 4) is used as a 3-bit adder will be described with reference to FIGS.
FIG. 6 is a configuration example of a 3-bit adder. Connections between the memory cell blocks in FIG. 6 are the same as those in FIG.

  Here, a case will be described in which 3-bit two numbers E and F are added and the result is Y. The least significant bit of E is E0, the next bit is E1, and the most significant bit is E2. The least significant bit of F is F0, the next bit is F1, and the most significant bit is F2. Further, the least significant bit of Y is Y0, the next bit is Y1, and the most significant bit is Y2. Also, the carry by adding the least significant bit is C0, the carry by adding the next bit is C1, and the carry by adding the most significant bit is C2. Although each signal is differential, it is described in a simplified manner for the sake of description.

In the memory cell block 300d, E0 is input to A0, F0 is input to A1, addition is performed, Y0 is output from D3, and C0 is output from D2.
In the memory cell block 300e, E1 is input to A0, F1 is input to A1, and C0 is input to A3. The addition is performed, Y1 is output from D3, and C1 is output from D2.
In the memory cell block 300f, E2 is input to A0, F2 is input to A1, and C1 is input to A3. The addition is performed, Y2 is output from D3, and C2 is output from D2.

Y0 output from D3 of the memory cell block 300d is output from D3 of the memory cell block 300j via a path (thick line) as shown in the figure.
Y1 output from D3 of the memory cell block 300e is output from D3 of the memory cell block 300k via a path (thick line) as shown in the figure.
Y2 output from D3 of the memory cell block 300f is output from D3 of the memory cell block 300l via a path (thick line) as shown in the figure.
In this way, Y0, Y1, and Y2 that are addition results can be obtained.

7A is a simplified diagram of the memory cell block 300, and FIG. 7B is a truth table stored in the memory cell blocks 300d, 300e, and 300f (see FIG. 6 as appropriate).
As shown in FIG. 7A, in the memory cell block 300, when there are inputs to A0 to A3, data defined in the truth table is output from D0 to D3 according to the inputs.

  As shown in FIG. 7 (b), if there are inputs E (E0 to E2), F (F0 to F2), and Cin (C0 to C2) in A0, A1 and A3, the three addition results are as follows: The bit value is output to D3 as Y (Y0 to Y2), and the carry is output to D2 as Cout (C0 to C2).

Since D0 and D1 are not used here, “0” is output in all cases.
The truth values other than A2 are the same in the 1st to 4th stages and the 5th to 8th stages from the top, but this indicates that any data of “0” or “1” is stored in A2. This is because an accurate output result can be obtained even if is input. The same applies to the 9th to 12th stages and the 13th to 16th stages.

8A is a simplified diagram of the memory cell block 300, and FIG. 8B is a truth table stored in the memory cell blocks 300g, 300j, 300k, and 300l (see FIG. 6 as appropriate).
As shown in FIG. 8A, in the memory cell block 300, when there are inputs to A0 to A3, data defined in the truth table is output from D0 to D3 according to the inputs.

As shown in FIG. 8B, when Y (Y0 to Y2) is input to A1, the value is output to D3 as it is.
Since D0 to D2 are not used here, “0” is output in all cases.

  Actually, it is only necessary to have two kinds (two levels) of truth tables from A1 to D3, “0” → “0”, “1” → “1”, but A0, A2, A3 It is a 16-level truth table so that an accurate output result can be obtained regardless of whether “0” or “1” data is input.

9A is a simplified diagram of the memory cell block 300, and FIG. 9B is a truth table stored in the memory cell blocks 300h and 300i (see FIG. 6 as appropriate).
As shown in FIG. 9A, in the memory cell block 300, when there are inputs to A0 to A3, data defined in the truth table is output from D0 to D3 according to the inputs.

As shown in FIG. 9B, when C (C0 to C2) is input to A0, the value is output to D1 as it is. Also, if Y (Y0-Y2) is input to A1, the value is output to D3 as it is.
Since D0 and D2 are not used here, “0” is output in all cases.

Further, as in the case of FIG. 8B, an accurate output result can be obtained when any data of “0” and “1” is input to A2 and A3.
In this manner, the semiconductor device 110 can be used as an adder, and can also be used as a subtracter, a multiplier, and a divider.

  Next, a configuration example of the semiconductor device 110 of this embodiment will be described with reference to FIGS. 10A to 14B (refer to other drawings as appropriate). Hereinafter, a value obtained by dividing the number of outputs from the memory cell block 300 by 2 is referred to as an “n value”. In other words, the n value represents an average value of the number of outputs from the upper and lower sides of the memory cell block 300.

  FIG. 10A is a diagram illustrating a configuration example of a memory cell block when the n value is “2”. The memory cell block 300Z includes a read address decoder 311, two sense amplifiers 600, and four memory cell mats 500Z. The memory cell mat 500Z includes 32 (8 × 4) memory cells 200. The memory cell block 300Z receives two inputs from the left and right and outputs two from the top and bottom.

  FIG. 10B is a diagram illustrating a configuration example of the semiconductor device 110 when the n value is “2”. By interconnecting the memory cell blocks 300Z in this way, each memory cell block 300Z can perform four outputs for four inputs.

  FIG. 11A is a diagram illustrating a configuration example of one memory cell block when the n value is “3”. The memory cell block 300A includes a read address decoder 311, two sense amplifiers 600, and six memory cell mats 500A. The memory cell mat 500A includes 128 (16 × 8) memory cells 200. The memory cell block 300A receives three inputs from the left and right, and outputs four from the top and two from the bottom.

  FIG. 11B is a diagram illustrating a configuration example of the other memory cell block when the n value is “3”. Memory cell block 300B includes read address decoder 311, two sense amplifiers 600, and six memory cell mats 500A. The memory cell block 300B receives three inputs from the left and right, and outputs two from the top and four from the bottom.

  FIG. 11C is a diagram illustrating a configuration example of the semiconductor device 110 when the n value is “3”. By interconnecting the memory cell blocks 300A and 300B in this way, each of the memory cell blocks 300A and 300B can perform six outputs for six inputs.

  FIG. 12A is a diagram illustrating a configuration example of a memory cell block when the n value is “6”. The memory cell block 300C includes a read address decoder 311, two sense amplifiers 600, and twelve memory cell mats 500C. The memory cell mat 500 </ b> C includes 8192 (128 × 64) memory cells 200. The memory cell block 300C receives six inputs from the left and right and outputs six from the top and bottom.

  FIG. 12B is a diagram illustrating a configuration example of the semiconductor device 110 when the n value is “6”. By interconnecting the memory cell blocks 300C in this way, each memory cell block 300C can perform 12 outputs for 12 inputs.

  FIG. 13A is a diagram illustrating a configuration example of a memory cell block when the n value is “8”. The memory cell block 300D includes a read address decoder 311, two sense amplifiers 600, and 16 memory cell mats 500D. The memory cell mat 500D includes 131072 (512 × 256) memory cells 200. The memory cell block 300D receives 8 inputs from the left and right and outputs 8 from the top and bottom.

  FIG. 13B is a diagram illustrating a configuration example of the semiconductor device 110 when the n value is “8”. By interconnecting the memory cell blocks 300D in this way, each memory cell block 300D can perform 16 outputs for 16 inputs.

  FIG. 14A is a diagram illustrating a configuration example of a memory cell block when the n value is “2.5”. The memory cell block 300E includes a read address decoder 311, two sense amplifiers 600, and five memory cell mats 500E. The memory cell mat 500E is composed of 64 (8 × 8) memory cells 200. The memory cell block 300E receives two inputs from the left and three inputs from the right, and performs three outputs from the top and two outputs from the bottom.

  FIG. 14B is a diagram illustrating a configuration example of the semiconductor device 110 when the n value is “2.5”. By interconnecting the memory cell blocks 300E in this way, each memory cell block 300E can perform five outputs for five inputs.

  The case where algebraic division is performed by the semiconductor device 110 when the n value is “2”, “2.5”, “3”, “6”, and “8” will be described with reference to FIGS. While explaining. In the semiconductor device 110 in the case where the n value is “2”, “2.5”, “3”, “6”, and “8”, similarly to the case of the adder described in FIGS. An algebraic division function can be realized. That is, in the semiconductor device 110, the truth table data may be stored in the memory cell 200 so that each memory cell block 300 outputs a value obtained by performing algebraic division on the address input as a random pattern. .

  FIG. 15 is a diagram illustrating an example of algebraic division. Here, algebraic division is different from general division satisfying the relationship of “(dividend) = (divisor) × (quotient) + (residue)”. The calculation is “1-1 = 0”, “1-0 = 1”, “0-1 = 1”, “0-0 = 0”, and is a division that does not carry up or down. As described above, algebraic division does not carry up or down, thereby simplifying the calculation and being suitable for generating a random random pattern. In the middle of the calculation, since no carry or carry is performed, for example, an operation rule of “1 + 1 = 0” may be applied instead of “1-1 = 0” (the calculation result is the same). The same applies to other calculation rules. Further, a random pattern may be generated by performing normal division instead of algebraic division.

  As shown in FIG. 15, according to such algebraic division, when the dividend “10010011010010...” Is divided by the divisor “1010”, the quotient is “0001011110001...” And the remainder is “0110”. Become.

  FIG. 16 shows the necessary memory capacity and critical path when performing algebraic division by the semiconductor device 110 when the n value is “2”, “2.5”, “3”, “6”, and “8”. It is a table | surface which shows the magnitude comparison of the number of. The number of critical paths refers to the number of memory cell blocks 300 when the longest path is taken among the memory cell blocks 300 used at the time of calculation.

As shown in FIG. 16, the necessary memory capacity is such that the n value is “2” in the semiconductor device 110 when the n value is “2”, “2.5”, “3”, “6”, and “8”. .5 ”is the minimum, and when the n value is“ 2 ”and“ 3 ”, the value is slightly larger.
On the other hand, the number of cells in the critical path is maximized when the n value is “2”, but is almost equal when the n value is other than that.
That is, when algebraic division is performed by the semiconductor device 110, the n value is “2.5” (the number of inputs / outputs in the memory cell block 300 is “5”) or “3” (the number of inputs / outputs in the memory cell block 300 is “ It can be seen that the case 6)) is efficient.

  When the area ratio of the sense amplifier 600 to the entire semiconductor device 110 is desired to be reduced, the n value may be set to “6” or “8”, that is, the operation scale and speed, the area of the sense amplifier 600, and the like. The n value can be freely selected appropriately according to the needs such as the ratio.

Next, a case where a semiconductor device is used for a tester using algebraic division will be described with reference to FIG. FIG. 17 is a configuration diagram of the tester and the like. The tester 1900 is a device for confirming the operation of the test target LSI 1910 (another semiconductor device).
The tester 1900 includes a large-scale memory 1400 (storage device), a semiconductor device 110, a driver 1901, a comparator 1902, a processing unit 1903, and a remainder generation unit 1904.

The large scale memory 1400 provides a divisor for the semiconductor device 110.
The semiconductor device 110 has a configuration of the memory cell 200 corresponding to the dividend in advance.
The semiconductor device 110 that has input the divisor outputs the quotient (random pattern) to the driver 1901 and outputs the remainder A (correct value of the remainder) to the comparator 1902.

The driver 1901 is a drive circuit, and upon receiving a quotient from the semiconductor device 110, transmits a signal based on the quotient to the test target LSI 1910.
The test target LSI 1910 operates based on the quotient input from the driver 1901 and outputs an output value to the remainder generation unit 1904.

The remainder generation unit 1904 converts the output value input from the test target LSI 1910 to obtain a remainder B.
The comparator 1902 is a comparator, and compares the remainder A input from the semiconductor device 110 with the remainder B input from the remainder generation unit 1904.
The processing unit 1903 is a device that receives the output from the comparator 1902 and performs processing. For example, the processing unit 1903 is realized by a CPU (Central Processing Unit), and receives the output from the comparator 1902 when the remainder A and the remainder B are the same. The test target LSI 1910 is determined to be “normal”.

Although not particularly illustrated, the tester 1900 includes a DC power supply, a timing generator, and the like as necessary.
In this manner, the semiconductor device 110 can be applied to a tester that uses algebraic division. The semiconductor device 110 corresponds to a so-called pattern generator, and the remainder generation unit 1904 corresponds to a so-called pattern compressor.

Next, an operation program of the semiconductor device 110 will be described.
In the manufacture of conventional FPGAs, for example, a C language program is created, and then HDL (Hardware Description Language) is created. Logic synthesis is performed from the HDL to create a logic circuit. From the logic circuit, logic arrangement and arrangement wiring are performed on the corresponding FPGA. In other words, a complicated and sophisticated work process was required.
On the other hand, since the semiconductor device of the present embodiment is a memory and a storage device, a C language program can be compiled and its data can be loaded as a truth value, so that the work process is simple and easy. In addition, since the semiconductor device of this embodiment is a memory device, even when different logic circuits are realized, it is only necessary to rewrite truth table data written in the memory cell 200 without changing the wiring.

  This will be described more specifically with reference to FIG. 18 (see FIG. 1 as appropriate). FIG. 18 is a flowchart showing a flow of processing when bit data for operating as a logic circuit is mounted on a semiconductor device.

First, the information processing apparatus 100 inputs a C language program describing a function to be realized from the input unit 101 (step S1201) and stores it in the storage unit 102.
Also, it is assumed that programs for various functions (addition, subtraction, etc.) are stored in the storage unit 102 in advance.

The operator of the information processing apparatus 100 adds a declaration sentence (Include sentence) using the input unit 101 in order to quote a necessary program among the programs stored in the storage unit 102 (step S1202).
The processing unit 106 creates a truth table (such as the truth table 601 in FIG. 7) based on the C language program with the Include statement added (step S1203), and creates bit data based on the truth table. Further, the bit data is mounted on the semiconductor device 110 via the communication unit 105 (step S1204) (step S1205).
Thus, according to the semiconductor device 110 of the present embodiment, the work for operating the semiconductor device 110 as a logic circuit can be simplified.

  As described above, according to the present embodiment, a semiconductor device that operates as a logic circuit, does not need to be connected again even if the truth value of the memory is rewritten, and can return data to the semiconductor device. Can be realized.

  Further, according to the semiconductor device of this embodiment, since an actual logic circuit is not used, even if a failure occurs in a part of the memory, the countermeasure (rescue) is avoided by avoiding the use of that part. It can be done easily.

  Furthermore, according to the semiconductor device of this embodiment, it is possible to test another one memory by using a plurality of memories and putting a test program in some of them. Then, after the test is completed, by deleting the test program from the memory in which the test program is stored, these memories can be used as a normal memory.

Further, a system LSI having a built-in memory performs self-test with the memory as the structure of the semiconductor device of the present embodiment, and configures a test logic circuit by writing a test program written in C language in that portion. Thus, other logic circuits in the system LSI can be tested.
Further, the number of sense amplifiers in one memory cell block is not limited to two, and may be one or three or more.

This is the end of the description of the embodiments, but the aspects of the present invention are not limited to these.
For example, the semiconductor device of the present invention may be realized using a DRAM (Dynamic Random Access Memory) or a flash memory instead of the SRAM.
Further, it does not limit the mounting of functions such as a precharge function for improving performance in the memory.
Further, the memory cell may be of a so-called double gate type using two read word lines.
In addition, it can change suitably in the range which does not deviate from the meaning of this invention.

Claims (8)

A semiconductor device having a plurality of memory cell blocks each including a plurality of memory cells for storing a predetermined amount of data,
Each of the memory cell blocks has an input number and an output number of 4 or more, and includes a read address decoder for the memory cell and a sense amplifier for amplifying a voltage when output to the outside, and a predetermined address input Storing truth table data for outputting a desired logic value in the memory cell and operating as a logic circuit;
The memory cell has a read word line corresponding to the read address decoder, and when the voltage of the read word line is applied, the data held at that time is read from the read data line. ,
The memory cell blocks are connected such that four or more outputs from one memory cell block are input to the other four or more memory cell blocks via the sense amplifier,
The memory cell block has 5 or 6 inputs and outputs,
The memory cell blocks are connected so that the outputs of 5 or 6 from one memory cell block are input to other four or more memory cell blocks via the sense amplifier. that semi conductor device. A semiconductor device having a plurality of memory cell blocks each including a plurality of memory cells for storing a predetermined amount of data,
Each of the memory cell blocks has an input number and an output number of 4 or more, and includes a read address decoder for the memory cell and a sense amplifier for amplifying a voltage when output to the outside, and a predetermined address input Storing truth table data for outputting a desired logic value in the memory cell and operating as a logic circuit;
The memory cell has a read word line corresponding to the read address decoder, and when the voltage of the read word line is applied, the data held at that time is read from the read data line. ,
The memory cell blocks are connected such that four or more outputs from one memory cell block are input to the other four or more memory cell blocks via the sense amplifier,
Each of said memory cell block, the semi-conductor device you characterized in that stores a truth table data in said memory cell to output a value obtained by dividing the address input as a random pattern. A semiconductor device having a plurality of memory cell blocks each including a plurality of memory cells for storing a predetermined amount of data,
Each of the memory cell blocks has an input number and an output number of 4 or more, and includes a read address decoder for the memory cell and a sense amplifier for amplifying a voltage when output to the outside, and a predetermined address input Storing truth table data for outputting a desired logic value in the memory cell and operating as a logic circuit;
The memory cell has a read word line corresponding to the read address decoder, and when the voltage of the read word line is applied, the data held at that time is read from the read data line. ,
The memory cell blocks are connected such that four or more outputs from one memory cell block are input to the other four or more memory cell blocks via the sense amplifier,
The plurality of memory cell blocks each have a rectangular shape with the same size, and the memory cell blocks are connected to each other by disposing at least a part from the array arrangement. semi conductor arrangement shall be the features. A semiconductor device having a plurality of memory cell blocks each including a plurality of memory cells for storing a predetermined amount of data,
Each of the memory cell blocks has an input number and an output number of 4 or more, and includes a read address decoder for the memory cell and a sense amplifier for amplifying a voltage when output to the outside, and a predetermined address input Storing truth table data for outputting a desired logic value in the memory cell and operating as a logic circuit;
The memory cell has a read word line corresponding to the read address decoder, and when the voltage of the read word line is applied, the data held at that time is read from the read data line. ,
The memory cell blocks are connected such that four or more outputs from one memory cell block are input to the other four or more memory cell blocks via the sense amplifier,
When said memory cells of the memory cell blocks does not store the truth table data, semiconductors devices you said to operate as a storage device. A semiconductor device having a plurality of memory cell blocks each including a plurality of memory cells for storing a predetermined amount of data,
Each of the memory cell blocks has an input number and an output number of 4 or more, and includes a read address decoder for the memory cell and a sense amplifier for amplifying a voltage when output to the outside, and a predetermined address input Storing truth table data for outputting a desired logic value in the memory cell and operating as a logic circuit;
The memory cell has a read word line corresponding to the read address decoder, and when the voltage of the read word line is applied, the data held at that time is read from the read data line. ,
The memory cell blocks are connected such that four or more outputs from one memory cell block are input to the other four or more memory cell blocks via the sense amplifier,
The memory cell block includes:
The area of the memory cell that operates is divided into two parts,
When a specific address selection line in the read address decoder is switched, the area of the memory cell to be operated is switched, operation as two types of logic circuits, or operation as a logic circuit and operation as a storage device , semi-conductor devices either characterized in that switching to instantaneous. A semiconductor device having a plurality of memory cell blocks each including a plurality of memory cells for storing a predetermined amount of data,
Each of the memory cell blocks has an input number and an output number of 4 or more, and includes a read address decoder for the memory cell and a sense amplifier for amplifying a voltage when output to the outside, and a predetermined address input Storing truth table data for outputting a desired logic value in the memory cell and operating as a logic circuit;
The memory cell has a read word line corresponding to the read address decoder, and when the voltage of the read word line is applied, the data held at that time is read from the read data line. ,
The memory cell blocks are connected such that four or more outputs from one memory cell block are input to the other four or more memory cell blocks via the sense amplifier,
When the truth table data stored in the memory cells of some of the memory cell blocks among the plurality of the memory cell blocks is rewritten,
Semi conductor arrangement you and changes the operation in accordance with the rewritten truth table data. The semiconductor device according to claim 2 constituting a system LSI,
A semiconductor device characterized by self-testing and testing another logic circuit in the system LSI. The semiconductor device according to claim 1 , wherein the semiconductor device is compiled by a C language program in which operation is described.

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