TWI357212B - - Google Patents

Description

139. The invention relates to a semiconductor device which can operate a memory as a logic circuit. [Prior Art]

Conventional semiconductor devices such as LSI (Large Scale Integration) are manufactured through many functions such as functional design, logic circuit design, wafer fabrication, and assembly. Thus, although its manufacturing engineering is suitable for mass production of the same product, it is not suitable for lowering costs for each small amount of production of a wide variety of articles. Here, a manufacturing technique such as an FPGA (Field Programmable Gate Array) has been developed as a technique suitable for a small amount of production of a plurality of types of semiconductor devices. The FPGA is a technology of a semiconductor device such as an LSI that can be programmed with a logic circuit after manufacture. However, since the FPGA is composed of a plurality of components such as a logic circuit and a wiring 'switch, there is a problem that a wiring structure of each layer and a high manufacturing technique are required for the number of wiring layers on the semiconductor process. In order to solve the problem, the problem is as follows: in the patent document, the memory is written in the memory of the (Static Random Access Memory), and the address is used as the output. A technique of a semiconductor device that operates as a logic circuit. [Patent Document 1;] Japanese Patent Laid-Open No. 2003-224468

2036-7602-PF SUMMARY OF THE INVENTION Problems to be Solved by the Invention: However, in the semiconductor device of Patent Document 1, a memory cell block of a plurality of memory cells collectively ensembles a predetermined amount of data is arranged in an array. The data of one memory cell unit block is only for outputting two of the adjacent four memory cell unit blocks (for example, the right and left sides of the top, bottom, left, and right sides), but to enable the data to be returned (return to the original The logic circuit of the memory cell block is difficult to operate. Moreover, the normalization of the size (input number and output number) of the memory cell unit block has not been considered. Here, the present invention has been made in view of the above-mentioned problems, and provides a dictation that can easily perform data manipulation and corrects the scale of the five-remembered unit cell block in order to operate as a logical circuit. The semiconductor device is designed for the purpose. Means for Solving the Problem: In order to solve the above problems, a semiconductor device according to the present invention includes a plurality of memory cell blocks including a plurality of memory cells for storing predetermined data. Therefore, each of the aforementioned memory cell blocks is configured to operate as a logic circuit by memorizing the truth table data for outputting the desired logical value to a predetermined address. Further, the memory cell blocks are connected to each other by inputting three outputs from one memory cell block to three or more other memory cell blocks. Effect of the Invention: The semiconductor device according to the present invention is made as a logic circuit

2036-7602-PF 6 1357212 The memory of the action can easily perform data feedback and can normalize the size of the early block of the memory unit. [Embodiment] Hereinafter, a semiconductor device according to an embodiment of the present invention will be described with reference to the drawings. 1 is a view showing the configuration of a semiconductor device and an information processing device. The information processing device 100 includes a computer device, an input unit 1〇1 such as a key disk, a memory unit 102 such as a hard disk, a memory 103 such as a RAM (Random Access Memory), and a CRT (Cathode Ray Tube). The output unit 1 04 is a communication unit 205 of the communication device; and a processing unit 106 such as a CPU (Central Processing Unit). Further, the bit data (described later in step S1104 in FIG. 12) formed by the information processing device 100 may be held in a ROM (Read Only Memory) (not shown), and the semiconductor device 110 and the information processing device 100. The communication unit 105 is connected. The semiconductor device 110 is a memory device similar to that of a normal SRAM (Static Random Access Memory), and is described in detail below with reference to FIG. 2 . Fig. 2 is a view showing the configuration of a memory unit constituting a memory element of the semiconductor device 110 of Fig. 1. The memory unit 200 is configured to include: read word lines 201, 202; write word lines 211; read data lines 221, 222; write data lines 231, 232; gates 241, 242, 251, 252, 261 262; and the flip-flop 271. 2036-7602-PF 7 1357212 Further, although the gates 241, 242, 251, 252, 261, and 262 are configured by N-MOS (Negative-Metal Oxide Semiconductor), P-MOS (Positive-Metal) can also be used. Oxide Semiconductor) • It can be used as a composite gate for N-M0S and P-M0S. In this case, it is better to change the peripheral circuits as needed. The reading word line 2 (Π, 202 is a wiring for applying a voltage when the data of the memory unit 200 is read from the outside. When the voltage of the reading word line 201 is applied, the gate 241 and the gate 242 are opened. The gate 251 and the gate 252 are turned on to read the voltage of the word line 202. The read word line 211 is a wiring for applying a voltage when writing data to the memory unit 2 from the outside. The voltage of the line 211 is turned on, and the gate 2 61 and the gate 262 are opened. The read data line 22 222 is applied to the read word line 201 and the read word line 202 to apply a predetermined voltage, and the gates 241, 242, 251 are applied. And 252 are wirings that can be read from the data held by the flip-flops 2 71 when they are turned on. Also, when the data is read from the read data line 221, when the data "0" is read out _ When the data "1" is read from the read data line 222 and the data "1" is read from the read data line 221, the so-called differential signal of the data "0" is read from the read data line 222. The operation of writing the data lines 231, 232 to the write word line 211 is applied, and when the gate 261 and the gate 262 are opened, the data can be written. In the wiring of the flip-flop 271, when the data "〇" is written from the write data line 231, the data "1" is written from the write data line 232, and the data "1" is written from the write data line 231. At the time of writing, the data "〇" is written from the write data line 232.

2036-7602-PF 丄357212 The flip-flop 2 71 is a memory circuit for retaining the data of "0" or "1" stored in the memory unit 200 in the above sense. Figure 3 is a block diagram of a portion of the internal structure of the internal structure of the semiconductor device 110 of Figure 1 (suitable for comparison with Figure 2). The unit cell 300 includes a plurality of memory cells 2 〇 〇 arranged in an array and connected to the address decoders 311 and 312. Further, as described above, the read address decoders 311 and 312' including the double read word line 2 〇 2 〇 2 may have the wiring function described below. The memory cell 200 on the outer side of the uppermost segment, that is, the memory cell 2 (Cell 31, 〇) and the memory cell 200 (Cell 31, 3) on the upper side; and the lowermost The inner memory unit 2, that is, the memory unit 200 (Cell0, 1) and the lower side of the memory unit 2 (CellO, 2), connect the read data lines 221, 222 to other memory unit blocks 300 (not The illustration is constructed in the same way. Moreover, the memory cell 200, which is the inner side of the uppermost segment, that is, the memory cell 2〇〇 (Cell31, η and the memory cell 200 (Ce 1131, 2)) on the upper side; and the lowermost segment The memory unit 2〇〇 on the outer side, that is, the memory unit 2〇〇 (Cell〇, 〇) and the memory unit 2〇〇 (Cell(), 3), will be cut off by reading the data lines 221 and 222. That is, in the memory cell block 300, the read data line is formed by connecting the complex number of the outer side to the upper side and the inner side of the complex number to the lower side. Thus, the output of the memory cell block 3 can be performed ( The size of the readout is suppressed to the necessary minimum, and the burden of various data processing is alleviated, and the output of the complex number can be performed in the plural direction.

2036-7602-PF 9 1357212 In the memory cell block 3 Ο 0, the read address decoder 311' is arranged on the left side and the complex address difference signal is received from the address input line 3 2 2 . Further, in the memory cell block 300, the read address decoder 312 is disposed on the right side, and the complex address difference signal is received from the address input line 32 3 . In addition, the so-called "three" or "four" in the number of inputs and the number of outputs in the scope of application for patents are equivalent to the meaning of "pair" or "four pairs" in the case of a so-called differential signal. The memory cell block 300 is separated by a number from the symbol 331 to the symbol 362 by input from the address input line 322, the address input line 323, the select line (designated address select line) 3〇1. The strip reads the word line (corresponding to the sub-element line 2 0 2 of FIG. 2) to select any strip, and the voltage at which the word line is read can be applied. Further, the selection line 3〇1 includes an inverter 3〇2. Further, the read address decoder 311 includes a plurality of logic circuits (AND circuits, etc.) 37 〇. and

Moreover, the write character line 371 (corresponding to the read character 3 (1) of Fig. 2 is connected to the write address decoder 411 (cf. Fig. 5). Also, the logic of decoding the address 312 even if the address is decoded. The circuit or the like is also the same as the case of the read address decoder 3! i, and therefore the description will be omitted (for example, the logic circuit 380 is connected to the read word line 381). When the input "1" is input from the selection line 301, the memory unit 200 in the memory unit block is operated by the upper half of the memory unit attached to the memory unit block 3 and the selected line person "〇"_'. The lower half is divided. Therefore, if it is set to, for example, it can be recorded in the memory cell block 3〇〇

2036-7602-PF 1357212 The upper half of the unit 200 is used as an adder, and the lower half of the memory unit 2 is used as a subtractor to operate. Only by switching the signal from the selection line 3〇1, it can be instantaneously Perform the switching between the adder and the subtractor. Further, in addition to this, switching between the adder and the normal memory device or the like can be performed. In the above, although the memory cell block 3 is described as a whole and in detail, if the memory cell 200 is used as the vertical 32) [horizontal 4 configuration, the read data line 22 222 is shortened (cf. FIG. 2). The sense amplifier can be omitted and the circuit can be simplified. Figure 4 shows the read connection 槔 in the semiconductor device 对照1〇 (reference picture 槔) (every 2 outputs above the read data line of Figure 3 and every 2 inputs from the address input lines 322, 323) Picture. Further, Fig. 4 shows a part of the upper left side when the semiconductor device is viewed in a plan view. In the suffix unit blocks 300d to 3001, 'input A0 (hereinafter referred to as "A0": A1 to A3 are also the same) is made by combining the gossip and /A of FIG. 3 for the sake of simplicity. And about A1~A3 are the same. Further, in the memory cell blocks 3〇〇d to 3001, the output D0 (hereinafter referred to as "DO": D1 to D3 are also the same) is a memory unit 200 of FIG. 3 for the sake of simplicity of presentation (Ce 1131, 0). The read data lines are made up of two together, and the same is true for D1 to D3. § A0 to A3 and D0 to D3 of the cell blocks 300d to 3001 are connected as shown in FIG. 4 and the 'drive circuit 420 is input from the external device to the device (semiconductor device 110). The signal is converted into a differential signal. Further, the amplifier 430 amplifies and converts the input differential signal into a normal 2036-7602-PF 11 1357212 signal and outputs it to an external device. In order to make such wiring, in the semiconductor device 110, feedback of data can be easily performed. Specifically, for example, when the data is sent from the (10) of the memory cell block (10) to the memory cell block 3〇〇giA1, the data from the memory cell block 3〇〇g can be given from D1. Similarly, if the truth table is first written to the 5 memory cell block 3 〇〇g, the data can be returned to A3 of the memory cell block 300d. Moreover, only the memory cell block 3 will be written. The truth table of 〇〇d3〇〇1 is changed, and the semiconductor device 11 can be operated as various logic circuits without changing the wiring. Further, the number of times and the appearance of the wiring are particularly 5 is a suitable configuration of the semiconductor device 11 (refer to FIG. 1). The memory cell blocks 300 are arranged in an array and are configurable on the left side. The address decoder 411 is provided with the write/read circuit 4" on the lower side. They are connected as shown in the figure. In short, Fig. 5 is a view showing a state other than the connection state of the read cymbal in the semiconductor device 11 同样 similar to that of Fig. 4 . The write address decoder 411 is configured to write the data to the memory cell block 3 as the x address of the specified memory cell block 3 (the address in the vertical direction of the semiconductor device 11 in FIG. 5). Device. The write address decoder 411 is used as the address of any memory unit block 3 in the memory unit block 300 of the specified complex number to be input to the upper address (the % time system A5w, A6w, ...) And the address of the internal (memory unit 2〇〇) of the memory unit block 300 designated as the designated one is the lower address

2036-7602-PF 12 U57212 In (in this case, A0w~A4w) is input J and the J input/readout circuit (9)1 is used to specify the reading and writing of the execution data: ::: y address, and then specified The memory unit paste does not obstruct the reading and writing of the material. Having: In the write/read circuit 4〇1 as the specified complex number, any memory cell block address (the semiconductor device in FIG. 5 takes the address in the horizontal direction) is Lose people (this occasion is tied to

The purpose is to write data from the input unit _ and internal (memory unit 200) of the shirt (in this case, in Figure 3: the address corresponds to the same 4 memory units) The 4-bit) is input to the write/read circuit 4〇1. - In this way, the truth table data can be overwritten with the memory unit 2 适宜 which is suitable for selecting the finger in the designated memory cell block 3〇〇. In other words, when the semiconductor device is in the memory cell of the plurality of memory cells, the memory cell (10) of the memory cell block (3) is stored in the memory device (10). Overwrite the truth table data to change the action. Continuing with reference to Fig. 6 to Fig. 9, the semiconductor device 11 〇 (cf. Fig. 4) is used as a three-bit adder. Fig. 6 is a configuration example of an 8-bit adder. The connection between the memory cell blocks in Fig. 6 is the same as in the case of Fig. 4. Here, a description will be given of a case where the number of octets E and p are added and the result is Y. Also, the lowest bit of E is E0,

2036-7602-PF 13 1357212 times—the bit is used as El and the highest bit is used as E2. Moreover, the lowermost bit of F is taken as F0, the next bit is taken as F1, and the uppermost bit is taken as F2. Furthermore, the lowermost bit of Y is used as Y0, the next bit is used as Y1, and the highest bit is used as Y2" and the carry of the addition according to the lowest bit is taken as c〇, based on The carry of the addition of one element is taken as C1, and the carry of the addition according to the highest bit is taken as C2. Further, although each signal system is differential, it is described briefly in the description. In the memory cell block 300d, E0 is input from A0, F0 is input from A1, and the addition operation is performed, and Y0 is output from D3, and C0 is output from D2. In the memory cell block 300e, E1 is input from A0, F1 is input from A1, C0' is input from A3, and addition is performed, and Y1 is output from D3, and C1 is output from D2. In the memory unit block 30 (^ is input from person 0, £2, from person 1 is input to ?2, and from C1' is input from A3, and addition is performed, and Y2 is output from D3, and C2 is output from D2. The Y0 outputted by D3 of 30Od is output from D3 of the memory cell block 3〇〇j via the path of the figure. The Y1 outputted from D3 of the memory cell block 300e is via the path of the figure D3 is output from the memory cell block 3〇〇k. Y2 outputted from D3 of the memory cell block 30〇f is outputted from D3 of the memory cell block 3001 via the path ' as shown in the figure. In the following, Y0, Y1, and γ2 are obtained as the result of the addition. In Fig. 7, '(a) is a simplified diagram of the memory cell block 300, and (b) is stored in the memory cell blocks 300d, 300e, and 300f. The truth table (suitable for comparison with Figure 6). 2036-7602-PF 14 1357212 As shown in Figure 7(a), 'in the memory cell block 3〇〇, as long as _ wheel in A0~A3', according to its input D0~D3 can rotate the data that has been defined in the truth table. As shown in Figure 7(b), as long as one is in AO, A1, A3# E (E〇~E2), F(F0~F2), Cin (C0~C2) input Then, as the result of the addition of three, the value of the bit is output to D3 as γ(γ〇~γ2), and the value is input to D2 as Cout(C0~C2). Also, 'Because D0 and D1 are not used here, they can be output as "〇" in all cases. And 'Although from the above, the first paragraph - the fourth paragraph and the fifth paragraph ~ 8 paragraphs, and 9th paragraphs - 12th paragraphs and 13th paragraphs - 16th paragraphs are the same as the true value except A2, but this is because any data is input even if A2 inputs r 〇" and "j" The correct output result can also be obtained. In Fig. 8, (a) is a simplified diagram of the memory cell block 3, and (b) is a truth table stored in the memory cell blocks 300g, 300j, 300k, and 3001. (Appropriate to FIG. 6) As shown in FIG. 8(a), in the memory cell block 300, as long as there is an input in a〇~A3, the DO~D3 output can be defined in the truth table according to its input. As shown in Fig. 8(b), as long as A1 has Y (Y0~Y2) input, its value is output as usual to D3. Also, because D0~D2 are not used here, Made in place In some cases, r 〇" can be output." Actually, although it is preferable to have "0"-> "0" from A1 to D3,

2036-7602-PF 15 1357212 "!" 2 types (2 segments) of the truth table, but even if you input any of the "〇" and "丨" in aq a2, A3, you can get the correct output. Ground, become the truth table of 16 segments. In Fig. 9, '(a) is a simplified diagram of the memory cell block 3, and (8) is stored in the truth cell of the memory cell blocks 3〇〇h and 300i (suitable for comparison with Fig. 6). As shown in Fig. 9(a), in the memory cell block 3, as long as there is an input from a〇 to a3, the data defined in the truth table is output from DO to D3 based on the input. • As shown in Fig. 9(b), as long as the input of (3) to C2 is stripped, the value is output as usual to D1. Moreover, when A1 has an input of γ(γ〇~γ2), its value is output as usual to D3. Also, since D0 and D2 are not used here, "〇" can be output in all cases. Further, in the same manner as in the case of Fig. 8(b), even if any data of "0" and "1" is input to A2 and A3, a correct output result can be obtained. Fig. 10 is a view showing a connection state of a semiconductor device 11 as a modification of the semiconductor device 11 of Fig. 4 in a half-conductor device. In the semiconductor device 11a, 'compared to the memory cell block 3〇〇m~3〇〇〇 in the leftmost column and the memory cell block 3〇〇s~3〇〇u in the column from the left third, The memory cell blocks 300p to 300r of the column are arranged in the vertical direction by shifting the half-divided memory cell blocks. Moreover, A'~8-3 and D0~D3 of the respective memory cell blocks are connected as shown. Thus, the memory cells are arranged in a staggered manner, and compared with the case of the semiconductor device 110 of Fig. 4, the D?~])3 of the respective memory cell blocks can be shortened.

2036-7602-PF 16 1357212 Enter the length of the wiring of AO to A3 of other memory cell blocks. Further, the number of times and the appearance of the bending of the wiring are not particularly limited to the Fig. 10, and can be appropriately changed. Further, the internal configuration of the semiconductor device 110a (corresponding to Fig. 5) is as shown in Fig. 11. In the semiconductor device 11〇3 of FIG. 11, the memory cell block 300a (corresponding to the memory cell block 3〇〇m~300o of FIG. 10) and the memory cell block 3 of the left third column are compared with the leftmost column. 〇〇c (corresponding to memory cell block 300s~300u of Fig. 10) 'memory cell block 3〇〇b in between (corresponding to Fig. 1 δ 己 recall unit block 3 0 0 p~3 0 0 r system Since the vertical direction is arranged by shifting the half-divided memory cell blocks, the X address and the internal X address system of each memory cell block input to the write address decoder 411 can also be set in consideration of this. Illustratively, in the memory device according to the present embodiment, data can be easily executed by giving four memory cell blocks from one memory cell block in a memory that can operate as a logic circuit. In addition, in the manufacture of conventional FPGAs, for example, to write a c language program, and write it into HDLCHardware Description Language). The logic synthesis is performed from its HDL, and a logic circuit is created. From its logic circuit, the FPGA is configured to perform logic configuration and configuration wiring. In short, complex and high-level work engineering is necessary. On the other hand, since the semiconductor device of the present embodiment is a memory and is a memory device, since the c language program can be compiled and the data is loaded into a true value, the work is simple and easy. Moreover, since the semiconductor device of the present embodiment is a memory device, even if the implementation is different

2036-7602-PF 17 1357212 In the case of logic circuit, the wiring system can also be completed by simply overwriting the true value data written to the memory unit. ——The surface is more specifically described with reference to Figure 12 (suitable for comparison) Fig. 12 is a flow chart showing a processing flow when the bit data for operating the logic circuit is mounted on the semiconductor device. First, the information processing device 100 is a C language that describes the function to be realized.

The program is input from the input unit 101 (step S1101), and is stored in the recording unit 102. D Also, the memory unit 1 〇 2 is used as a program that can memorize various functions (addition, subtraction, etc.). Since the operator of the information processing apparatus 1 refers to the necessary items stored in the program stored in the memory unit 102, the input unit 1〇1 is used to add the essay (Included) (step si 102). The processing unit 106 creates a truth table (the truth table 6 00 in FIG. 7 or the like) based on the c language program added to the Include text (step S1103), and creates bit data based on the truth table (step S11〇4). Further, the bit data is mounted on the semiconductor device 11 via the communication unit 1〇5 (step su〇5). As described above, according to the semiconductor device U of the present embodiment, the operation of operating the semiconductor device 110 as a logic circuit can be easily performed. Furthermore, since the semiconductor device according to the present embodiment is not used, the actual logic circuit is not used, so that even if a part of the memory is broken, the correspondence can be easily performed by avoiding the use thereof or the like (relief) ). Moreover, if the word line of one memory cell block is used as 32 in the case of 2036-7602-PF 18 1357212 as in the present embodiment, the attenuation of the data (signal) can be suppressed without sensing the amplification of the pirate. Use. However, if the function of the semiconductor device is to be emphasized, the number of word lines can be made 33 or more by detecting the amplified pirates or reading the data lines to use the intermediate buffer. Further, according to the semiconductor device of the present embodiment, another memory can be tested by using a plurality of memories and putting the test program into several memories therein. Therefore, after the test is completed, the test program is erased from the memory loaded into the test program, and the memory can be used as the usual memory. Further, in the system LSI of the built-in memory, the memory is self-tested by the structure of the semiconductor device of the embodiment, and the test logic circuit is written by the test program described in the C language. 'And other logic circuits in the system LSI can be tested. Furthermore, the connection between the memory unit blocks is not limited to the case where one memory unit block is connected to the other four memory unit blocks, and may be more than three memory unit blocks that are returned as the execution data. Other components connected. Furthermore, although the read data lines are made differential, the logic layout of the semiconductor layout and the read address decoder can be considered, and the data lines can be wired only on one side. Although the description of the embodiments has been completed above, the aspects of the invention should not be limited to these. For example, the semiconductor device of the present invention can be implemented by using DJRAM (Dynamic Random Access Memory) and flash memory instead of the above.

2036-7602-PF 19 The memory of the second memory is improved. The function of the memory is loaded. It is possible that he does not go beyond the scope of the present invention to give appropriate changes. It is a simple diagram of the structure of the information processing device. BRIEF DESCRIPTION OF THE MEMORY ELEMENTS OF THE SEMICONDUCTOR DEVICE 110 Fig. 1 shows a semiconductor device Fig. 2 as a block diagram of the memory cell of Fig. 1. Figure 3 is a block diagram of a memory cell block. Fig. 4 is a view showing the connection state of the readout electrodes in the semiconductor device 11A. Fig. 5 is an internal configuration diagram of the semiconductor device 11A. Fig. 6 is a configuration example of a 3-bit adder. Fig. 7(a) is a schematic diagram of the memory cell block 3A, and Fig. 7(b) is a truth table stored in the memory cell blocks 300d, 300e, and 300f. Fig. 8(a) is a schematic diagram of the memory cell block 3A, and Fig. 8(b) is a truth table stored in the memory cell blocks 3 0 0 g, 3 0 0 j , 300k, and 300 1 . Fig. 9(a) is a schematic diagram of the memory cell block 3A, and Fig. 9(b) is a truth table stored in the memory cell blocks 300h and 300i. Fig. 10 is a view showing the connection state of the readouts in the semiconductor device 11A3. Fig. 11 is a view showing the internal structure of the semiconductor device 110a. 2036-7602-PF 20 1357212 Fig. 12 is a flow chart showing a processing flow when a bit device for operating a logic circuit is mounted in a semiconductor device. [Description of main component symbols] 100 Information processing device 101 Input unit 102 Memory unit 103 Memory

104 output unit 105 communication unit 106 processing unit 110 semiconductor device 200 memory unit 201, 202 read word line 211 write word line 221, 222 read data line 231, 232 write data line 241, 242, 251, 252 , 261 , 262 gate 271 flip-flop 300 memory cell block 301 select line 302 inverter 311 ' 312 read address decoder 322, 323 address input line 2036-7602-PF 21 1357212 401 write / read 600 ' 700 ' 800 circuit truth table

2036-7602-PF 22

Claims (1)

1J57212 No. 094143819 No. 094143819 revised the replacement page, the patent application Fangu.m _ device, having a plurality of memory unit blocks including a plurality of memory units for memorizing the quantitative data, wherein: The memory cell block memorizes the truth table data for outputting the desired logic value by inputting a predetermined address, and is constructed as a logic circuit; The number of single-system bad input and the number of outputs are three or more; the foregoing memory cell fields are 'multiple of the foregoing memory cells that can be rotated from one memory cell block to three or more other memory cell blocks The block systems are each formed into a rectangular parallelepiped of the same size, and the second block is configured by at least a staggered arrangement from the array configuration, and the execution is performed: the connection between the memory cell blocks. The binary conductor device 'has a plurality of memory cell blocks including a plurality of memory blocks for memorizing the quantitative data, wherein each of the memory cell blocks is input to a predetermined address. The truth table data of the desired logical value is memorized in the note leaflet, and is constructed as a logic circuit. ^ : The memory cell block system, the number of inputs, and the number of outputs are three or more; The memory cell blocks are connected in such a manner that three rounds of (10) memory cell blocks can be input to more than three other memory cell blocks; 2036-7602-PF1 23 1357212. (10) 4143819, September 100 14th modified replacement page, the memory unit is internally contained in the memory unit to correspond to the above two: out address decoder; contains two read word lines, and two read word decoders When it is applied, the voltage is now out. The data held at this time is read from the read data line. 3. As claimed in the patent scope, the + conductor device includes: a write address decoder, and a plurality of the above-mentioned records and specifies a plurality of memories. Single ^ phase connection, X address; & the edge of the memory cell writes the eight-best circuit 'connected with a plurality of the aforementioned memory cell blocks to specify a plurality of constant orders, and ~ ghosts and their internal σ卩The address of the memory unit is 丄 丄 丄 丄 前述 前述 前述 前述 前述 前述 前述 前述 前述 ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; In the semiconductor described in the second or second paragraph of the patent application, in the memory cell block described above, ^ s 隐 早 早 早 己 己 己 己 己 己 己 己 己 己 己 己 己 己 己 己 己 己The device operates. 5. The semiconductor device according to claim 2, wherein in the memory cell block, the area of the memory cell to be operated is divided into two parts; for privately decoding the read address When the specified address selection line in the device is switched, the area of the memory unit that performs the above action is switched, and the 2019-7602-PF1 24 1357212 No. 094143819 is revised on September 14, 100. The replacement page is 2 The action of the type of logic circuit, or the action of the A logic stepping circuit and the operation of the normal memory device - the action is switched as %. 6. The semiconductor device according to claim 1 or 2, wherein, in the plurality of memory cell blocks, the memory of a portion of the memory cell of the memory cell is true When the value table data is overwritten, the action is changed based on the truth table data that is overwritten. 7. The semiconductor device of claim 2 or 2, wherein the system LSI is constructed; the self-test is feasible, and the other logic circuits in the aforementioned system LSI are tested. 8. The semiconductor device according to claim 1 or 2, wherein the semiconductor device is compiled by a c language program described in the operation. 2036-7602-PF1 25 1357212 f No. 094143819 Revision of the revised page on September 14, 100. VII. Designation of representative drawings: (1) The representative representative of the case is: (5). (2) A brief description of the component symbols of this representative diagram: · - 110 semiconductor device; -· 211 write word line; 300 memory cell block; 401 402 write/read circuit; input; 411 • write address decoding Device. 8. If there is a chemical formula in this case, please reveal the chemical formula that best shows the characteristics of the invention. No 2036-7602-PF1 4