JPH06112315A - Integrated circuit designing method and cad device for designing integrated circuit - Google Patents

Abstract

PURPOSE:To reduce dependency on the signal delay characteristics of a cell to be used and to reduce the load of a designer and TAT. CONSTITUTION:A cell A is a cell group of a plurality of cells where the logic relationship between input and output is the same, the occupation shapes and input/output terminal positions of the layout pattern are the same, and at least only one part of the signal delay characteristics are different. Circuit diagram data, logic data, and occupation shape/terminal position layout are common for the same cell group. Also, delay data and layout data are different for each cell in the cell group and can be referred mutually, thus reducing the dependency on the signal delay characteristics by using a cell library in this configuration.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit design method for designing an integrated circuit layout pattern using a logic gate cell registered in advance, or information on a cell layout pattern of a logic gate cell is registered. A CAD device for integrated circuit design that uses information of a logic gate cell to support integrated circuit design, and reduces the burden on the designer by reducing the dependence of the selection of the logic gate cell to be used on the signal delay characteristic. The present invention relates to an integrated circuit design method or a CAD device for integrated circuit design, which can shorten the delivery time.

[0002]

2. Description of the Related Art Integrating an electronic device into an integrated circuit has many advantages such that not only the size of the entire electronic device can be reduced, but also the reliability of the electronic device is improved and the power consumption is reduced. . When designing an integrated circuit, an extremely large number of design steps are required. Therefore, the ratio of the design cost is extremely high, and the TAT (turn around time) becomes long. Therefore, it is difficult to customize. There is. In order to solve the problems (1) to (3) of customizing the integrated circuit, there is a technique in which at least a part of the design process or the manufacturing process is shared and prepared in advance, and the other processes are customized. An integrated circuit using such a technique is called a semi-custom type integrated circuit, and includes a CBIC (cell based integrated circuit) and a G / A (gate array).

The CBIC is an integrated circuit based on a design method in which registered cells corresponding to logic gates and functional blocks are arranged according to a circuit to be incorporated and interconnected. The G / A is an integrated circuit of a system in which a group of cells arranged in a matrix which is processed before the wiring process is made common and the subsequent wiring process is customized according to a circuit incorporated in the integrated circuit. According to such a semi-custom type integrated circuit, it is possible to reduce TAT and cost at the time of designing and manufacturing, and it is possible to provide an integrated circuit designed according to the customer.

Such CBIC and G / A have been performed in the procedure described below, for example.

First, in the first design process, as "creation of a cell library", a cell library is registered for a logic gate or a cell of a functional block composed of a plurality of logic gates. That is, data regarding a cell layout pattern used for designing an integrated circuit layout pattern, data regarding a logical relationship between inputs and outputs, data regarding signal delay characteristics such as delay data depending on an external load when outputting logic, Register as a library.

In the second design process, as "circuit diagram creation", cells registered in advance in the cell library are selected, and input / output connections between the cells are described to create and input user circuits.

In the third design process, as "execution of virtual wiring length simulation", the wiring length between cells at the time of actual layout is predicted from the input user circuit. The virtual cell wiring length thus obtained is substituted into the external load value of each cell to simulate the logical operation and signal delay of the user circuit.

Next, in the fourth design process, as "execution of integrated circuit layout", the actual simulation is performed according to the simulation of the third design process and the user circuit after the design change based on the simulation result performed as needed. The integrated circuit layout pattern is created. That is, the layout of each cell and the actual layout of the wiring between each cell are performed.

In the fifth design process, as "execution of actual wiring length simulation", the wiring length between cells is first obtained as the actual inter-cell wiring length according to the actual layout. Also, the actual cell-to-cell wiring length thus obtained is substituted for the external load value of each cell for calculation, and the logic operation and signal delay of the user circuit are simulated based on the calculation result.

In the sixth design step, as "creation of reticle data", reticle (mask) creation data for manufacturing a semiconductor integrated circuit is created based on the integrated circuit layout result of the user circuit verified in the fifth design step. To generate.

According to such a designing method using a total of 6 steps, the virtual wiring length is obtained in advance and the simulation is performed, so that the cell delay in consideration of the signal delay is taken before the very time-consuming design of the integrated circuit layout pattern. It is possible to make a selection, reduce the burden on the designer,
AT can be shortened.

However, the prediction of the inter-cell wiring length in the third design step is a very time-consuming task. In addition, the work requires the skill of the designer. Therefore, the efficiency of the integrated circuit layout design is reduced,
There was a problem such as extension of delivery date. Further, there is an error in the prediction of the virtual wiring length as described above, which may cause a problem regarding signal delay after designing the integrated circuit layout. In this case, time-consuming integrated circuit layout design must be performed again. Various techniques have been disclosed in order to solve such problems.

For example, a plurality of cells having the same logical relationship between the input and the output, the same occupying shape of the cell layout pattern, and different signal delay characteristics of the output are prepared. Is being done.
As a result, a cell having a more optimal signal delay characteristic is selected from a plurality of cells and used more flexibly.

FIG. 12 is a diagram showing an example of the configuration of a conventional cell library.

In FIG. 12, cell A, cell A'and cell B are registered. These cells A and A '
Have the same logical relationship between their inputs and outputs, and
The occupied shapes of the cell layout patterns are the same. Further, the cell A and the cell A ′ are different from each other in the output delay characteristic, and the delay data in FIG. 12 are different.

FIG. 13 is a graph showing the signal delay characteristics of the output of the cell A registered in the conventional cell library. FIG. 14 is a graph showing the signal delay characteristic of the output of the cell A ′ registered in the conventional cell library.

13 and 14, the degree of signal delay with respect to the magnitude of the external load connected to the output is shown. 13 and 14, the external load value on the horizontal axis and the delay value on the vertical axis are unit values. For example, the cell A has a delay value of about “2.5” with respect to an external load value of “1”. On the other hand, as shown in FIG. 14, the cell A'has a delay value of "1.5" with respect to the external load value "1". As described above, the cell A ′ has a larger output drive capability and a smaller delay value than the cell A.

As described above, the cell A and the cell A'have the same logical relationship between the input and the output, and
The occupied shapes of the cell layout patterns are the same,
Only the signal delay characteristics of the output are different. Therefore, by providing the cell A and the cell A ′, it is possible to flexibly change the output drive capability.

Further, Japanese Patent Laid-Open No. 3-77372 discloses a technique of arranging macro cells composed of basic cells whose relative arrangement relations are predetermined in combination. This is because in the soft macro method in which only the netlist information before the cell layout is made into a macro, the signal delay characteristic is unknown until the integrated circuit layout design. Therefore, by setting the relative arrangement relationship in advance for a certain specific macro cell, The range of change in signal delay between basic cells in the macro cell is compensated. JP-A-3-7737
According to 2, the signal delay characteristic can be compensated to some extent even in the soft macro system.

Further, in Japanese Patent Laid-Open No. 3-259550, at least two methods are used in a semiconductor integrated circuit designing method in which circuit connection information and element information are input and layout data of a semiconductor integrated circuit having desired circuit functional characteristics is created. Layout cell data of a virtually provided switch element having terminals and capable of connecting or disconnecting the terminals by adding or deleting a single step is created. In addition, primary layout data is created by an automatic layout and wiring design in which the connection information of the circuit using the switch element and the element information are input. Connection process data is added to the created primary layout data at the position of the layout cell corresponding to the switch element in the connected state among the switch elements to create the layout data. According to such Japanese Patent Laid-Open No. 3-259550, it is possible to change the circuit connection by the automatic placement and routing program, and it is possible to change part of the circuit function relatively easily.

Further, Japanese Patent Application Laid-Open No. 3-283664 discloses a technique in which the driving capability of a logical function block is switched by selectively short-circuiting a buffer connected to the output terminal of the logical function block. In addition, JP-A-3-
283665 discloses a technique of switching the output drive capability by selecting a plurality of buffers connected in parallel to the output terminal of the logic function block. JP-A-3-283664 or JP-A-3-283636
According to 283665, it is possible to change the signal delay characteristic of the output relatively easily even after the integrated circuit layout.

[0022]

However, the logical relationship between the input and the output thereof as described above with reference to FIGS. 12 to 14 is the same, and the occupation shape of the cell layout pattern is the same. The technique of preparing a plurality of cells having different output signal delay characteristics in advance depends on the designer, and is laborious. Further, the occupying shapes of the cell layout patterns of the plurality of cells must be the same as each other, but this management is performed by the designer, and there is a possibility that a work error may occur.

Further, the technique disclosed in the above-mentioned Japanese Patent Laid-Open No. 3-77372 is to compensate for the delay characteristic of the macro cell in the soft micro system, and to change the signal delay of the output after the integrated circuit layout design. Is not the technology of. Further, the above-mentioned JP-A-3-259550 and the above-mentioned JP-A-3-259550.
283664 and JP-A-3-283636 do not increase the work of different types which has not been performed in the conventional design of an integrated circuit layout pattern, that is, do not perform in the first design process to the sixth design process. There is a problem that the work of different types is increased and the burden on the designer is increased.

The present invention has been made to solve the above-mentioned conventional problems. By reducing the dependence of the selection of the logic gate cell to be used on the signal delay characteristic, the burden on the designer can be further reduced. An object of the present invention is to provide an integrated circuit design method and a CAD device for integrated circuit design that can further shorten TAT.

[0025]

According to a first aspect of the present invention, there is provided an integrated circuit designing method for designing an integrated circuit layout pattern using pre-registered cells. The cell layout pattern of a plurality of cells having the same logical relationship, the occupied shape of the cell layout pattern and the input / output terminal positions being the same, and different only in the signal delay characteristics thereof, of the cell group. Cell group layout information based on the information on the occupied shape and the information on the input / output terminal positions, information on signal delay characteristics of each cell in the cell group, and information on each cell layout pattern of each cell. , So that they can be mutually referenced using relational information, and In designing a cell, first, by using the cell group layout information, the occupied shape of the incorporated cell and the input / output terminal are arranged, and the arranged cell is wired, and after the arrangement and wiring, each cell is arranged. The actual wiring length of each wiring between them is obtained, the degree of signal delay for each wiring is obtained from the actual wiring length, and the relational information and the signal delay are obtained according to the degree of the signal delay and the desired signal delay time. Using the information about the characteristics, a cell in the cell group that is more suitable for the signal delay characteristics is selected, and the information about the cell layout pattern of the selected cell is used to determine the cell layout pattern of the arranged cells. The above problems are achieved by designing and designing an integrated circuit layout.

The CA for integrated circuit design according to the second invention of the present application
In the D device, the information on the cell layout pattern of the cell is registered, and in the CAD device for integrated circuit design which supports the integrated circuit design using the information of the cell, the logical relationship between the input and the output is the same, and For a plurality of cells that are grouped into cells and have the same cell layout pattern occupying shape and the same input / output terminal position and differ only in their signal delay characteristics, the occupying shape information of the cell layout pattern of the cell group and Cell group layout information based on the information on the input / output terminal position, information on the signal delay characteristics of each cell in the cell group,
And cell layout pattern storage means for storing information on each cell layout pattern in a mutually referable state using relational information, and using the cell group layout information, at any desired position of the integrated circuit layout. With respect to the layout editing means capable of arranging the occupied shape of the cell group and the input / output terminals, and the wiring between the arranged cells after the wiring, the actual wiring length of each wiring between each cell is Seeking,
A means for obtaining the degree of signal delay for each wiring from the actual wiring length, and the relational information and information on the signal delay characteristic according to the degree of signal delay and desired signal delay time Means for selecting a cell having a more suitable signal delay characteristic among them and obtaining information on the cell layout pattern of the selected cell are achieved.

Further, the CAD device for integrated circuit design further comprises default value generating means for generating a default value of the signal delay characteristic, and the layout editing means does not define the desired signal delay characteristic. At the time of, by using the default value by the default value generating means, while achieving the above-mentioned object,
The work efficiency is improved.

[0028]

In the first and second inventions of the present application, in order to improve the efficiency of the integrated circuit layout design work, for cells having different output signal delay characteristics, first, the occupied shape and input common to these cells are set. The output terminals are arranged. This allows wiring between the cells before determining the signal delay characteristic of each cell.

FIG. 1 is a diagram showing the gist of the present invention.

FIG. 1 shows an example of a cell library used in the first invention and the second invention of the present application. The cell library stores information related to a plurality of registered cells. For each cell, data required for the integrated circuit layout pattern, data related to the logical relationship between its input and output, signal delay characteristics of output, etc. Various data such as data regarding signal delay characteristics are stored.

In FIG. 1, as an example, the storage form of each of the cells A and B stored in the cell library is shown. The information of the cell A is, for example, in FIG. 1, circuit diagram data, logic data, and
Occupied shape / terminal position layout data (hereinafter referred to as APR data), delay data, and a plurality of layout data A1 to A3 ... Are stored.

The circuit diagram data stores information representing the circuit diagram inside the circuit of the cell A, for example, when the cell A is a functional block using a plurality of basic logic gates. The logical data is information on the logical relationship between the input and the output of the cell A. The A
The PR data stores data regarding the occupied shape of the cell A, that is, the outer shape and area of the cell layout pattern. Further, the APR data has data on the layout position of the input / output terminal with respect to the outside of the cell A.

The delay data and the layout data A
1 to A3 ... Are features of the present invention, and data of each cell forming the corresponding cell group is stored for each cell group. Those having the same logical relationship between the input and the output, the same occupying shape of the cell layout pattern and the same input / output terminal position, and different only in the signal delay characteristic thereof are cell groups, for example, A plurality of cells A1 that are grouped into cells such as cell A
..- A3 ..., Information regarding each signal delay characteristic and information regarding each cell layout pattern are stored in a mutually referable state. That is, the delay data includes a plurality of cells A1 to A3.
..A plurality of cells A1 to A3 having corresponding signal delay data and corresponding thereto
Each cell layout pattern can be referenced.

Therefore, when the designer of the integrated circuit layout changes the output signal delay characteristic of the cell, the cell layout pattern of the cell having the desired signal delay characteristic, for example, the desired output delay characteristic can be easily obtained.

Further, in the present invention, the information on each occupied shape and the information on the input / output terminal position, which are common to the cells in the cell group, are used as cell group layout information from the cell layout pattern for each cell. By providing them independently, wiring between cells can be performed at an earlier stage of integrated circuit layout design. Therefore, it is also possible to obtain the degree of signal delay of each wiring based on the actual wiring length before selecting a cell having a more suitable signal delay characteristic in the cell group.

In the above description, the signal delay characteristic of the output is taken as an example of the condition for the designer to select the cell, but the present invention is not limited to this, and a general signal delay characteristic is used. May be

Further, in FIG. 1, the delay data and the layout data A1 to A3 ... Are integrally stored in the cell group of the cell A.
The present invention is not limited to this. For example, as the information of the cell group such as the cell A, only the signal delay characteristics of individual cells of the cell group, for example, the signal delay characteristics and the address storing the cell layout pattern of the individual cells are integrated. It may be in a stored form. That is, some kind of correlation is made, or information about the signal delay characteristics for each cell forming the cell group and information about the cell layout pattern are stored by using some sort of relayable information. I wish I had it.

Although the present invention is not limited to this, for example, the signal delay characteristic serving as a reference for selecting a specific cell in the cell group is obtained by a predetermined default value generating means. It may be a value.
For example, at the time of initial design of an integrated circuit layout pattern, it is preferable to omit the design work of deciding the setting value of the signal delay characteristic for selecting one of the cells in the cell group. In such a case, according to the default value as described above, it is possible to omit the design work related to such a set value, and it is possible to efficiently perform the entire design.

[0039]

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 2 is a circuit diagram C for designing an integrated circuit according to the first and second embodiments to which the first and second inventions of the present application are applied.
It is a block diagram which shows the hardware constitutions of AD device.

As shown in FIG. 2, the hardware of the CAD device for designing an integrated circuit is mainly a CPU.
(Central processing unit) 50 and main storage device 52
A hard disk device 54 and an optical disk device 56.
A floppy disk device 58, an input / output device 60,
The keyboard 62, a CRT (cathode ray tube) controller 64a, a CRT 64b, and a system bus 70 are included.

The CPU 50 executes the program modules and the like according to the present embodiment on the main storage device 52 read from the hard disk device 54. The hard disk device 54 stores the program module according to the present embodiment, the cell library data described above with reference to FIG. 1, and the like, and is read to the main storage device 52 as necessary. It is like this. The optical disk device 56 is used to back up program modules and various data stored in the hard disk device 54. The floppy disk device 58 is used to transfer various program modules and data to and from other computer systems.

The input / output device 60 is connected to an input device such as a mouse not shown in FIG.
The keyboard 62 is used for operating the CAD device when designing an integrated circuit layout. Also, the keyboard 6
2 is also used when setting various data. The CRT control device 64a is a bit map display device, and is a circuit diagram and an integrated circuit layout of a circuit to be incorporated in an integrated circuit, which is designed by a designer using the CAD device for designing the integrated circuit, in addition to characters such as numbers. The CRT
64b can be displayed.

The system bus 70 is connected to the CP
U50, the main memory device 52, the hard disk device 54, the optical disk device 56, the floppy disk device 58, the input / output device 60, the keyboard 62, and the CRT control device 64a when transferring data or the like. It is used.

FIG. 3 is a diagram showing the data structure of the cell library of the first embodiment.

In the first embodiment, the cell library having the structure shown in FIG. 1 is stored in the data structure shown in FIG. In the cell library of this embodiment, fixed-length data of a total of 10 cell groups, that is, cells A to T, are stored at consecutive addresses. For each cell group, for example, cell A, circuit diagram data, logic data, APR data, delay data, and layout data A1 to A10 are stored at addresses. The data for each of the cell groups is the same as that described above with reference to FIG.

As described above, in the first embodiment,
Up to 10 cells included in each cell group
Although it is possible to store data of individual layout patterns, regarding the cell group of the cell A, in the following description, it is assumed that only the data of three cells, that is, cells A1 to A3 are stored. To do. Also, cells A4 to A
It is assumed that the storage area of the portion corresponding to 10 is blank.

FIG. 4 is a graph showing the delay data of the first and second embodiments.

In FIG. 4, as an example, the delay characteristics of the cell A1, the cell A2, and the cell A3 in the cell group of the cell A are shown by broken lines A1 to A3, respectively. In the graph of FIG. 4, the horizontal axis represents cells A1 to A3.
It is the magnitude of the load connected to the output of (cell group of cell A), that is, the external load value, and the horizontal axis is the degree of the signal delay of the output, that is, the delay value. Both the external load value and the delay value are the number of units. Also, this Figure 4
The rectangular area in each cell is located in which cell A1 to A3 as shown in A1 to A3 written in each rectangular area.
Indicates whether to select.

As described above, in the first and second embodiments, the magnitude of the load connected to the output of the cell group of the corresponding cell A, that is, the external load value is determined, and the delay value of the output is determined. When is determined, which cell A1 to A3 in the cell group of the cell A to be used is automatically selected by the predetermined layout editing means based on this.

FIG. 5 is a diagram showing the data structure of the cell library of the CAD device for integrated circuit design of the second embodiment to which the first and second inventions of the present application are applied.

In the second embodiment, the CAD device for designing an integrated circuit having the cell library as shown in FIG. 5 is constructed on the hardware as shown in FIG. In the second embodiment, with respect to the data of each cell group, for example, the cell A, the layout data of the cells A1 to A10 in the cell group are not integrated, and the addresses A1 to A1 shown in FIG. As indicated by the address A10, each layout data A
Addresses where 1 to 10 are stored are stored.
In the second embodiment, the layout data A1 to A10 are not integrated with the data of the cell group in this way and are indirectly specified. Therefore, each of the layout data A1 to A10 is specified. The data length of can be made variable.

As described above, in the second embodiment, for each cell group, data of a cell layout pattern of a maximum of 10 cells included in the cell group can be stored. However, in the following description of the cell group of the cell A, it is assumed that data regarding three cells, that is, cells A1 to A3 is stored.

FIG. 6 is a symbol diagram for creating a circuit diagram showing the cell A of the cell group and the cells A1 to A10 in the cell group of the cell A. The graphic information of this symbol is stored in the circuit diagram data of FIG.

The diagram shown in FIG. 7 shows the cell A in the cell group and the cells A1 to A in the cell group of the cell A.
11 is a truth table showing the logic of 10. As shown in FIG. 7, the cell A and the cells A1 to A10 are NAND gates. Information indicating this logic is stored in the logic data in FIG.

In the following description, the integrated circuit to be designed in the second embodiment is G / A. Further, in the wiring pattern between the transistors of the basic cell shown in each of FIGS. 8 to 10 described later,
The input and output terminals are shown by the "O" mark and the symbols A, B, Y, V and G, and are stored as the data of the cell A together with the APR data of FIG.

In addition, a total of 6 shown in FIGS.
Individual regions, that is, regions Aa to Ac and Ba to Bc are shown, which are basic cells. In the regions Aa to Ac, P channel MOS (metal oxide se)
miconductor) A transistor is built in. N-channel MOS transistors are built in the regions Ba to Bc. The cell layout pattern of each of these MOS transistors and the wiring connecting these MOS transistors and the input / output terminals is stored in each of the layout data A1 to A3 of FIG.

FIG. 8 is a wiring pattern diagram of the cell A1 designed in the second embodiment.

In FIG. 8, the wiring pattern between the transistors of the basic cell, which is determined by the layout data A1 of the cell A1, is shown together with the layout of the basic cell which is built for easy understanding. In FIG. 8, NAND gates are formed in the regions Aa and Ba and are connected to the output Y. Further, the areas Ab, Ac, Bb and Bc are unused areas.

FIG. 9 shows the wiring pattern of the cell A2 designed in the second embodiment as in FIG.

In FIG. 9, the areas Aa and Ba
In, a NAND gate is built in. Area A
Inverters are built in b and Bb, and the area Ac
And Bc also has built-in inverter. The cell A
At 2, the output of the NAND gate is input to an inverter connected in series, and the output of the inverter connected in series is connected to the output Y. Areas Aa and B
The output drive capability of the inverter built in the regions Ac and Bc is larger than the output drive capability of the NAND gate at a. Therefore, the output drive capacity of the cell A2 shown in FIG. 9 is larger than the output drive capacity of the cell A1.

FIG. 10 is a wiring pattern diagram of the cell A3 designed in the second embodiment.

In FIG. 10, the wiring pattern determined by the layout data A3 of the cell group of the cell A of FIG. 5 is shown similarly to FIG. By forming the wiring as shown in FIG. 10, NAND gates are formed in the regions Aa and Ba. Further, inverters are built in the areas Ab and Bb. In the areas Ac and Bc, the P channel MO
Two S-transistors in parallel, N-channel MO
An inverter having two S-transistors in parallel and a larger output drive capability is built in.

Therefore, as compared with the output drive capability of the inverters built in the areas Ac and Bc of the cell A2 of FIG. 9, the area Ac of the cell A3 of FIG.
And the drive capacity of the inverter built into Bc is larger. Therefore, the output drive capability of the entire cell A3 is the same as that of the entire cell A2 or the cell A2.
It is larger than the total output drive capacity of one cell.

FIG. 11 is a diagram showing APR data of cell A.

In FIG. 11, the basic cell occupying shape and the terminal position, which are determined by the APR data of the cell A, are shown together with the layout of the basic cell which is built for easy understanding.

As described above, the first embodiment and the second embodiment
In the embodiment, in cells in the same cell group,
The same cell layout pattern is occupied by one piece of APR data, and the positions of input / output terminals are also the same. or,
With respect to a plurality of cells in such a cell group, cells having different output drive capabilities can be realized by respective layout data.

In particular, in the first and second embodiments, by using the APR data, the occupied shape of each cell and the arrangement of input / output terminals are first determined, and the degree of signal delay according to the actual wiring length is used. , A cell having a more suitable signal delay characteristic can be automatically selected from the corresponding cell group. Therefore, by setting a required signal delay characteristic or using a default value when creating a circuit, it is possible to create a circuit suitable for the purpose without performing a tentative wiring simulation.

[0069]

As described above, according to the present invention, the burden on the designer can be further reduced and the TAT can be further reduced by reducing the dependence of the selection of cells to be used on the signal delay characteristics.
It is possible to obtain an excellent effect that can shorten.

[Brief description of drawings]

FIG. 1 is a diagram showing the gist of a first invention and a second invention of the present application.

FIG. 2 is a first application of the first invention and the second invention of the present application.
FIG. 3 is a block diagram showing a hardware configuration used in a CAD device for designing an integrated circuit according to the first and second embodiments.

FIG. 3 is a diagram showing the data structure of the cell library of the first embodiment.

FIG. 4 is a graph showing delay data used in the first and second embodiments.

FIG. 5 is a diagram showing a data structure of a cell library used in the second embodiment.

FIG. 6 is a symbol diagram for making a circuit diagram of a cell used in the first embodiment and the second embodiment.

FIG. 7 is a diagram showing a truth table of the cells of the first embodiment and the second embodiment.

FIG. 8 is a diagram showing a wiring pattern of a cell A1 of a cell group of the cell A used in the second embodiment.

FIG. 9 is a diagram showing a wiring pattern of a cell A2 of the cell group of the cell A.

FIG. 10 is a diagram showing a wiring pattern of a cell A3 of the cell group of the cell A.

FIG. 11 is a diagram showing a basic cell occupation shape and terminal positions of APR data of the cell group of the cell A.

FIG. 12 is a diagram showing a data structure of a cell library of a conventional CAD device for integrated circuit design.

FIG. 13 is a graph showing a delay characteristic of a cell A designed by the conventional CAD device for designing an integrated circuit.

FIG. 14 is a graph showing delay characteristics of a cell A ′ designed by the conventional CAD device for designing an integrated circuit.

[Explanation of symbols]

 50 ... CPU 52 ... Main storage device 54 ... Hard disk device 56 ... Optical disk device 58 ... Floppy disk device 60 ... Input / output device 62 ... Keyboard 64a ... CRT control device 64b ... CRT 70 ... System bus A, B ... Input Y ... Output V … Power supply G… Ground 81… Wiring pattern 82… Contact pattern 83… Occupied shape

Claims (3)

[Claims] 1. An integrated circuit design method for designing an integrated circuit layout pattern using pre-registered cells, wherein the input and output have the same logical relationship, and the occupied shape and input / output of the cell layout pattern. With respect to a plurality of cells having the same terminal position and different signal delay characteristics, which are regarded as a cell group, the cell based on the information on the occupied shape of the cell layout pattern of the cell group and the information on the input / output terminal position. Group layout information, information about each signal delay characteristic of each cell in the cell group, and information about each cell layout pattern of each cell are prepared in a mutually referable state using relational information. When designing an integrated circuit layout pattern, first, the cell group layout information The occupying shape of the cell to be incorporated and the input / output terminal are arranged, and the arranged cell is wired, and after the arrangement and wiring, the actual wiring length of each wiring between the cells is obtained, and the actual wiring is calculated. The degree of signal delay for each wiring is obtained from the length, and according to the degree of signal delay and the desired signal delay time,
Using the relational information and the information on the signal delay characteristics, select a cell having a more suitable signal delay characteristic in the cell group, and arrange using the information on the cell layout pattern of the selected cell. A method for designing an integrated circuit, which comprises designing a cell layout pattern of existing cells and performing an integrated circuit layout design. 2. A CAD device for integrated circuit design, in which information about a cell layout pattern of a cell is registered, and which uses the information of the cell to support integrated circuit design, has the same logical relationship between its input and output, Information on the occupied shape of the cell layout pattern of the cell group for a plurality of cells that have the same cell layout pattern occupying shape and the same input / output terminal position and differ only in their signal delay characteristics Cell group layout information based on the input / output terminal position information, information on signal delay characteristics of each cell in the cell group, and information on each cell layout pattern can be mutually referred to by using relational information. Cell layout pattern storing means for storing the cell layout pattern Using layout information, layout editing means capable of arranging the occupied shape of the arbitrary cell group and the input / output terminal at a desired position in the integrated circuit layout, and wiring between the arranged cells after the wiring. Of the wiring, the means for determining the actual wiring length of each wiring between the cells, the means for determining the degree of signal delay for each wiring from the actual wiring length, and the means for determining the degree of signal delay and the desired signal delay time Means for selecting a cell having a more suitable signal delay characteristic in the cell group, using relational information and information on the signal delay characteristic, and obtaining information on the cell layout pattern of the selected cell. A CAD device for integrated circuit design characterized by the above. 3. The method according to claim 2, further comprising a default value generating means for generating a default value of the signal delay characteristic, and wherein the layout editing means, when the desired signal delay characteristic is undefined. A CAD device for designing an integrated circuit, wherein the default value generated by the default value generating means is used.