JP3515997B2 - Programmable semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device for performing sequence control, and more particularly to a programmable semiconductor device whose function can be changed by an external program.

[0002]

2. Description of the Related Art When performing sequence control using a semiconductor device, it is necessary to set various functions of the semiconductor device in accordance with the purpose and application.

As semiconductor devices having simple functions, gate arrays and FPGAs (field programmable gate arrays) are already on the market.

In the gate array, the user combines the basic cells having simple functions with the CAD (co
It is possible to obtain a device that can perform a desired operation by being generated by a computer aided design and bringing the information to a semiconductor manufacturer.

Further, in the FPGA, the user can perform a desired operation by combining function blocks having a simple function, generating the connection information by a dedicated CAD, and writing it in the FPGA by a dedicated tool. We can get possible devices.

Further, as a method of constructing the hardware by a program from the outside, Japanese Patent Laid-Open No. 8-50428 can be used.
A "system for compiling algorithm language source code into hardware" described in Japanese Patent No. 5 and a "high-speed programmable logic controller" described in Japanese Patent Publication No. 8-5055483 are known.

[0007]

However, the conventional gate array and FPGA have the following problems.

1. In the gate array, since a sequence control processing circuit is realized by a combination of simple logic circuits, a huge amount of time is required for design. In addition, since manufacturing of a device that performs a desired operation after designing is performed by a semiconductor manufacturer, manufacturing requires a lot of time. Further, the user cannot change or modify the function after manufacturing.

2. In the case of the FPGA, although the function can be changed or modified after manufacturing, in order to realize the sequence control processing circuit by combining the function blocks having the simple functions, as in the case of the gate array, an enormous amount of time is required for the design.

3. A system for compiling the algorithm language source code described in Japanese Patent Publication No. 8-504285 into hardware is a PLD (programmamb).
In this system, a plurality of semiconductor devices are connected to each other in order to provide a desired function, and thus a decrease in operating speed is inevitable.

4. The high-speed programmable logic controller described in JP-A-8-505483 is a system that uses a microprocessor, and the instruction set of the microprocessor itself cannot be changed.
Extra resources are attached to achieve the desired functionality.

Therefore, the present invention has an object to obtain a semiconductor device capable of complicated control and function change by arranging a sequence control processing circuit whose function can be modified and changed by an external program operation in an array. To do.

[0013]

A programmable semiconductor device according to the present invention has a variable command input from the outside.
A variable instruction set, which is a set of force signals, is input, a controller unit that stores the input variable instruction set, and an input to be processed are input, and the variable instruction set is stored based on the variable instruction set stored in the controller unit. While providing a plurality of basic unit cells composed of a data path unit for performing a predetermined operation on a processing input and outputting a processing output, the input and output of each basic unit cell of the plurality of basic unit cells is provided. A switch control circuit for switching connection relations is provided.

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION A plurality of basic unit cells suitable for sequence processing are prepared on a semiconductor device, and a cascade input and a cascade output are further provided. Each basic unit cell is composed of a circuit having a control section and a data path section, and allows variable processing by a program.
Further, a software tool for changing the function of the basic unit cell and a software tool for the programmable space switch are prepared.

[0015]

1 is a block diagram showing the structure of a field programmable sequencer array (FPSA) to which the present invention is applied.

The field programmable sequencer array includes one instruction input signal line 1, one switch setting signal line 2, and four or more switch input / output signal lines 3.
And a plurality of basic unit cells (in the figure, BUC (Basi
c Unit Cell) 4), a switch control circuit 5, and an input / output control circuit 6.

As will be described in detail later, each basic unit cell 4 has a command input I, a cascade input C, and a processed input P as inputs, and outputs a cascade output and a processing output.
A command input is supplied to each basic unit cell 4, and the command input terminal, processed input terminal, cascade output terminal, and processing output terminal of each basic unit cell 4 are connected to the switch control circuit 5. Further, the switch setting signal is supplied to the switch control circuit 5 and the input / output control circuit 6. Further, the input / output signal is supplied to the input / output control circuit 6,
Is supplied to the switch control circuit 5, and the output from the switch control circuit 5 is supplied to the input / output control circuit 6.

[Basic Unit Cell] FIG. 2 shows a basic unit cell 4
3 is a block diagram showing the internal configuration of FIG. Basic unit cell 4
Is composed of a controller section 7 and a data path section 8.

The controller section 7 comprises a program control circuit 7a, a cascade control circuit 7b, a memory circuit 7c and a program counter circuit 7d.

The program control circuit 7a expands the serial command input signal input from the command input signal line 1 in parallel and stores it in the memory circuit 7c. The cascade control circuit 7b controls the processing of the basic cell according to an input signal from the other basic cell 4 and sends a cascade signal to another basic cell connected to the basic cell.
This cascade signal is a signal indicating carry information in each basic cell similar to carry-in and carry-out. The memory circuit 7c stores the instructions expanded in parallel by the program control circuit 7a. The program counter circuit 7d generates a memory address for sending the program stored in the memory circuit 7c to the data path unit 8 having an instruction decoder.

The data path unit 8 is composed of an arithmetic circuit 8a, a bit processing circuit 8b, a memory circuit 8c, a variable instruction decoder circuit 8d, a data latch circuit 8e, and an output control circuit 8f. The data path unit 8 is supplied from the controller unit 7 with an instruction signal to the variable instruction decoder circuit 8d and a control signal as a signal indicating a program state. The control signal from the controller unit 7 is a signal indicating the processing state for one instruction step.

The arithmetic circuit 8a performs arithmetic processing according to a program on the input to be processed supplied to the basic unit cell 4. The bit processing circuit 8b performs bit processing on an input to be processed according to a program. The memory circuit 8c is
It stores temporary data for bit processing and arithmetic processing, and data for the variable instruction decoder 8d. The variable instruction decoder circuit 8d decodes the instruction used in the target sequencer processing circuit constructed from the basic unit cells 4 alone or in combination, determines the processing of the input to be processed, and controls all circuits. Send a signal. That is, the control signal from the variable instruction decoder 8d is supplied to all the circuits of the data path unit 8, that is, the arithmetic circuit 8a, the bit processing circuit 8b, the memory circuit 8c, the data latch circuit 8e, and the output control circuit 8.
f and a status signal to the controller unit 7. The instruction decoding rule of the variable instruction decoder circuit 8d can be changed by the data stored in the memory circuit 8c. That is, the instruction set is changed by the micro programming method.

The data latch circuit 8e receives the input to be processed,
The variable instruction decoder circuit 8d temporarily holds until the processing is completed in the processing circuit selected. Output control circuit 8
f controls the output of the processed signal.

[Switch Control Circuit] FIG. 3 is a block diagram showing an internal configuration of the switch control circuit 5. The switch control circuit 5 includes a switch setting control circuit 5a, a switch setting memory 5b, and a matrix switch 5c.

The switch setting control circuit 5a is an external switch setting input for physically connecting the basic unit cell outputs 1 to n input to the matrix switch 5c and the basic unit cell inputs 1 to n output. Is read and written in the switch setting memory 5b. Switch setting memory 5b
Stores the setting information of the matrix switch 5c. The basic unit cell output is composed of the processed output and the cascade output, and the basic unit cell input is composed of the processed input and the cascade input.

[Input / Output Control Circuit] FIG. 4 is a block diagram showing the internal structure of the input / output control circuit 6. The input / output control circuit 6 is composed of a normal bidirectional circuit having a CMOS structure. The output signal from the switch control circuit 5 is wire-dot connected, that is, wired-OR connected to the input / output of the device via the output enable buffer 6a. Further, the output from the device is connected to the switch control circuit 5 via the buffer 6b. Output enable signals to all the input / output terminals are input from the switch setting input line 2 and set by the input decoder 6c.

Next, a procedure for realizing a sequence processing circuit having a desired function by using the above field programmable sequencer array will be described.

FIG. 5 is a flow chart showing a basic procedure for realizing a sequence processing circuit having a desired function. In the present embodiment, as shown in FIG. 5, the operation of the sequence processing circuit that the designer wants to realize is described by software (step 101), and the description can be realized by the instruction set of the basic unit cell 4. By converting the machine language code by the converting software (step 102) (step 103) and inputting an instruction to the basic unit cell 4, one basic unit cell 4 realizes a sequence processing circuit having a desired function. Functions as a sequence processing circuit.

The conversion software is a high-level language such as C language or C ++ language used for control or Verilog H.
It is software that generates a machine language code optimized for the instruction set of the basic unit cell 4 for realizing a processing function described in a hardware description language such as DL or VHDL. As the conversion software, generally commercially available compiler technology can be applied.

If the instruction set of the basic unit cell 4 is unsuitable for implementing the processing circuit, the instruction optimization software is used (step 206) as shown in the flow chart of FIG. An appropriate sequence processing circuit can be realized by estimating an appropriate instruction set of the basic unit cell 4 from the above (step 207) and programming the instruction set in the basic unit cell 4 (step 208). Note that steps 201 to 205 in FIG.
Since it corresponds to the processing shown in steps 101 to 105 of No. 1, description thereof will be omitted.

When the instruction set of the basic unit cell 4 is unsuitable for realizing a processing circuit, as an example of changing this to an optimum sequence processing, a product-sum operation using a combination of addition instructions is performed. An example is changing to a process that uses a sum operation instruction. By changing the instruction set in this way, the processing time is shortened. Further, as another example, when bit processing is performed, a process of shifting data by a combination of multiplexing instructions is changed to a process using a shift instruction. Also in this case, the processing time is shortened.

The instruction optimizing software is to realize a processing function described in a high-level language such as C language or C ++ language used for control or a hardware description language such as Verilog HDL or VHDL. It is software that estimates the optimum instruction set and generates the instruction set. As the instruction optimization software, for example, software to which artificial intelligence technology is applied can be used.

In the case of a complicated sequence processing circuit in which the desired sequence processing circuit cannot be realized by the basic unit cell 4, a plurality of basic unit cells 4 are used as shown in the flowchart of FIG. Implement sequence processing.

That is, 1. The sequence processing to be realized is described by software (step 301).

2. The sequence processing contents are divided into basic unit cell levels by the division software (step 30).
2).

3. The switch control circuit 5 is set to realize the connection between the basic unit cells necessary for the division processing (steps 303 and 304).

4. Machine code suitable for the instruction set to the basic unit cell for realizing the divided processing is generated by the conversion software similar to that shown in FIG. 6 (steps 305 and 306).

5. The machine language code for the basic unit cell and the setting code for the switch control circuit 5 are input (step 307).

6. Sequence processing is executed on a plurality of basic unit cells (step 308).

The above-mentioned software for dividing the basic unit cells into basic units has processing functions described in a high-level language such as C language or C ++ language used for control or a hardware description language such as Verilog HDL or VHDL. It is optimally divided into functional units that can be processed by cells, and information is generated for instruction set conversion software and basic unit inter-cell connection setting software. As the division software, for example, software to which the automatic placement and routing software used in LSI design is applied can be used.

The instruction set conversion software is a machine language optimized for the instruction set of the basic unit cell based on the information (definition of processing for each basic unit cell) generated by the division software for the basic unit cell. Generate code. The basic unit cell connection setting software generates a connection code between basic unit cells from the information (definition of the relationship of all basic unit cells) generated by the division software into basic unit cells. FIG. 8 is an explanatory diagram showing the connection between the basic unit cells via the switch control circuit 5.

Further, when the instruction set of the basic unit cell is not suitable for the required sequencer processing, the desired sequencer processing circuit can be realized by changing the instruction set of the basic unit cell as described above.

[0043]

As a basic unit cell, a logic circuit module capable of performing sequence control by programming from the outside is arranged, and a large number of such logic circuit modules are arranged in an array and the connections between the modules are controlled by space switch control. A semiconductor device having multiple functions can be constructed.

By preparing a plurality of basic unit cells suitable for sequence processing on a semiconductor device, a combination of simple logic circuits such as a gate array and a combination of function blocks having simple functions such as FPGA can be used. It can be designed in a significantly shorter period than when designing a sequence processing circuit.

By providing a plurality of basic unit cells by providing a cascade input and a cascade output, a complicated sequence processing circuit can be provided in a gate array or FP.
It can be designed in a significantly shorter period than GA.

Since the basic unit cell is composed of a circuit having a controller section and a data path section and variable processing by a program is possible, the function of the sequence processing circuit can be changed or modified in a short time.

By preparing a software tool for changing the function of the basic unit cell, the function of the basic unit cell can be changed or modified in a short period of time.

By preparing a software tool for the programmable space switch, the function of the semiconductor device can be changed or modified in a short time.

[Brief description of drawings]

FIG. 1 is a block diagram showing a structure of a field programmable sequencer array to which a semiconductor device of the present invention is applied.

FIG. 2 is a block diagram showing an internal configuration of a basic unit cell.

FIG. 3 is a block diagram showing an internal configuration of a switch control circuit 5.

FIG. 4 is a block diagram showing an internal configuration of the input / output control circuit 6.

FIG. 5 is a flowchart showing a basic procedure for realizing a sequence processing circuit having a desired function.

FIG. 6 is a flowchart showing processing when the instruction set of the basic unit cell is inappropriate for realizing the processing circuit.

FIG. 7 is a flowchart showing a process when a sequence process is realized by using a plurality of basic unit cells.

FIG. 8 is an explanatory diagram showing a connection between basic unit cells via a switch control circuit 5.

[Explanation of symbols]

1 ... Command input signal line, 2 ... Switch setting signal line, 3 ... Input / output signal line, 4 ... Basic unit cell, 5 ... Switch control circuit, 5a ... Switch setting control circuit, 5b ... Switch setting memory, 5c ... Matrix Switch, 6 ... I / O control circuit, 6a ... Buffer with output enable, 6b ... Buffer, 6c ... Input decode, 7 ... Controller section, 7a
... Program control circuit, 7b ... Cascade control circuit, 7
c ... memory circuit, 7d ... program counter circuit, 8 ...
Data path unit, 8a ... Arithmetic circuit, 8b ... Bit processing circuit, 8c ... Memory circuit, 8d ... Variable instruction decoder circuit,
8e ... Data latch circuit, 8f ... Output control circuit

─────────────────────────────────────────────────── ─── Continuation of the front page (72) Hiroto Yasuura, 1-2-2, Momochihama 2-chome, Sawara-ku, Fukuoka City Kyushu System Information Technology Laboratory (56) Reference JP-A-7-168610 (JP, A) JP-A-6-125067 (JP, A) JP-A-7-6080 (JP, A) JP-A-4-257945 (JP, A) JP-A-5-257512 (JP, A) JP-A-8-505483 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) G05B 19/02-19/05 H03K 19/098-19/23

Claims (4)

(57) [Claims] 1. A controller unit for parallelly expanding and storing a serial instruction input signal input from the outside, and an instruction input signal stored in the controller unit for an input to be processed input from the outside. A plurality of basic unit cells each of which is composed of a data path unit for performing a predetermined calculation based on the above and outputting a processing output, and the input and output connection relationships between the basic unit cells of the plurality of basic unit cells are externally connected. A programmable semiconductor device comprising one switch control circuit for performing switching control based on a switch setting input from the device and storing the setting information. 2. The controller unit of the basic unit cell expands a serial instruction input signal input from the outside in parallel.
The program control circuit and the other basic unit cell input signal
Control processing and connect to the basic unit cell.
Send a cascade signal to another basic unit cell
Cascade control circuit and instruction input expanded in parallel by the program control circuit
A memory circuit that stores a force signal and a program stored in the memory circuit.
Memory add for sending to the data path part having a memory
And a program counter circuit that generates a response
The programmable semiconductor device according to claim 1. 3. The data path part of the basic unit cell is a processor for a processed input supplied to the basic unit cell.
An arithmetic circuit for performing arithmetic processing according to the gram, and bit processing according to a program for the input to be processed.
A bit processing circuit which performs, is constructed from a single piece or a combination of the basic unit cell
The instruction used in the target sequencer processing circuit.
Variable instruction sequence that decodes and determines the processing of the input to be processed
Processing circuit and the processing target determined by the variable instruction sequencer processing circuit.
Output control circuit that outputs the processing result of the physical input as the processing output
Programmable semiconductor claim 2, characterized in that a road
device. 4. The switch control circuit connects the plurality of basic unit cell outputs to the basic unit cell inputs.
Continuing matrix switch and switch setting for the matrix switch from the outside.
A switch setting control circuit that takes in a constant input and the matrix that is taken in by the switch setting control circuit
Switch setting that stores the switch setting information
4. A constant memory according to claim 1.
A programmable semiconductor device according to.