JP4669781B2 - Processing equipment - Google Patents

Description

  The present invention relates to a processing apparatus including a reconfigurable circuit.

  Recently, wireless communications such as mobile phones, GPS, and VICS have become widespread, and the types of wireless devices are increasing. If these radios or their functions are all implemented by hardware, the cost and mounting area increase. Therefore, there is a concept of “software radio” that implements various functions by installing a circuit having general-purpose capability as hardware and switching software loaded thereon.

  Circuits that implement a software defined radio include an FPGA (Field Programmable Gate Array) and a DSP (Digital Signal Processor). Patent Document 1 proposes a method of reusing a circuit configuration by dynamically reconfiguring an FPGA. The type of circuit that can be dynamically changed is hereinafter referred to as a reconfigurable circuit.

  The FPGA can design circuit configuration relatively freely by writing circuit data after the LSI is manufactured, and is used for designing dedicated hardware. The FPGA includes a lookup table (LUT) for storing a truth table of a logic circuit, a basic cell composed of an output flip-flop, and a programmable wiring resource that connects the basic cells. In the FPGA, a target logical operation can be realized by writing data stored in the LUT and wiring data. However, when an LSI is designed using an FPGA, the mounting area is very large and the cost is high compared to an ASIC (Application Specific IC) design. Thus, a method has been proposed in which the circuit configuration is reused by dynamically configuring the FPGA (see, for example, Patent Document 1).

In a reconfigurable circuit that dynamically configures a logic circuit operation function and a connection between logic circuits, it is common that an operation processing bit number of the logic circuit is equal to a bit number of one address of the memory ( For example, see Patent Document 2).
Japanese Patent Laid-Open No. 10-256383 JP 2005-276854 A

  For example, in satellite broadcasting, image quality may be adjusted by switching broadcast modes depending on the season. In the satellite broadcast receiver, a plurality of circuits are built in hardware for each broadcast mode in advance, and the circuit is switched by a selector according to the broadcast mode for reception. Therefore, the other broadcast mode circuits of the receiver are idle during that time. When switching and using multiple dedicated circuits, such as mode switching, and the switching interval is relatively long, instead of creating multiple dedicated circuits, the LSI can be reconfigured instantaneously at the time of switching. The structure can be simplified and versatility can be improved, and at the same time the mounting cost can be reduced. In order to meet such needs, the manufacturing industry has become increasingly interested in dynamically reconfigurable LSIs. In particular, LSIs mounted on mobile terminals such as mobile phones and PDAs (Personal Digital Assistants) need to be miniaturized. If LSIs can be dynamically reconfigured and functions can be switched appropriately according to the application, The mounting area can be kept small.

  The FPGA has a high degree of design freedom in circuit configuration and is general-purpose. On the other hand, in order to enable connection between all the basic cells, it is necessary to include a large number of switches and a control circuit for controlling ON / OFF of the switches. This inevitably increases the mounting area of the control circuit. Moreover, since a complicated wiring pattern is used for connection between basic cells, the wiring tends to be long. Furthermore, the delay is increased because of the structure in which many switches are connected to one wiring. For this reason, FPGA based LSIs are often used only for trial manufacture and experiments, and are not suitable for mass production in view of mounting efficiency and performance cost. Furthermore, in the LSI based on the FPGA, it is necessary to send setting data to a large number of basic cells of the LUT method, so that it takes a considerable time to configure the circuit. For this reason, FPGA LSIs are not suitable for applications that require instantaneous switching of the circuit configuration.

  In order to solve these problems, in recent years, a reconfigurable processor using a multi-functional element called ALU (Arithmetic Logic Unit) having a plurality of basic arithmetic functions has been developed. In the reconfigurable processor, the command data is set to control the arithmetic function configuration and the connection part of the ALU circuit, so that the desired arithmetic processing circuit can be realized as a whole. Command data is generally created based on the data flow called DFG (Data Flow Graph) created from a source program written in a high-level programming language such as C language.

  As shown in FIG. 11, in a processor having a conventional memory configuration (see Patent Document 2), the number of arithmetic processing bits of the ALU is equal to the number of bits of one address of the memory, and the input / output data of the ALU is stored as it is. It was. For this reason, when the number of effective bits of the input / output data of the ALU is small, the upper bits that are originally unnecessary are also stored in the memory, and the memory is used wastefully. In particular, if the number of ALU processing bits is increased to, for example, 32 bits or even 64 bits, the memory that is wasted is increased.

  The present invention has been made in view of such circumstances, and an object thereof is to provide a processing apparatus including a reconfigurable circuit that contributes to a reduction in circuit scale.

  In order to achieve the above object, a processing device according to a first aspect of the present invention includes an arithmetic unit including a plurality of logic circuits each capable of selectively executing a plurality of arithmetic logic operation functions, In a processing apparatus including a reconfigurable circuit comprising a connection unit that holds a connection relationship between logic circuits, a storage unit that stores data used in the logic circuit, and a valid bit of data stored in the storage unit Divided storage means for dividing the data into a plurality of portions having the number of bits of the memory word and storing the data in a plurality of memory words when the number exceeds the number of bits of the memory word specified by one address of the storage means When the data stored by being divided into a plurality of memory words by the divided storage means is read from the plurality of memory words, the data of the original number of bits Characterized in that it comprises a coupling reading means for restoring, the.

  A processing device according to a second aspect of the present invention is a processing unit comprising a plurality of logic circuits each capable of selectively executing a plurality of arithmetic logic operation functions, and a connection relationship between the plurality of logic circuits. In a processing apparatus including a reconfigurable circuit including a connection unit that holds the data, a storage unit that stores data used in the logic circuit, and the number of effective bits of the data stored in the storage unit is 1 of the storage unit. If the number of bits of the memory word specified by the address does not exceed, the degenerate storage means that can restore the data and change the number of bits to be equal to or less than the number of bits of the memory word and store in the memory, and the degenerate storage means When reading the stored data after changing the number of bits to the number of bits of the memory word or less, the data is restored in accordance with the number of input bits of the logic circuit. Characterized in that it and a extended reading means.

  A processing apparatus according to a third aspect of the present invention includes the storage unit, the divided storage unit, the concatenated reading unit, the degenerate storage unit, and the extended reading unit.

  Further, the number of bits of a memory word specified by one address of the storage means for storing data used in the logic circuit is smaller than the number of bits of data processed in the logic circuit.

  Preferably, the divided storage means has a limited storage area for storing each of the data divided into a plurality of portions having the number of bits of the memory word of the storage means according to the bit position in the original data. It is characterized by that.

  In particular, the divided storage means or the degenerate storage means limits the number of data output from the arithmetic unit according to the number of effective bits of the data.

  In particular, the concatenated reading unit or the extended reading unit limits the number of data input to the arithmetic unit according to the number of effective bits of the data.

  Further, the divided storage means or the degenerate storage means may prevent the total number of memory words to be used from exceeding the number of memory words that can be simultaneously written according to the number of effective bits of each data output from the arithmetic unit. In addition, the number of data output from the arithmetic unit at the same time is limited.

  Still further, the concatenated reading means or the extended reading means may prevent the total number of memory words used according to the number of valid bits of each data input to the arithmetic unit from exceeding the number of memory words that can be read simultaneously. In addition, the number of data input to the arithmetic unit at the same time is limited.

  Preferably, the divided storage unit or the degenerate storage unit limits the number of data output from the calculation unit according to the number of effective bits of the data, or further outputs each of the data output from the calculation unit. The number of data simultaneously output from the arithmetic unit is limited so that the total number of memory words used according to the number of valid bits of data does not exceed the number of simultaneously writeable memory words, and the concatenated reading means Alternatively, the extended reading means limits the number of data input to the calculation unit according to the number of effective bits of the data, or further uses the data according to the number of effective bits of each data input to the calculation unit. The number of data to be simultaneously input to the arithmetic unit is limited so that the total number of memory words does not exceed the number of memory words that can be read simultaneously. To.

  A processing device according to a fourth aspect of the present invention is any one of the processing devices, comprising: a plurality of arithmetic logic operation functions selectively executed in the plurality of logic circuits; and a plurality of logic circuits between the plurality of logic circuits. In the generation of setting data for setting the connection relation and controlling the operation of the reconfigurable circuit, the input of the logic circuit is based on a program that describes the intended arithmetic processing executed by the plurality of logical arithmetic circuits. The setting data is generated by determining the number of valid bits of the output data.

  According to the processing apparatus of the present invention, since it is possible to store the memory with the number of bits closer to the effective number of data than in the conventional reconfigurable circuit, it is possible to use the memory efficiently and to reduce the necessary memory capacity. Tesumu. And the circuit scale can be reduced by reducing the memory capacity.

  An embodiment of a processing apparatus according to the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a processing apparatus including a reconfigurable circuit according to an embodiment of the present invention. As shown in FIG. 1, the processing apparatus 10 includes an integrated circuit device 26. The integrated circuit device 26 has a function that makes it possible to reconfigure the circuit configuration. The integrated circuit device 26 is configured as one chip, and includes a reconfigurable circuit 1, a setting unit 14, a control unit 18, an internal state holding circuit 20, an output circuit 22, and a path unit 24. The reconfigurable circuit 1 can change the function by changing the setting.

  The setting unit 14 includes a first setting unit 14a, a second setting unit 14b, a third setting unit 14c, a fourth setting unit 14d, and a selector 16, and configures an intended circuit in the reconfigurable circuit 1. The setting data 40 is supplied. The path unit 24 functions as a feedback path, and connects the output of the reconfigurable circuit 1 to the input of the reconfigurable circuit 1. The internal state holding circuit 20 and the output circuit 22 are configured by a sequential circuit such as a data flip-flop (D-FF) or a memory, for example, and receive the output of the reconfigurable circuit 1. The internal state holding circuit 20 is connected to the path unit 24. The internal state holding circuit 20 includes a storage unit 4 that stores data used in the reconfigurable circuit 1. The reconfigurable circuit 1 is configured as a combinational circuit or a sequential circuit including state holding such as D-FF.

  FIG. 2 is a diagram illustrating a configuration example of the reconfigurable circuit 1 using an ALU array. As shown in FIG. 2, the reconfigurable circuit 1 has a structure including a plurality of sets of logic circuits (ALU) 2 including arithmetic logic units and the like whose functions can be changed. It is provided between the bodies and has at least one connection part 3 capable of selectively establishing the connection of the ALU 2 between the aggregates.

  In the reconfigurable circuit 1, a plurality of ALUs 2 capable of selectively executing an arithmetic function are arranged in a matrix form. In the example of FIG. 2, an ALU array of X stages and Y columns is configured and arranged in each stage. A plurality of ALUs 2 constitute an aggregate, and the processing result in the upstream aggregate is delivered to the downstream aggregate according to the connection selectively established in the connection unit 3. Data transfer between the logic circuits from the upper stage to the lower stage is determined to which ALU 2 in the lower stage the data is transferred by setting a connection data set in a connection switch that switches connection between the logic circuits. During operation, arithmetic processing is performed according to the configuration information and the result is output.

  The function of each logic circuit (ALU) 2 and the connection relationship between the logic circuits are set based on setting data 40 supplied by the setting unit 14 shown in FIG. The setting data 40 is generated by the following procedure.

  A program 36 to be realized by the integrated circuit device 26 is held in the setting storage unit 34. The program 36 describes a signal processing circuit or a signal processing algorithm in a high-level language such as C language. The compiling unit 30 compiles the program 36 stored in the setting storage unit 34, converts it into a data flow graph (DFG) 38, and stores it in the setting storage unit 34. The data flow graph 38 is a graph structure representing operations or data flow from input data to output data by input variables and constants. Here, the compiling unit 30 generates the data flow graph 38 according to the connection limitation of the aggregate of ALUs 2 in the reconfigurable circuit 1.

  The setting data generation unit 32 generates setting data 40 from the data flow graph 38. The setting data 40 is data for mapping the data flow graph 38 to the reconfigurable circuit 1 and defines the function of the ALU 2 in the reconfigurable circuit 1 and the connection relationship between the logic circuits.

(Embodiment 1)
FIG. 3 is a diagram showing an example of the configuration of the storage unit 4 that stores data used by the reconfigurable circuit 1 in the processing apparatus 10 according to the present invention. In the present embodiment, the ALU array of the reconfigurable circuit 1 has an arithmetic processing bit number of 32 bits. The storage unit 4 includes two systems of RAMs 5a and 5b each having a 16-bit memory word designated by one address as the memory 5. The storage unit 4 stores the output from the ALU having the number of arithmetic processing bits of 32 bits in a RAM having a memory word of 1 address as 16 bits. In the figure, a thick line represents a 32-bit data line, and a thin line represents a 16-bit data line.

  The storage unit 4 includes a register 7a that receives the 32-bit data of the reconfigurable circuit 1 as it is, and a register 7b that receives the lower 16 bits of the 32-bit data. The data in the 32-bit register 7a is input to a selection circuit (MUX) 6a that selects upper 16-bit data and lower 16-bit data. The register 7b that receives the lower 16 bits is connected to the RAM 5b.

  On the read side of the RAMs 5a and 5b, registers 7c and 7d, a bit expansion circuit 8, a selection circuit 6b, and synthesis circuits 9a and 9b are provided. The bit expansion circuit 8 expands the MSB (most significant bit) of the data read from the RAM 5b to generate upper 16 bits. The selection circuit 6b selects the output of the bit extension circuit 8 and the data of the RAM 5a. The synthesizing circuit 9a generates the original data with the data in the RAM 5a as the lower 16 bits and the 16 bits obtained by extending the MSB as the upper 16 bits. The synthesizing circuit 9b generates original data with the data of the RAM 5b as the lower bits and the output of the selection circuit 6b as the upper 16 bits.

  Next, the operation of the storage unit 4 will be described. As shown in FIG. 3, the storage unit 4 has a pair of two RAMs 5a and 5b, and if the number of effective bits of output data from the ALU 2 is 17 bits or more, the upper and lower parts are respectively stored in the pair of two RAMs 5a and 5b. Store. That is, the selection circuit 6a selects the upper 16 bits of the data in the register 7a and stores it in the RAM 5a. The lower 16 bits are stored in the RAM 5b. Of the pair of RAMs 5a and 5b constituting the memory 5, the RAM 5a is for the upper level and the RAM 5b is for the lower level.

  The divided and stored data is read out from the RAMs 5a and 5b for the upper 16 bits and the lower 16 bits, respectively, and is coupled to the ALU 2 as the original 32-bit data. The selection circuit 6b selects the data in the RAM 5a and sets it as the upper 16 bits of the synthesis circuit 9b. The lower 16 bits of the synthesis circuit 9b are the RAM 5b data (register 7d data). In this way, the 32-bit data divided and stored in the RAMs 5a and 5b is read out by being combined with the original 32-bit data by the synthesis circuit 9b.

  When the number of effective bits output from the ALU is 16 bits or less, only the lower 16 bits of 32 bits are stored in the RAM 5a or RAM 5b. At that time, the data may be stored in any of the RAMs 5a and 5b. For example, continuous data of 16 bits or less is stored in the RAM with the larger unused area of the RAM 5a and RAM 5b. When the lower 16 bits are stored in the RAM 5a, the selection circuit 6a selects the lower 16 bits and stores them in the RAM 5a. At that time, the RAM 5b may store different data of 16 bits or less. When only the lower 16 bits are stored in the RAM 5b, the lower 16 bits from the register 7b are stored in the RAM 5b. At that time, the RAM 5a may store different data of 16 bits or less.

  When data having only the lower 16 bits stored therein is read from the RAM 5a or 5b, the data is bit-extended and input to the ALU 2 as the original 32-bit data. That is, when the lower 16-bit data stored in the RAM 5a is read, the data in the RAM 5a (data in the register 7c) is set as the lower 16 bits in the synthesis circuit 9a, and the 16 bits obtained by extending the MSB of the register 7c are set as the upper 16 bits. Generate data for

  The method of extending the lower 16 bits MSB differs depending on the data type. For example, when 16-bit data is a code such as a character code, the bit extended to the upper 16 bits may always be 0. When the data is an integer type and the negative number is 2's complement notation, the bit extended to the upper 16 bits needs to be the same bit as the MSB of the lower 16 bits. That is, in the case of a positive number, 0 is padded to upper 16 bits, and in the case of a negative number, 1 is padded to upper 16 bits. In ALU2, if the upper 16 bits are not used for anything other than the integer type, the bit extension circuit 8 may always perform the same processing as the integer type.

  When reading only the lower 16 bits of data stored in the RAM 5b, the bit expansion circuit 8 expands the MSB (most significant bit) of the data read from the RAM 5b to generate upper 16 bits. The selection circuit 6b selects the output of the bit expansion circuit 8 and sets the higher 16 bits of the synthesis circuit 9b. The synthesizing circuit 9b generates original data using the data in the RAM 5b (data in the register 7d) as the lower 16 bits and the output of the selection circuit 6b (the upper 16 bits generated by the bit expansion circuit 8) as the upper 16 bits.

  In this way, the data in which only the lower 16 bits are stored in the RAM 5a or 5b is expanded and read by the combining circuit 9a or the combining circuit 9b to the original 32-bit data.

  When the number of effective bits of output data from the ALU 2 is 16 bits or less, the upper 16-bit data unnecessary in the configuration of the conventional storage unit 4a shown in FIG. 11 is also stored in the memory. Storage of unnecessary data is reduced by the storage unit 4, and data can be stored in the memory 5 more efficiently than in the past. As a result, the circuit scale can be reduced by reducing the memory capacity.

  In FIG. 3, the RAM 5a stores 16-bit or 32-bit upper data, and the RAM 5b stores 16-bit or 32-bit lower data. Therefore, in the input to the memory 5, the left RAM 5a is provided with a selection circuit (MUX) 6a for selecting whether the upper 16 bits or the lower 16 bits, but lower data is always written in the right RAM 5b. The selection circuit is not necessary.

  In the output from the storage unit 4, the upper 16 bits that are output from the left RAM 5a when the original data is 32-bit data and the output from the right RAM 5b when the original data is 16 bits are bits. A selection circuit 6b that selects the expanded upper 16 bits, and an output from the selection circuit 6b as upper 16 bits, and a synthesis circuit 9b that performs bit integration with the output from the right RAM 5b as lower 16 bits to generate 32-bit data. Is equipped. In addition, when lower 16-bit data is stored in the left RAM 5a, there is provided a synthesis circuit 9a that expands the output from the left RAM 5a to 32-bit data. Since the upper 16 bits of the combining circuit 9a are always 16-bit data obtained by bit-extending the output from the left RAM 5a, a selection circuit for selecting the upper 16 bits such as the selection circuit 6b is not necessary.

  FIG. 4 is a diagram showing a circuit configuration example from the ALU 2 to the memory 5 when the configuration of the storage unit 4 of FIG. 3 is used. Three ALUs 2 can access the pair of RAMs 5a and 5b in FIG. In order to allow both the upper 16 bits and the lower 16 bits to be input to the left RAM 5a, a 6 → 1 selection circuit (selecting one 16-bit data from a total of 6 ALUs 3 × upper and lower 2) ( MUX) 6c. Further, since only the lower 16 bits are input to the right RAM 5b, a 3 → 1 selection circuit (MUX) 6d for selecting one 16-bit data from a total of three ALUs 3 × lower ones is provided. Yes.

  When 6 → 1MUX 6c selects the upper 16 bits, 3 → 1 MUX 6d selects the lower 16 bits of the output of the same ALU. When 6 → 1MUX 6c selects the lower 16 bits, 3 → 1 MUX 6d may select the lower 16 bits of the output of a different ALU2. Therefore, the output from the three ALUs 2 is limited to two pieces of data having an effective bit number of 16 bits or less or one piece of data having 17 bits or more. The same applies to the input to the ALU 2. The number of valid bits of input data is limited to two data (types) of 16 bits or less or one data (type) of 17 bits or more. As described above, the input / output limit of the ALU 2 depends on the number of effective bits of data.

  The number of effective bits of the input / output data of the ALU 2 is determined based on a program 36 describing an intended arithmetic process executed by the reconfigurable circuit 1. When the intended arithmetic processing is described in C language, the number of effective bits can be determined by a variable type or a comment sentence. For example, if the variable type is int type (integer type), the effective bit number of the variable can be determined as 32 bits, and if the variable type is short type, the effective bit number can be determined as 16 bits. Then, when creating the setting data 40, the setting data generation unit 32 sets the setting data for storing the data in the RAMs 5a and 5b with the above-described restrictions from the number of effective bits based on the determination result of the input / output data of the ALU2. 40 is created.

  FIG. 5 shows a configuration of the storage unit 4 using a plurality of pairs of RAMs 5a, 5b, 5c, and 5d. The storage unit 4 in FIGS. 3 and 4 has a configuration using a pair of RAMs 5a and 5b, but may have a plurality of pairs of RAM configurations as shown in FIG. FIG. 5 shows a configuration using two pairs of RAMs 5a and 5b and RAMc and d. In this case, the number of effective bits of input / output data is four (types) of 16 bits or less, or two data of 17 bits or more. (Type) or one data (type) of 17 bits or more and one data (type) of 16 bits or less.

  When two pairs of RAMs are used like the storage unit shown in FIG. 5, the ALU2 of the reconfigurable circuit is divided into two, one accesses the left pair of RAMs 5a and 5b, and the other accesses the right pair. The RAMs 5c and 5d may be accessed. All ALUs 2 may be allowed to access any pair of RAMs 5a, 5b, 5c, 5d.

  In the present embodiment, the case where 32-bit data is divided into upper 16 bits and lower 16 bits and stored in the storage unit 4 has been described. However, the number of data bits and the number of bits stored in the storage unit 4 are 32 bits. It is not limited to 16 bits. The memory 5 only needs to be composed of a number of RAMs that can store the number of input / output bits of the ALU 2. For example, when the number of data bits is 16, the storage unit 4 can be divided and stored in two parts of 8 bits. In addition, when the data is 64 bits, the data may be divided into upper 32 bits and lower 32 bits and stored in the storage unit. The configuration for storing data in two parts, upper and lower, is the same as the configuration of FIGS.

  Furthermore, a configuration in which data is divided into many parts and stored in the storage unit is also possible. For example, 64-bit data can be divided into four portions of 16 bits and stored in the storage unit. In that case, data is stored in four 16-bit RAMs divided into four cases where the number of effective bits of data is 16 bits or less, 32 bits or less, 48 bits or less, and more than 48 bits.

  FIG. 6 shows an example of the configuration of the storage unit 4 when data output from the 64-bit ALU array is stored in four 16-bit RAMs. In FIG. 6, a white line represents a 64-bit data line, a thick line represents a 32-bit data line, and a thin line represents a 16-bit data line. The storage unit 4 in FIG. 6 is configured to perform the division in the storage unit 4 in FIG. 3 in two stages, and to perform expansion and synthesis in two stages.

  When the effective bits of 64-bit data exceed 32 bits, the data is divided into 16 bits and stored in four RAMs 5a, 5b, 5c, and 5d. When the valid bits of 64-bit data are 32 bits or less, only 64-bit lower 32-bit data is stored in RAMs 5a and 5b or RAMs 5c and 5d. Furthermore, when the number of valid bits of data is 16 bits or less, only the 64-bit least significant 16-bit data is stored in any of the RAMs 5a, 5b, 5c, or 5d.

  Note that the number of bits of the memory word specified by one address of the paired RAM may be non-uniform. For example, the RAM 5a may be 8 bits and the RAM 5b may be 24 bits. In that case, if the number of effective bits of data is 8 bits or less, it is stored in the RAM 5a or RAM 5b. If the effective bit number of the data is 9 bits or more and 24 bits or less, it is stored in the RAM 5b. Furthermore, if the number of valid bits of data is 25 bits or more, the data is stored as a pair in the RAM 5a and RAM 5b.

  FIG. 7 shows an example of the storage unit 4 in which the memory 5 is composed of three RAMs having different numbers of bits. In FIG. 7, a thick solid line represents a 32-bit data line, a thin solid line represents a 16-bit data line, and a dotted line represents an 8-bit data line. The ALU array of the reconfigurable circuit 1 has an arithmetic processing bit number of 32 bits. The storage unit 4 includes, as a memory 5, a RAM 5a having a 16-bit memory word specified by one address and RAMs 5e and 5f having an 8-bit memory word specified by one address. The storage unit 4 stores the output from the ALU having the number of arithmetic processing bits of 32 bits in the RAM 5a in which the memory word at one address is 16 bits and the 8-bit RAMs 5e and 5f.

  The storage unit 4 includes a register 7a that receives the 32-bit data of the reconfigurable circuit 1 as it is, a register 7b that receives the lower 16 bits of the 32-bit data, and a register 7c that receives the least significant 8 bits of the 32-bit data. Prepare. The data in the 32-bit register 7a is selected from upper 16-bit data (D1 and D2), central 16-bit data (D2 and D3) or lower 16-bit data (D3 and D4). Is input. The output of the selection circuit 6a is input to the RAM 5a.

  The register 7b that receives the lower 16 bits is input to a selection circuit (MUX) 6b that selects the upper 8 bits and the lower 8 bits of the 16 bits. The output of the selection circuit 6b is input to the RAM 5e. The register 7c that receives the least significant 8 bits is connected to the RAM 5f.

  On the reading side of the RAMs 5a, 5e and 5f, registers 7d, 7e, 7f, 7g and 7h, bit expansion circuits 8a, 8b and 8c, selection circuits 6c, 6d, 6e and 6f, and synthesis circuits 9a, 9b, 9c is provided. The bit extension circuit 8a generates 8 bits obtained by extending the MSB (most significant bit) of the 16-bit data (register 7d) read from the RAM 5a. The bit extension circuit 8b generates 8 bits by extending the MSB of the 8-bit data (register 7e) read from the RAM 5e. The bit extension circuit 8c generates 8 bits by extending the MSB of the 8-bit data (register 7f) read from the RAM 5f.

  The expansion circuit 7g expands the output of the bit expansion circuit 8b to double 16 bits. The expansion circuit 7h expands the output of the bit expansion circuit 8c to double 16 bits.

  The selection circuit 6c selects the data of the RAM 5a and the data of the enlargement circuit 7g to obtain the 16-bit data (D2 and D3) at the center of the synthesis circuit 9b. The selection circuit 6d selects the data of the RAM 5a and the data of the enlargement circuit 7g or 7h, and uses the data as the upper 16-bit data (D1 and D2) of the synthesis circuit 9c. The selection circuit 6e selects the output of the bit expansion circuit 8a and the output of the bit expansion circuit 8b, and sets it as the upper 8-bit data (D1) of the synthesis circuit 9b. The selection circuit 6f selects the data of the RAM 5e and the output of the bit expansion circuit 8c, and uses the lower 16 bits of the synthesis circuit 9c as the higher-order 8-bit data (D3).

  Next, the operation of the storage unit 4 will be described. As shown in FIG. 7, the storage unit 4 is a set of three RAMs 5a, 5e, and 5f. If the number of effective bits of output data from the ALU 2 is 25 bits or more, the set of three RAMs 5a, 5e, and 5f Divide and store. That is, the selection circuit 6a selects the upper 16 bits of the data in the register 7a and stores it in the RAM 5a. Of the lower 16 bits, the upper 8 bits are selected by the selection circuit 6b and stored in the RAM 5e. The least significant 8 bits are stored in the RAM 5f.

  The data stored with the effective number of bits divided into 24 bits or less is read out from the upper 5 bits and lower 8 bits of the upper 16 bits and lower 16 bits from the RAMs 5a, 5e, and 5f, respectively, and bit-combined to obtain the original 32 bits. Is input to the ALU 2 as the data. The selection circuit 6d selects the data in the RAM 5a and sets it as the upper 16 bits of the synthesis circuit 9c. The selection circuit 6f selects the data in the RAM 5e (the data in the register 7e), and sets the upper 8 bits of the lower 16 bits of the synthesis circuit 9c. The lower 8 bits (D4) of the lower 16 bits of the synthesis circuit 9c are used as the data of the RAM 5f (register 7f). Thus, the 32-bit data divided and stored in the RAMs 5a, 5e, and 5f is read out by being combined with the original 32-bit data by the synthesis circuit 9c.

  When the number of valid bits output from the ALU is 17 bits or more and 24 bits or less, the 16 bits data (D2 and D3) at the center of 32 bits are stored in the RAM 5a, and the least significant 8 bits data (D4) is stored. Store in the RAM 5e. That is, the selection circuit 6a selects the central 16 bits of the data in the register 7a and stores it in the RAM 5a. The least significant 8-bit data (D4) is selected from the register 7b by the selection circuit 6b and stored in the RAM 5e.

  The data divided and stored with the effective bit number being 17 bits or more and 24 bits or less is read out by being combined with the original 32-bit data by the synthesis circuit 9b. The selection circuit 6c selects the data in the RAM 5a (data in the register 7d) and uses it as 16-bit data (D2 and D3) in the center of 32 bits. The least significant 8 bits of the synthesis circuit 9b are data in the RAM 5e. The selection circuit 6e selects the output of the bit extension circuit 8a and sets it as the most significant 8-bit data of the synthesis circuit 9b.

  When the number of effective bits output from the ALU is 16 bits or less, only the lower 16 bits of 32 bits are stored in the RAM 5a or the RAMs 5e and 5f. For example, continuous data of 16 bits or less is stored in the RAM 5a, RAM 5e, and 5f with the larger unused area. When storing the lower 16 bits in the RAM 5a, the selection circuit 6a selects the lower 16 bits (D3 and D4) and stores them in the RAM 5a. At that time, the RAMs 5e and 5f may store different data of 16 bits or less. When only the lower 16 bits are stored in the RAMs 5e and 5f, the selection circuit 6b selects the upper 8 bits (D3) from the register 7b and stores them in the RAM 5e, and stores the lowest 8 bits (D4) from the register 7c in the RAM 5f. To do. At that time, the RAM 5a may store different data of 16 bits or less.

  When data having only the lower 16 bits stored therein is read from the RAM 5a or the RAMs 5e and 5f, the data is bit-extended and input to the ALU 2 as the original 32-bit data. That is, when reading the lower 16-bit data stored in the RAM 5a, the synthesizing circuit 9a sets the data in the RAM 5a (data in the register 7d) to the lower 16 bits, and the 8 bits obtained by extending the MSB of the register 7d is twice the upper 16 bits. To the original data.

  When reading the lower 16 bits stored in the RAM 5e and RAM 5f, the combining circuit 9c concatenates the read data. The least significant 8 bits are data read from the RAM 5f. The selection circuit 6f selects the data in the RAM 5e and sets it as the upper 16-bit data (D3) of the lower 16 bits. The bit expansion circuit 8b expands the MSB of the register 7e, and the expansion circuit 7g further expands to double 16 bits. The selection circuit 6d selects the data of the enlargement circuit 7g and sets it as the upper 16 bits of the synthesis circuit 9c.

  When the number of effective bits output from the ALU 2 is 8 bits or less, only the least significant 8 bits of 32 bits are stored in the RAM 5e or RAM 5f. The selection circuit 6b selects the least significant 8 bits and stores them in the RAM 5e, or stores the least significant 8 bits (represented by the register 7c) in the RAM 5f. Further, the lower 16 bits of 32 bits may be stored in the RAM 5a. In this case, it is the same as storage and reading when the number of effective bits is 16 bits or less.

  Data storing only the least significant 8 bits is expanded and read by the combining circuit 9b or 9c to the original 32 bits. When reading data in which only the least significant 8 bits are stored from the RAM 5e, the data of the enlargement circuit 7g is selected by the selection circuit 6c to be the center 16 bits. The selection circuit 6e selects the output of the bit expansion circuit 8b and sets it as the most significant 8 bits (D1) of the synthesis circuit 9b. The least significant 8 bits of the synthesis circuit 9b are data (represented by the register 7e) read from the RAM 5e.

  When reading data in which only the least significant 8 bits are stored from the RAM 5f, the selection circuit 6d selects the data of the expansion circuit 7h (the data obtained by doubling the output of the bit expansion circuit 8c) and combines the circuit 9c. Are the upper 16 bits. The selection circuit 6f selects the output of the bit expansion circuit 8c and sets it as the upper 8 bits (D3) of the lower 16 bits of the synthesis circuit 9c. The least significant 8 bits of the synthesis circuit 9c are data read from the RAM 5f (represented by the register 7f).

  The storage unit 4 in FIG. 7 can store the lower 8 bits in the RAM 5e or RAM 5f if the number of valid bits of the output data from the ALU 2 is 8 bits or less. If the number of valid bits is 9 bits or more and 16 bits or less, the lower 16 bits can be stored in the RAM 5a or RAM 5e + RAM 5f, and if it is 17 bits or more and 24 bits or less, the lower 24 bits can be stored in the RAM 5a + RAM 5e. . If it is 25 bits or more, 32 bits can be stored in the RAM 5a + RAM 5e + RAM 5f.

  The smaller the number of bits of RAM, the more efficient the use of RAM and the smaller the capacity of RAM. However, since the RAM peripheral circuit such as MUX and the number of set data increase, the best mode depends on the scale of the entire circuit and the system. I'm about to do it.

  3, 4, 6, and 7, the registers 7 a and 7 b are illustrated on the input side and output side of the memory 5 for easy understanding, but the registers are not data holding circuits but data lines. May be.

(Embodiment 2)
FIG. 8 is a diagram illustrating an example of a different configuration of the storage unit 4 that stores data used by the reconfigurable circuit 1 in the processing apparatus 10 according to the present invention. Similar to the storage unit 4 in FIG. 3, the output data from the ALU 2 having a 32-bit arithmetic processing bit number is stored in a RAM having a 16-bit memory word at one address. In the present embodiment, the ALU array of the reconfigurable circuit 1 has an arithmetic processing bit number of 32 bits.

  The storage unit 4 includes, as the memory 5, two RAMs each having a 16-bit memory word designated by one address. The storage unit 4 stores an output from the ALU 2 having a 32-bit arithmetic processing bit number in a RAM having a 16-bit memory word at one address. In the figure, a thick line represents a 32-bit data line, and a thin line represents a 16-bit data line.

  The storage unit 4 includes a register 7 that receives 32-bit data of the reconfigurable circuit 1, and a selection circuit 6 a that selects upper 16 bits and lower 16 bits of the register 7. The output of the selection circuit 6a is connected to the RAM 5a. The lower 16 bits of the register are connected to the RAM 5b.

  On the read side of the RAMs 5a and 5b, selection circuits 6b and 6e, a register 7e, a bit expansion circuit 8, and a synthesis circuit 9b are provided. The selection circuit 6e selects one memory word data in the RAM 5a and one memory word data in the RAM 5b and inputs the selected data to the register 7e. The register 7e is connected to the lower 16 bits of the synthesis circuit 9b. The bit expansion circuit 8 expands the MSB (most significant bit) of the data in the register 7e to generate upper 16 bits. The selection circuit 6b selects the output of the bit extension circuit 8 and the data of the RAM 5a. The synthesizing circuit 9b generates the original data with the data in the register 7e as the lower 16 bits and the output of the selection circuit 6b as the upper 16 bits.

  Next, the operation of the storage unit 4 will be described. As shown in FIG. 8, if two RAMs 5a and 5b are paired and the number of effective bits of output data from ALU2 is 17 bits or more, upper 16 bits and lower 16 bits are stored in a pair of two RAMs 5a and 5b. Store each one. That is, the selection circuit 6a selects the upper 16 bits of the register 7 and stores it in the RAM 5a. The lower 16 bits of the register 7 are stored in the RAM 5b. In this case, of the pair of RAMs 5a and 5b of the memory 5, the RAM 5a is for the upper level and the RAM 5b is for the lower level.

  The divided data stored in the upper 16 bits and lower 16 bits are read out from the RAMs 5a and 5b, bit-combined, and input to the ALU 2 as the original 32-bit data. The selection circuit 6b selects the data in the RAM 5a and sets it as the upper 16 bits of the synthesis circuit 9b. The selection circuit 6e selects the data in the RAM 5b and sets it in the register 7e. The data in the register 7e is the lower 16 bits of the synthesis circuit 9b. In this case, the output of the bit extension circuit 8 is not used. The upper 16 bits of the combining circuit 9b are data of the RAM 5a that is the output of the selection circuit 6b, and the lower 16 bits are data of the RAM 5b (data of the register 7e). In this way, the 32-bit data divided and stored in the RAMs 5a and 5b is read out by being combined with the original 32-bit data by the synthesis circuit 9b.

  When the number of effective bits output from the ALU 2 is 16 bits or less, only the lower 16 bits of 32 bits are stored in the RAM 5a or RAM 5b. At that time, the data may be stored in any of the RAMs 5a and 5b. For example, continuous data of 16 bits or less is stored in the RAM with the larger unused area of the RAM 5a and RAM 5b. When the lower 16 bits are stored in the RAM 5a, the selection circuit 6a selects the lower 16 bits of the register 7 and stores it in the RAM 5a. At that time, the RAM 5b is not used. When only the lower 16 bits are stored in the RAM 5b, the lower 16 bits from the register 7 are stored in the RAM 5b. At that time, the RAM 5a is not used.

  When data having only the lower 16 bits stored therein is read from the RAM 5a or 5b, the data is bit-extended and input to the ALU 2 as the original 32-bit data. That is, when reading the lower 16-bit data stored in the RAM 5a, the selection circuit 6e selects the data in the RAM 5a and sets it in the register 7e. The bit extension circuit 8 extends the MSB of the register 7e to generate upper 16 bits. The selection circuit 6b selects the output of the bit expansion circuit 8 and sets the higher 16 bits of the synthesis circuit 9b. The data in the register 7e (data in the RAM 5a) is the lower 16 bits of the synthesis circuit 9b. The synthesizing circuit 9b generates original data with the data in the RAM 5a (data in the register 7e) as the lower 16 bits and the 16 bits obtained by extending the MSB of the register 7e as the upper 16 bits.

  When reading data of only the lower 16 bits stored in the RAM 5b, the selection circuit 6e selects the data in the RAM 5b and sets it in the register 7e. The bit extension circuit 8 extends the MSB of the register 7e to generate upper 16 bits. The selection circuit 6b selects the output of the bit expansion circuit 8 and sets the higher 16 bits of the synthesis circuit 9b. The data in the register 7e (data in the RAM 5b) is the lower 16 bits of the synthesis circuit 9b. The synthesizing circuit 9b generates original data using the data in the RAM 5b (data in the register 7e) as lower bits and the output of the selection circuit 6b (upper 16 bits generated by the bit expansion circuit 8) as upper 16 bits.

  In this way, the data in which only the lower 16 bits are stored in the RAM 5a or 5b is expanded and read by the combining circuit 9b into the original 32-bit data.

  When the number of effective bits output from the ALU 2 is 16 bits or less, storage of unnecessary upper 16 bits of data is reduced as in the case of FIG. 3, and data is stored in the storage unit 4 more efficiently than before. Is possible. In FIG. 8, the left RAM 5a stores upper 16 bits or lower 16 bits of 32-bit output data from ALU2, and the right RAM 5b stores lower 16 bits of 32-bit output data from ALU2. To do. In the configuration of the storage unit 4 in FIG. 3, if the number of effective bits is 16 bits or less, the RAM 5a and 5b can be simultaneously read / written. However, in the storage unit 4 in FIG. Can only read and write to either one of the RAMs 5a or 5b. However, in the configuration of FIG. 3, the selection circuit for selecting the 32 bits of the output of the storage unit 4 is omitted, and when the circuit scale is compared including that, the configuration of FIG. 8 is compared with the configuration of FIG. Since the number of (MUX) is small, the circuit scale is small.

  FIG. 9 is a diagram illustrating a circuit configuration example from the ALU 2 to the memory 5 when the configuration of the storage unit 4 of FIG. 8 is used. Three ALUs 2 can access the pair of RAMs 5a and 5b in FIG. A 3 → 1 MUX 6f for selecting output data from the 32-bit ALU 2 is provided. Therefore, the output from the three ALUs 2 is limited to one regardless of the number of effective bits. The same applies to the input to the ALU 2 and is limited to one data (type) regardless of the number of effective bits. As described above, since the input / output limitation of the ALU 2 does not depend on the number of effective bits of data, if the pair of RAMs 5a and 5b is regarded as one memory 5, the same processing as the conventional RAM configuration can be applied.

  The number of effective bits of the input / output data of the ALU 2 is determined based on a program 36 describing an intended arithmetic process executed by the reconfigurable circuit 1. When the intended arithmetic processing is described in C language, the number of effective bits can be determined by a variable type or a comment sentence. Then, when creating the setting data 40, the setting data generation unit 32 sets the setting data for storing the data in the RAMs 5a and 5b with the above-described restrictions from the number of effective bits based on the determination result of the input / output data of the ALU2. 40 is created.

  FIG. 10 shows a configuration of the storage unit 4 using a plurality of pairs of RAMs 5a, 5b, 5c, and 5d. 8 and 9 show a pair of RAM configurations, but a plurality of pairs of RAM configurations may be used as shown in FIG. FIG. 10 shows an example in which two pairs of RAMs 5a and 5b and RAMs 5c and 5d are used in the configuration of the storage unit 4 shown in FIG. In this case, the input / output data is limited to two (types) regardless of the number of effective bits.

  The configuration of the storage unit 4 in FIGS. 3 and 8 is different in input / output restrictions of the ALU 2. Which configuration is adopted is determined according to the characteristics of the system to which the processing apparatus 10 is applied. A combination of the two embodiments is also possible.

  Also in this embodiment, the case where 32-bit data is divided into upper 16 bits and lower 16 bits and stored in the storage unit 4 has been described. However, the number of bits of data and the number of bits stored in the storage unit are 32 bits. It is not limited to 16 bits. For example, when the number of bits of data is 16 bits, it can be configured to be divided and stored in two parts where the number of bits stored in the storage unit is 8 bits. In addition, when the data is 64 bits, the data may be divided into upper 32 bits and lower 32 bits and stored in the storage unit. The configuration for storing data divided into two parts, upper and lower, is the same as the configuration of FIGS.

  Furthermore, a configuration in which data is divided into many parts and stored in the storage unit is also possible. In addition, the number of bits of the memory word specified by one address of the paired RAM may be non-uniform.

  8 and 9, the registers 7, 7e and the like are shown on the input side and output side of the memory 5 for easy understanding, but the registers may be data lines instead of circuits for holding data.

  According to the present invention, since data can be efficiently stored in the storage unit 4, the entire memory capacity is reduced as compared with the conventional case, and the circuit scale can be reduced.

Note that the circuit configurations of the processing device 10, the reconfigurable circuit 1, and the storage unit 4 described in the embodiments are merely examples, and can be arbitrarily changed and modified. The configuration of the storage unit 4 is not limited to that shown in the embodiment, and is not limited to these.

It is a block diagram which shows the structure of a processing apparatus provided with the reconfigurable circuit which concerns on embodiment of this invention. It is a block diagram which shows the example of a structure of the reconfigurable circuit which concerns on embodiment of this invention. It is a figure which shows an example of a structure of the memory | storage part which memorize | stores the data which a reconfigurable circuit uses in the processing apparatus which concerns on this invention. FIG. 4 is a diagram illustrating a circuit configuration example from an ALU to a memory when the configuration of the storage unit in FIG. 3 is used. It is a figure which shows the structure of the memory | storage part using several pairs RAM. It is a figure which shows the structural example of the memory | storage part in the case of storing the data output from a 64-bit ALU array in four 16-bit RAM. It is a figure which shows the example of the memory | storage part which comprised memory by three RAM from which bit numbers differ. It is a figure which shows the example from which the structure of the memory | storage part which memorize | stores the data which a reconfigurable circuit uses is different in the processing apparatus which concerns on this invention. FIG. 9 is a diagram illustrating a circuit configuration example from an ALU to a memory when the configuration of the storage unit in FIG. 8 is used. It is a figure which shows the structure of the memory | storage part using several pairs RAM. It is a figure which shows the example of the memory | storage part in the conventional reconfigurable circuit.

Explanation of symbols

1 Reconfigurable circuit
2 Logic circuit (ALU)
3 connections
4 storage
5 Memory 5a, 5b, 5c, 5d, 5e, 5f RAM
6a, 6b, 6c, 6d, 6e, 6f selection circuit 7, 7a, 7b, 7c, 7d, 7e, 7f register
7g, 7h Enlarged circuit
8, 8a, 8b bit expansion circuit
9a, 9b, 9c synthesis circuit
10 Processing device
30 Compilation section
32 Setting data generator
34 Setting memory
36 programs
38 Data flow graph
40 Setting data

Claims (8)

An arithmetic unit composed of a plurality of logic circuits each capable of selectively executing a plurality of arithmetic logic operation functions;
A connection unit for maintaining a connection relationship between the plurality of logic circuits;
In a processing apparatus including a reconfigurable circuit comprising:
Storage means for storing data used in the logic circuit;
When the number of bits of data stored in the storage means exceeds the number of bits of a memory word specified by one address of the storage means, and the number of valid bits of the data does not exceed the number of bits of the memory word , Degenerate storage means for changing data to a number of bits less than or equal to the number of bits of the memory word and storing it in one memory word;
Extended read means for restoring the data in accordance with the number of input bits of the logic circuit when the data stored in the degenerate storage means is changed to a bit number equal to or less than the number of bits of the memory word ; and
A processing apparatus comprising: If the number of bits of data stored in the storage means exceeds the number of bits of the memory word and the number of valid bits of the data exceeds the number of bits of the memory word, the data has the number of bits of the memory word. Divided storage means for dividing into a plurality of parts and storing in a plurality of memory words;
Concatenated read means for restoring the original number of bits when reading from the plurality of memory words, the data divided and stored in the plurality of memory words by the divided storage means,
The processing apparatus according to claim 1, further comprising: The divided storage means has a plurality of portions having the number of bits of the memory word of the storage means
Each of the divided data is stored according to the bit position in the original data.
The processing apparatus according to claim 2, wherein the storage area is limited . The divided storage unit or the degenerate storage unit is configured to calculate the number of data output from the arithmetic unit.
4. The method according to claim 1, wherein the number of bits is limited according to the number of effective bits of the data.
The processing apparatus according to item. The concatenated reading means or the extended reading means is the number of data input to the arithmetic unit.
The processing apparatus according to any one of claims 1 to 4, characterized in that to limit in accordance with the number of effective bits of the data. The divided storage unit or the degenerate storage unit is configured to validate each data output from the arithmetic unit.
Memory in which the total number of memory words to be used can be written simultaneously according to the number of bits
5. The processing apparatus according to claim 4 , wherein the number of the data simultaneously output from the arithmetic unit is limited so as not to exceed the number of words . The concatenated reading means or the extended reading means is each data input to the arithmetic unit.
Depending on the number of valid bits, the total number of memory words used can be read simultaneously
6. The processing apparatus according to claim 5 , wherein the number of data simultaneously input to the arithmetic unit is limited so as not to exceed the number of memory words . A plurality of arithmetic logic operation functions selectively executed in the plurality of logic circuits;
A setting for controlling the operation of the reconfigurable circuit by setting a connection relationship between logic circuits.
In the generation of constant data ,
Based on a program describing an intended arithmetic process executed by the plurality of logic circuits,
Determining the number of effective bits of the input and output data of the logic circuit, the processing apparatus according to any one of claims 1 to 7, characterized in that to generate the configuration data.

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