JP3896083B2 - Reconfigurable circuit and integrated circuit device using it - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to integrated circuit technology, and more particularly to a reconfigurable circuit and an integrated circuit device that can use the reconfigurable circuit.
[0002]
[Prior art]
An FPGA (Field Programmable Gate Array) can design circuit configuration relatively freely by writing circuit data after the LSI is manufactured, and is used for designing dedicated hardware. The FPGA includes a lookup table (LUT) for storing a truth table of a logic circuit, a basic cell composed of an output flip-flop, and a programmable wiring resource connecting the basic cells. In the FPGA, a target logical operation can be realized by writing data stored in the LUT and wiring data. However, when an LSI is designed using an FPGA, the mounting area is very large and the cost is high compared to an ASIC (Application Specific IC) design. Thus, a method has been proposed in which the circuit configuration is reused by dynamically reconfiguring the FPGA (see, for example, Patent Document 1).
[0003]
[Patent Document 1]
JP-A-10-256383 (full text, Fig. 1-4)
[0004]
[Problems to be solved by the invention]
In particular, LSIs mounted on mobile terminals such as mobile phones and PDAs (Personal Data Assistants) must be downsized. If LSIs can be dynamically reconfigured and functions can be switched appropriately according to the application, LSIs Mounting area can be reduced. Also, satellite broadcasting has the property that when radio waves hit rain drops, it becomes difficult to reach, so when it rains it can be switched to rain compatible broadcasting that simultaneously sends a low resolution screen that is not easily affected by rain. However, in the receiver, a circuit is provided separately for each broadcast mode, and the broadcast is received by switching the circuit according to the broadcast mode. When it starts to rain, the broadcast mode is switched and broadcast in that mode continues until clear, while the other broadcast mode circuits of the receiver are idle. When switching and using multiple dedicated circuits, such as mode switching, and the switching interval is relatively long, instead of creating multiple dedicated circuits, the LSI can be reconfigured instantaneously at the time of switching. The structure can be simplified to improve versatility, and at the same time the mounting cost can be reduced. In order to meet such needs, the manufacturing industry has attracted attention to dynamically reconfigurable LSIs.
[0005]
The FPGA has a high degree of freedom in the design of the circuit configuration and is general-purpose. On the other hand, in order to enable connection between all basic cells, the FPGA includes a large number of switches and a control circuit for controlling ON / OFF of the switches. The mounting area of the control circuit is increased. In addition, since a complicated wiring pattern is used to connect the basic cells, the wiring tends to be long, and a delay is increased because many switches are connected to one wiring. For this reason, FPGA based LSIs are often used only for trial manufacture and experiments, and are not suitable for mass production in view of mounting efficiency, performance, cost, and the like.
[0006]
Further, in the FPGA, since it is necessary to send setting data to a large number of basic cells of the LUT method, it takes a considerable time to configure the circuit. Therefore, the FPGA cannot be used at all for applications that require instantaneous switching of the circuit configuration.
[0007]
The present invention has been made in view of such circumstances, and an object thereof is to provide a reconfigurable circuit that is advantageous in terms of mounting area, power consumption, circuit reconfiguration speed, and the like, and an integrated circuit device using the reconfigurable circuit. is there.
[0008]
[Means for Solving the Problems]
One embodiment of the present invention relates to a reconfigurable circuit. The circuit includes a multi-stage arrangement of logic circuits each capable of selectively executing a plurality of arithmetic functions, and a connection unit capable of setting a connection relationship between the output of the preceding logic circuit and the input of the succeeding logic circuit, In addition to the connection for connecting the logic circuits, the connection section is provided with an input connection that can directly input data to the logic circuit in the middle stage. The connection unit has a connection for connecting the output of the logic circuit to the input of another logic circuit, and the connection having a specific connection relationship can be validated by setting.
[0009]
In a multistage array of logic circuits in which operations are advanced from the upper stage to the lower stage, input variable and constant data are directly input to the uppermost logic circuit array. The output result from the preceding logic circuit string is generally input to the logic circuit string in the middle stage, that is, the second and subsequent stages. However, depending on the operation to be processed, the logic circuits in the second and subsequent stages are necessary. Input variable or constant data is directly input to the column. For this purpose, an input connection for directly inputting data to the second and subsequent logic circuit rows is provided.
[0010]
Each logic circuit may be a circuit capable of relatively high-performance operations, for example, an arithmetic logic circuit (ALU) capable of selectively executing a plurality of types of multi-bit operations. Depending on the setting data loaded from the outside, in each logic circuit, it may be set which of a plurality of arithmetic functions is selected. When a specific function is constructed in each logic circuit as in ALU, the logic circuit to which data necessary for the operation executed in the entire reconfigurable circuit can be relatively easily specified. The connection provided for direct input to the stage is effectively utilized.
[0011]
The structure of the multistage arrangement of the logic circuits is such that there is no connection connection between the logic circuits in the horizontal direction in the arrangement in which a plurality of rows of logic circuits arranged in the horizontal direction are combined in the vertical direction. A connection connection may be provided between the output of and the input of the logic circuit array at the next stage. If the connection connection is only in the vertical direction, the circuit scale can be reduced and the structure can be simplified. However, if the mesh structure has connection connections in the horizontal direction, the arrangement of the same number of logic circuits can be used. Can perform complex operations.
[0012]
The input connection may be provided at a connection portion of each stage, and may be provided by limiting to at least a part of the stages, for example, the upper n stages (n is an integer) among intermediate stages. Furthermore, input connection may be provided by limiting to a part of the columns of the logic circuits arranged in the same stage. In general, when an operation is advanced from the upper stage to the lower stage using a multi-stage logic circuit, the upper logic circuit requires a larger number of data inputs, and the lower the stage, the more logic circuits necessary for the operation. In many cases, the calculation structure is an inverted triangle such as decreasing. For this reason, it is possible to effectively use the logic circuit arrangement by providing a larger number of input connections in the upper-level logic circuit.
[0013]
Yet another embodiment of the present invention relates to an integrated circuit device. This device includes a reconfigurable circuit in which a logic circuit capable of selectively executing a plurality of arithmetic functions is connected in a multi-stage array structure capable of directly inputting data to a logic circuit at an intermediate stage, and the reconfigurable circuit A storage unit that stores setting data for setting a function of each logic circuit in the circuit and an input / output connection relationship between the logic circuits, and a setting that reads the setting data from the storage unit and loads the setting data into the reconfigurable circuit Part. For the calculation function of the logic circuit set by the setting data and the input / output connection relationship between the logic circuits, a graph representing the data flow of the operation to be processed is used as appropriate, and direct input of data to the logic circuit in the intermediate stage is used May be generated by mapping to a logic circuit having a multi-stage array structure. By this mapping, it is possible to specify a logic circuit at an intermediate stage that requires direct input of data such as input variables and constants, and it is possible to supply necessary data directly to the logic circuit.
[0014]
It should be noted that any combination of the above components and the expression of the present invention expressed as a method, apparatus, system, and computer program are also effective as an aspect of the present invention.
[0015]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 is a configuration diagram of an integrated circuit device 10 and an external control device 24 according to the embodiment. The external control device 24 creates data for setting the circuit configuration of the integrated circuit device 10 and supplies the data to the integrated circuit device 10.
[0016]
The integrated circuit device 10 includes a reconfigurable circuit 12, a setting data storage unit 16 that stores setting data 17 for reconfiguring the reconfigurable circuit 12, and a setting that loads the setting data 17 to the reconfigurable circuit 12. Part 14. The external control device 24 includes a control unit 18, a compilation unit 20, and a program storage unit 22.
[0017]
The program storage unit 22 of the external control device 24 holds various programs 19 to be executed by the integrated circuit device 10. The compiling unit 20 compiles the program 19 stored in the program storage unit 22, converts it into a data flow graph 21, and stores it in the program storage unit 22. As will be described later, the data flow graph 21 shows the flow of calculation of input variables and constants in a graph structure.
[0018]
The data flow graph 21 is converted into setting data 17 for mapping to the circuit configuration of the reconfigurable circuit 12, supplied to the setting unit 14 of the integrated circuit device 10 via the control unit 18, and the setting data storage unit 16. Stored in In the setting data storage unit 16, a plurality of setting data 17 are stored in advance corresponding to the data flow graph 21 of the operation to be processed. The setting unit 14 reconfigures the reconfigurable circuit 12 by appropriately reading the setting data 17 from the setting data storage unit 16 and loading it into the reconfigurable circuit 12. The reconfigured reconfigurable circuit 12 performs an operation based on the loaded setting data 17.
[0019]
FIG. 2 is a configuration diagram of the reconfigurable circuit 12. The reconfigurable circuit 12 includes a plurality of rows of ALUs (Arithmetic Logic Units) arranged in a plurality of stages, and the connection connection 30 provided in each stage causes the output of the preceding ALU column and the subsequent ALU column to be output. Input can be connected arbitrarily according to the setting. Further, for the ALU column in the middle stage except the first stage, input connection for direct input of input variables and constants is provided in the connection line 30 of each stage. Each ALU can selectively execute a plurality of types of multi-bit operations such as logical sum, logical product, and bit shift by setting.
[0020]
As shown in the figure, Y ALUs are arranged in the horizontal direction and X ALUs are arranged in the vertical direction, and input variables and constants are inputted to the first-stage ALU11, ALU12,..., ALU1Y. Depending on the setting, a predetermined calculation is performed. The calculation result output is input to the second-stage ALU 21, ALU 22,..., ALU 2Y in accordance with the connection set in the first-stage connection line 30. The first-stage connection line 30 is configured so that an arbitrary connection relationship between the output of the first-stage ALU column and the input of the second-stage ALU column can be realized. Connection is effective. Further, the first-stage connection line 30 is provided with a second-stage direct input line for directly inputting data to the second-stage ALU 21, ALU 22,..., ALU 2Y. Hereinafter, the connection configuration 30 up to the (X-1) -th stage connection wiring 30 has the same configuration, and the ALU column of the X-th stage, which is the final stage, outputs the final result of the calculation.
[0021]
The setting data 17 for mapping the data flow graph 21 to the reconfigurable circuit 12 includes information for selecting an operation of each ALU, information for selecting a connection connection between ALU columns, and ALU columns in the first and intermediate stages. The information for selecting the input connection, and the values of the input variables and constants are included.
[0022]
In general, the data flow graph 21 often has an inverted triangular graph structure in which the number of required ALUs decreases as the operation stage progresses, but not only the first-stage ALU column but also the intermediate-stage graph. By configuring the ALU column so that data can be input, the data flow graph 21 can be mapped to the reconfigurable circuit 12 without being restricted by the number of horizontal ALU columns.
[0023]
FIG. 3 to FIG. 5 are diagrams for explaining the reconfigurable circuit 12 in which restrictions are imposed on an ALU array that can be input midway. If halfway input is possible for all ALUs, the circuit scale of the connection line 30 is increased by direct input connection. Therefore, limiting the number of stages and columns of the ALU array that can be input halfway reduces the mounting area. It is advantageous.
[0024]
FIG. 3 shows an example of the reconfigurable circuit 12 when the number of stages of ALU arrays that can be input midway is limited. Direct input connection is provided only to the first and second stage connection connections 32 of the four-stage and four-column reconfigurable circuit 12, and data is directly input to the second and third ALU columns. Is possible.
[0025]
FIG. 4 is an example of the reconfigurable circuit 12 when the number of columns of the ALU array that can be input midway is limited. Although direct input connections are provided for the connection connections 36 in all stages of the reconfigurable circuit 12, the horizontal direction is limited to two columns from the left. For example, it is possible to directly input only the ALU 21 in the first column and the ALU 22 in the second column among the ALU columns in the second column to the first stage connection line 36.
[0026]
FIG. 5 shows an example of the reconfigurable circuit 12 when both the number of stages and the number of columns of the ALU array that can be input midway are limited. Direct input connections are provided only for the first and second stage connection connections 38 of the reconfigurable circuit 12, and the horizontal direction is limited to two columns from the left, and the first and second columns of the second stage. And direct input of data only to the ALUs in the first and second columns of the third stage.
[0027]
FIG. 6 is a diagram illustrating an example of the data flow graph 21. This data flow graph 21 shows multiplication of inputs X and Y. In the figure, operators are indicated by circles, “+” is logical sum, “&” is logical product, “<<” is left bit shift, “>>” is right bit shift, “==” is etc. “SEL” is an operator for selecting either true (T) or false (F) based on the determination result. Also, input variables, constants, and outputs are indicated by squares. A solid line is a data signal line, and a dotted line is a selection signal from a selection operator. Inputs X and Y are both positive integers, and Y is 2 bits. The result of multiplication by the data flow graph 21 is finally output as an output ANS.
[0028]
FIG. 7 shows an example in which the data flow graph 21 of FIG. 6 is mapped to the reconfigurable circuit 12 that cannot be directly input to the intermediate stage. Since none of the connection connections 42 is provided with a direct input connection, all input variables X and Y and constants (indicated by reference numerals 46 to 60) must be input to the first stage ALU column. In order to input input variables and constants, eight rows of ALUs are required in the horizontal direction, and five steps of ALU columns are required in the vertical direction in order to perform five stages of operations. Therefore, as shown in the figure, the data flow graph 21 is mapped to the reconfigurable circuit 12 having 5 columns and 8 columns. In the figure, ALUs that are used are indicated by solid circles, and ALUs that are not used are indicated by dotted circles. “MOV” indicates that the input value is output as it is without being calculated. A considerable number of ALUs are not used in the latter half, and the utilization efficiency of the ALU array is not good.
[0029]
FIG. 8 shows an example in which the data flow graph 21 of FIG. 6 is mapped to the reconfigurable circuit 12 that can be directly input to the intermediate stage. In this case, connection wirings 44 with direct input are provided in all stages, and some constants 50, 52, 58, 60 input to the first ALU column in FIG. 7 are replaced with the second stage in FIG. The data flow graph 21 is mapped to the reconfigurable circuit 12 having 5 columns in the vertical direction and 4 columns in the horizontal direction by directly inputting to the ALU column in the third stage.
[0030]
9A is a diagram for explaining the configuration of the connection connection 42 in FIG. 7 and FIG. 9B is a diagram for explaining the configuration of the connection connection 44 with direct input in FIG. 7 includes an n-bit 4-to-1 selector 62 for selecting one of the four data signals ALUX1 to ALUX4 from the preceding ALU column, and four selections from the previous ALU column. 1-bit 4-to-1 selector 64 for selecting one of signals ALUX1LSB to ALUX4LSB is included. The output results of the selectors 62 and 64 are input to each ALU 66 in the subsequent ALU column. Accordingly, by setting the selectors 62 and 64, a specific connection relationship between the output of the preceding ALU column and the input of the subsequent ALU column is realized.
[0031]
In the case of the connection line 44 in FIG. 8, since there is a signal that is directly input in addition to the output signal from the preceding ALU column, one of the four data signals from the preceding ALU column and the directly input data signal is present. An n-bit 5-to-1 selector 68 for selecting one and a 1-bit 5-to-1 selector 70 for selecting one of the four selection signals from the ALU column in the previous stage and the selection signal directly input Will be provided. The output results of the selectors 68 and 70 are input to each ALU 72 in the subsequent ALU column. Since the connection is for direct input, the circuit scale of the connection line 44 with direct input is larger than that of the connection line 42 in FIG.
[0032]
FIG. 10 shows the case where the number of stages that can be directly input is limited in the configuration of FIG. 8, and the second stage and third stage ALU columns to which data is directly input are directly input as shown in FIG. A supplementary connection 44 is provided. On the other hand, since the connection connection 42 without the direct input connection is provided for the other ALU columns, the circuit scale can be reduced accordingly.
[0033]
FIG. 11 shows a case where more direct inputs are provided in the configuration of FIG. The two constants 46 and 48 that have been input to the first-stage ALU column in FIG. 10 are directly input to the second-stage and third-stage ALU columns in FIG. In addition, the data flow graph 21 is mapped to the reconfigurable circuit 12 having five columns in the vertical direction and three columns in the horizontal direction by directly inputting the data to the third-stage ALU column. Since the number of ALU columns is reduced by one and the number of ALUs used is reduced, the circuit can be realized with a smaller circuit scale.
[0034]
FIG. 12 shows a case where the number of columns that can be directly input is further limited in the configuration of FIG. In the second and third ALU columns, data is directly input only in the two right columns, so that the right 2 of the second and third ALU columns as shown in FIG. The connection connection 45 with direct input is provided only for the columns, and the connection connection 43 without direct input connection is provided for the left two columns. Compared to the connection connection 44 with direct input in FIG. 10, the connection connection 45 with direct input in FIG. 12 is realized with a smaller circuit scale because of less direct input connection.
[0035]
FIG. 13 shows an example in which another data flow graph 21 is mapped to the reconfigurable circuit 12 that cannot be directly input to an intermediate stage. In this example, the data flow graph 21 is mapped to the reconfigurable circuit 12 of 6 columns and 9 columns, and no input connection is provided for any connection connection 80. Therefore, all input variables X , Y, Z, W and constants (indicated by reference numerals 84 to 96) are input to the ALU column in the first stage. The data flow graph 21 of this example is characterized in that more constants are used in the latter half of the calculation. Therefore, when mapping the data flow graph 21 to the reconfigurable circuit 12 that can directly input to the intermediate stage, it is more efficient to enable direct input to the latter stage.
[0036]
FIG. 14 shows an example in which the same data flow graph 21 as in FIG. 13 is mapped to the reconfigurable circuit 12 that can be directly input to the lower stage. For the second and third ALU columns, connection connection 80 without direct input connection is provided, but for the lower stages after that, that is, for the ALU columns from the fourth to sixth stages. Is provided with a connection 82 with direct input. In this example, three constants 86, 92, 96 and an input variable W are directly input to the fourth-stage ALU column, and two constants 84, 94 are input to the fifth-stage ALU column. Directly entered. The connection line 82 with direct input is also provided for the sixth-stage ALU column, but in this example, direct input is not performed for the sixth-stage ALU column. By configuring in this way, the data flow graph 21 can be mapped to the reconfigurable circuit 12 having six columns and three columns. As seen in this example, not only a configuration that allows direct input from the top level to several levels, but also a configuration that allows direct input from the bottom level to several levels is advantageous for mapping the data flow graph 21. is there.
[0037]
FIG. 15 shows an example in which another data flow graph 21 is mapped to the reconfigurable circuit 12 that cannot be directly input to an intermediate stage. In this example, the data flow graph 21 is mapped to the reconfigurable circuit 12 of 6 columns and 10 columns, and no direct connection is provided for any of the connection connections 80. Therefore, all the input variables X , Y, Z and constants (indicated by reference numerals 98 to 116) are input to the ALU column in the first stage. In this case, as shown in FIG. 16, the data flow graph 21 is mapped to the reconfigurable circuit 12 of 6 columns and 3 columns by limiting the direct input to the intermediate stage to the left two columns. Can do. As shown in the figure, a direct connection connection 83 is provided for the first and second columns of the ALU columns at each stage, and a direct input connection for the third column of the ALU columns at each stage. A connection line 81 having no connection is provided. In this example, of the constants input to the first stage in FIG. 15, two constants 104 and 110 are in the second stage ALU column, and the other two constants 102 and 112 are in the third stage ALU string. Two other constants 100 and 116 are directly input to the fourth-stage ALU column, and another one constant 98 is directly input to the fifth-stage ALU column. The input variable Z is input to the fourth-stage ALU column. By limiting the direct input connection to the left two columns, the connection can be reduced and realized with a smaller circuit scale.
[0038]
According to the reconfigurable circuit 12 described above, since an ALU having a high-performance computing capability is used as a basic cell, the configuration can be performed by a setting operation of one clock. The circuit can be reconfigured instantly. In general, when ALUs are arranged in multiple stages, even if a sufficient number of ALU arrays are provided in the horizontal direction in the first stage, the number of ALU arrays necessary for the calculation tends to decrease as going to the subsequent stage. Although the circuit utilization efficiency deteriorates, the reconfigurable circuit 12 according to the present embodiment allows the data flow graph 21 to be efficiently mapped to the ALU array by permitting direct input of data at an intermediate stage. It is. Therefore, the reconfigurable circuit 12 can be configured with a small circuit scale, and the mounting cost can be reduced and the power consumption can be kept small.
[0039]
The present invention has been described based on the embodiments. The embodiments are exemplifications, and it will be understood by those skilled in the art that various modifications can be made to combinations of the respective constituent elements and processing processes, and such modifications are within the scope of the present invention. .
[0040]
As such a modification, the above embodiment has described the case where ALUs are arranged in multiple stages in a rectangular shape. However, the arrangement pattern is not limited to this, and the lower the level, the more the ALUs are arranged in the horizontal direction. It may be arranged in multiple stages in an inverted triangular shape with a decreasing number. Even in the case of multi-stage arrangement in an inverted triangle shape, the number of ALU columns required in the first stage for input data differs depending on the operation pattern to be processed, and may require direct input to the ALU in the middle stage. The present invention is also effective in such an arrangement. In other words, one advantage of the present invention is that it has a structure that allows direct input to the ALU in the middle stage, thereby enabling efficient mapping of the data flow graph without depending on the shape of the ALU array. There is.
[0041]
Furthermore, the arrangement of ALUs is not limited to a multistage arrangement that allows connection only in the vertical direction, but may be a mesh arrangement that also allows connection in the horizontal direction. In this case, the same effect can be obtained by adopting a configuration that enables direct input of data to the ALU that is in the middle of the operation stage when the operation pattern is mapped to the mesh arrangement.
[0042]
In the above description, the connection for connecting the logic circuit by skipping the stage is not provided. However, a simple circuit configuration is sacrificed, but the connection connection for skipping such a stage is provided. Also good.
[0043]
Also, some of the components of the integrated circuit device 10 and the external control device 24 of the embodiment may be provided on the other device side. For example, the setting data 17 may be stored in the program storage unit 22 of the external control device 24 without being stored on the integrated circuit device 10 side, and supplied from the external control device 24, or a data flow graph 21 may be stored in the setting data storage unit 16, and the process of converting the data flow graph 21 into the setting data 17 may be performed on the integrated circuit device 10 side. In the above-described embodiment, the integrated circuit device 10 can be disconnected from the external control device 24 after the setting data 17 is stored in the setting data storage unit 16, but the integrated circuit device 10 is connected to the external control device. The integrated circuit device 10 and the external control device 24 may be integrated into a single arithmetic processing device.
【The invention's effect】
According to the present invention, an efficient reconfigurable circuit can be realized.
[Brief description of the drawings]
FIG. 1 is a configuration diagram of an integrated circuit device and an external control device according to an embodiment.
2 is a configuration diagram of the reconfigurable circuit of FIG. 1;
FIG. 3 is another configuration diagram of the reconfigurable circuit of FIG. 1;
4 is still another configuration diagram of the reconfigurable circuit of FIG. 1. FIG.
5 is still another configuration diagram of the reconfigurable circuit of FIG. 1. FIG.
6 is a diagram for explaining an example of the data flow graph of FIG. 1; FIG.
7 is a diagram for explaining an example in which the data flow graph of FIG. 6 is mapped to a reconfigurable circuit that cannot be directly input to an intermediate stage.
8 is a diagram illustrating an example in which the data flow graph of FIG. 6 is mapped to a reconfigurable circuit that can be directly input to an intermediate stage.
9A is a configuration diagram of the connection connection of FIG. 7, and FIG. 9B is a configuration diagram of the connection connection with direct input of FIG.
FIG. 10 is a diagram illustrating a case where the number of stages that can be directly input is limited in the reconfigurable circuit of FIG. 8;
11 is a diagram for explaining a case where more direct inputs are provided in the reconfigurable circuit of FIG.
12 is a diagram illustrating a case where the number of columns that can be input midway is limited in the reconfigurable circuit of FIG.
FIG. 13 is a diagram illustrating an example in which another data flow graph is mapped to a reconfigurable circuit that cannot be directly input to an intermediate stage.
14 is a diagram for explaining an example in which the same data flow graph as in FIG. 13 is mapped to a reconfigurable circuit that can be directly input to the lower stage.
FIG. 15 is a diagram illustrating an example in which another data flow graph is mapped to a reconfigurable circuit that cannot be directly input to an intermediate stage.
16 is a diagram for explaining an example in which the same data flow graph as in FIG. 15 is mapped to a reconfigurable circuit that can be directly input to the left column.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 10 Integrated circuit device, 12 Reconfigurable circuit, 14 Setting part, 16 Setting data storage part, 17 Setting data, 18 Control part, 19 Program, 20 Compile part, 21 Data flow graph, 22 Program storage part, 24 External control device , 30 Connection connection.

Claims (6)

Each including a multi-stage arrangement of logic circuits capable of selectively executing a plurality of arithmetic functions, and a connection section capable of setting a connection relationship between an output of the preceding logic circuit and an input of the succeeding logic circuit,
In addition to the connection for connection between the logic circuits, the connection section is provided with an input connection that allows direct input of data to the logic circuit in the middle stage .
The reconfigurable circuit according to claim 1, wherein the input connection is limited to a part of the stages of the multistage arrangement . The reconfigurable circuit according to claim 1 , wherein the input connection is limited to upper n stages (n is an integer) of the multistage array. The logic circuit is reconfigurable circuit according to claim 1 or 2, characterized in that it is capable of selectively executing arithmetic and logic multi-bit operations of a plurality of types. Reconfigurable circuit according to any one of claims 1-3 wherein the input connection, characterized in that the provided limits a part of columns of the logic circuits arranged in each stage. A reconfigurable circuit according to any one of claims 1 to 4 ,
A storage unit that stores setting data for setting a function of each logic circuit in the reconfigurable circuit and an input / output connection relationship between the logic circuits;
An integrated circuit device comprising: a setting unit that reads the setting data from the storage unit and loads the setting data into the reconfigurable circuit. The setting data is generated by mapping a graph representing a data flow of an operation to be processed to the logic circuit having the multi-stage array structure in a format appropriately using direct input of data to the logic circuit in the middle stage. The integrated circuit device according to claim 5 , wherein the integrated circuit device is a device.

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