JPH1091216A - Programmable semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain the semiconductor device which can alter complicated control and functions by arranging sequence control processing circuits, which can correct and alter functions through program operation from outside, in array. SOLUTION: The semiconductor device is provided with basic unit cells 4 each consisting of a controller part which inputs and stores an input variable instruction set from outside and a data bus part which inputs an input to be processed, performs specific operation for the input to be processed according to the variable instruction set stored in the controller part, and outputs a process output, and also provided with a switch control circuit 5 which switches connection relation of input and output among the basic unit cells 4.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device for performing sequence control, and more particularly to a programmable semiconductor device whose function can be changed by an external program.

[0002]

2. Description of the Related Art When performing sequence control using a semiconductor device, it is necessary to set various functions of the semiconductor device according to the purpose and application.

As a semiconductor device having a simple function, a gate array and an FPGA (field programmable gate array) are already commercially available.

In a gate array, a user combines basic information having a simple function with CAD (co.
A device capable of performing a desired operation can be obtained by generating the information by using a computer aided design and bringing the information to a semiconductor manufacturer.

[0005] Further, in the FPGA, a user can perform a desired operation by combining function blocks having simple functions, generating the connection information by a dedicated CAD, and writing the information into the FPGA by a dedicated tool. A possible device can be obtained.

Further, as a method of constructing hardware by an external program, Japanese Patent Application Laid-Open No. Hei 8-50428 is disclosed.
The "system for compiling the algorithm language source code into hardware" described in Japanese Unexamined Patent Application Publication No. 5-2005 and the "high-speed programmable logic controller" described in Japanese Unexamined Patent Publication No. Hei 8-505483 are known.

[0007]

However, the conventional gate array and FPGA have the following problems.

[0008] 1. In a gate array, since a sequence control processing circuit is realized by a combination of simple logic circuits, an enormous amount of time is required for design. In addition, after the design is completed, the manufacture of a device that performs a desired operation is performed by a semiconductor manufacturer, so that much time is required for the manufacture. Further, the function cannot be changed or modified on the user side after manufacturing.

[0009] 2. In the case of an FPGA, although the functions can be changed or modified after manufacture, enormous time is required for design as in the case of the gate array, in order to realize a sequence control processing circuit by combining function blocks with simple functions.

[0010] 3. A system for compiling the algorithm language source code described in Japanese Patent Application Laid-Open No. 8-504285 into hardware is a PLD (programmab).
This is a system in which a semiconductor device is connected to a hardware device that can be connected to the device, and a plurality of semiconductor devices are connected to each other to have a desired function.

4. The high-speed programmable logic controller described in Japanese Patent Application Laid-Open No. 8-505483 is a system using a microprocessor, and cannot change the instruction set of the microprocessor itself.
Extra resources are required to achieve the desired function.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor device capable of performing complicated control and changing functions by arranging a sequence control processing circuit capable of correcting and changing functions by an external program operation in an array. I do.

[0013]

In the programmable semiconductor device of the present invention, a variable instruction set is externally input, a controller for storing the input variable instruction set, and an input to be processed are input. And a data bus unit configured to perform a predetermined operation on the input to be processed based on the variable instruction set stored in the controller unit and output a processed output. And a switch control circuit for switching an input and output connection relationship between the basic unit cells.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A plurality of basic unit cells suitable for sequence processing are prepared on a semiconductor device, and a cascade input and a cascade output are provided. Each basic unit cell is composed of a circuit having a control section and a data path section, and enables variable processing by a program.
Also, a software tool for changing the function of the basic unit cell and a software tool for the programmable space switch are prepared.

[0015]

FIG. 1 is a block diagram showing the structure of a field programmable sequencer array (FPSA) to which the present invention is applied.

The field programmable sequencer array has one command input signal line 1, one switch setting signal line 2, and four or more switch input / output signal lines 3.
And a plurality of basic unit cells (BUC (Basi
c Unit Cell) 4, a switch control circuit 5, and an input / output control circuit 6.

As will be described in detail later, each basic unit cell 4 receives a command input I, a cascade input C, and an input P to be processed, and outputs a cascade output and a processing output.
An instruction input is supplied to each basic unit cell 4, and an instruction input terminal, an input terminal to be processed, a cascade output terminal, and a processing output terminal of each basic unit cell 4 are connected to the switch control circuit 5. Also, a switch setting signal is supplied to the switch control circuit 5 and the input / output control circuit 6. Also, the input / output signal is supplied to the input / output control circuit 6, and the input / output control circuit 6
Is supplied to the switch control circuit 5, and the output from the switch control circuit 5 is supplied to the input / output control circuit 6.

[Basic Unit Cell] FIG.
FIG. 2 is a block diagram showing an internal configuration of the device. Basic unit cell 4
Is composed of a controller unit 7 and a data path unit 8.

The controller section 7 comprises a program control circuit 7a, a cascade control circuit 7b, a memory circuit 7c, and a program counter circuit 7d.

The program control circuit 7a develops in parallel a serial command input signal input from the command input signal line 1 and stores the same in the memory circuit 7c. The cascade control circuit 7b controls the processing of the basic cell by an input signal from another basic cell 4 and sends out a cascade signal to another basic cell connected to the basic cell.
This cascade signal is a signal indicating carry information in each basic cell similar to carry-in and carry-out. The memory circuit 7c stores instructions developed in parallel by the program control circuit 7a. The program counter circuit 7d generates a memory address for sending the program stored in the memory circuit 7c to the data path unit 8 having an instruction decoder.

The data path section 8 comprises an arithmetic circuit 8a, a bit processing circuit 8b, a memory circuit 8c, a variable instruction decoder circuit 8d, a data latch circuit 8e, and an output control circuit 8f. A control signal is supplied to the data path unit 8 from the controller unit 7 as an instruction signal to the variable instruction decoder circuit 8d and a signal indicating a program state. The control signal from the controller unit 7 is a signal indicating a processing state for one instruction step.

The arithmetic circuit 8a performs arithmetic processing on an input to be supplied to the basic unit cell 4 according to a program. The bit processing circuit 8b performs bit processing on the input to be processed according to a program. The memory circuit 8c includes:
Temporary data for bit processing and arithmetic processing and data for the variable instruction decoder 8d are stored. The variable instruction decoder circuit 8d decodes an instruction used in a target sequencer processing circuit constructed from a single unit or a combination of the basic unit cells 4, determines processing of an input to be processed, and controls all circuits. Send a signal. That is, the control signal from the variable instruction decoder 8d is transmitted to all the circuits of the data path unit 8, that is, the arithmetic circuit 8a, the bit processing circuit 8b, the memory circuit 8c, the data latch circuit 8e, and the output control circuit 8
f and a status signal to the controller 7. The instruction decoding rule of the variable instruction decoder circuit 8d can be changed by the data stored in the memory circuit 8c. That is, the instruction set is changed by the microprogramming method.

The data latch circuit 8e outputs the input to be processed
The processing is temporarily held until the processing is completed in the processing circuit selected by the variable instruction decoder circuit 8d. Output control circuit 8
f controls the output of the processed signal.

[Switch Control Circuit] FIG. 3 is a block diagram showing the internal configuration of the switch control circuit 5. As shown in FIG. The switch control circuit 5 includes a switch setting control circuit 5a, a switch setting memory 5b, and a matrix switch 5c.

The switch setting control circuit 5a is provided with an external switch setting input for physically connecting the basic unit cell outputs 1 to n input to the matrix switch 5c and the basic unit cell inputs 1 to n output. And writes it in the switch setting memory 5b. Switch setting memory 5b
Stores setting information of the matrix switch 5c. The basic unit cell output is composed of a processed output and a cascade output, and the basic unit cell input is composed of a processed input and a cascade input.

[Input / Output Control Circuit] FIG. 4 is a block diagram showing the internal configuration of the input / output control circuit 6. As shown in FIG. The input / output control circuit 6 is constituted by a bidirectional circuit having a normal CMOS structure. The output signal from the switch control circuit 5 is connected to the input / output of the device via a dot 6 via a buffer 6a with an output enable, that is, wired or connected. The output from the device is connected to the switch control circuit 5 via the buffer 6b. Output enable signals to all input / output terminals are input from the switch setting input line 2 and set by the input decoder 6c.

Next, a procedure for realizing a sequence processing circuit having a desired function using the above-described field programmable sequencer array will be described.

FIG. 5 is a flowchart showing a basic procedure for realizing a sequence processing circuit having a desired function. In this embodiment, as shown in FIG. 5, the operation of the sequence processing circuit that the designer wants to realize is described in software (step 101), and the description can be realized by the instruction set of the basic unit cell 4. The sequence is converted into a machine language code by the software for conversion (step 102) (step 103), and a command is input to the basic unit cell 4, thereby realizing a sequence processing circuit having a desired function in one basic unit cell 4. Functions as a sequence processing circuit.

The above-mentioned conversion software means a high-level language such as C language or C ++ language used for control or Verilog H
This is software for generating a machine language code optimized for the instruction set of the basic unit cell 4 to realize a processing function described in a hardware description language such as DL or VHDL. As the conversion software, it is possible to apply the technology of a commercially available compiler.

If the instruction set of the basic unit cell 4 is not suitable for realizing the processing circuit, as shown in the flowchart of FIG. 6, instruction optimization software is used (step 206) to execute the software description. An appropriate sequence processing circuit can be realized by estimating an appropriate instruction set of the basic unit cell 4 from (step 207) and programming the instruction set in the basic unit cell 4 (step 208). Steps 201 to 205 in FIG.
Since the processing corresponds to the processing shown in steps 101 to 105 of FIG.

When the instruction set of the basic unit cell 4 is unsuitable for realizing the processing circuit, an example of changing the instruction set to an optimal sequence processing is a product-sum operation using a combination of addition instructions. The processing may be changed to a processing using a sum operation instruction. By changing the instruction set in this way, the processing time is reduced. Another example is that, when performing bit processing, changing the processing of shifting data by a combination of multiplexing instructions to the processing using shift instructions. Also in this case, the processing time is reduced.

The instruction optimizing software is used to realize a processing function described in a high-level language such as C language or C ++ language used for control or a hardware description language such as Verilog HDL or VHDL. It is software that estimates the optimal instruction set and generates the instruction set. As the instruction optimizing software, for example, software to which artificial intelligence technology is applied can be used.

In the case of a complex sequence processing circuit in which a desired sequence processing circuit cannot be realized by the basic unit cells 4, as shown in the flowchart of FIG. Implement sequence processing.

That is, 1. The sequence processing to be realized is described in software (step 301).

2. The sequence processing contents are divided into basic unit cell levels by division software (step 30).
2).

3. The setting of the switch control circuit 5 for realizing the connection between the basic unit cells required for the division processing is performed (steps 303 and 304).

4. A machine language code suitable for the instruction set to the basic unit cell for realizing the divided processing is generated by the same conversion software as that shown in FIG. 6 (steps 305 and 306).

5. The machine language code to the basic unit cell and the setting code to the switch control circuit 5 are input (step 307).

6. A sequence process is performed on a plurality of basic unit cells (step 308).

The above-mentioned software for dividing into basic unit cells uses processing functions described in a high-level language such as C language or C ++ language used for control or a hardware description language such as Verilog HDL or VHDL as basic units. It is optimally divided into functional units that can be processed by cells, and generates information for software for converting to instruction sets and software for setting connection between basic unit cells. As the division software, for example, software to which automatic placement and routing software used in LSI design is applied can be used.

The software for converting into an instruction set is a machine language optimized for the instruction set of the basic unit cell based on information (definition of processing for each basic unit cell) generated by the software for dividing the basic unit cell. Generate code. The basic unit cell connection setting software generates a connection code between basic unit cells from information (definition of the relationship between all basic unit cells) generated by the software for dividing into basic unit cells. FIG. 8 is an explanatory diagram showing the connection between basic unit cells via the switch control circuit 5.

Further, if the instruction set of the basic unit cell is not suitable for the required sequencer processing, a desired sequencer processing circuit can be realized by changing the instruction set of the basic unit cell as described above.

[0043]

According to the present invention, the basic unit cells are logic circuit modules which can be controlled in sequence by being programmed from the outside, a large number of them are arranged in an array, and connections between the modules are performed by space switch control. A semiconductor device having multiple functions can be configured.

By preparing a plurality of basic unit cells suitable for sequence processing on a semiconductor device, a combination of a simple logic circuit such as a gate array and a combination of simple function blocks such as an FPGA can be utilized. It can be designed in a much shorter time than when designing a sequence processing circuit.

Further, by providing a cascade input and a cascade output to realize the use of a plurality of basic unit cells, a complicated sequence processing circuit can be implemented by a gate array or FP.
It can be designed in a much shorter time than GA.

Since the basic unit cell is constituted by a circuit having a controller section and a data path section and can perform variable processing by a program, the function of the sequence processing circuit can be changed or modified in a short time.

By preparing a software tool for changing the function of the basic unit cell, the function of the basic unit cell can be changed or modified in a short time.

By providing a software tool for a programmable space switch, changes and modifications to the functionality of the semiconductor device can be made in a short period of time.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a structure of a field programmable sequencer array to which a semiconductor device of the present invention is applied.

FIG. 2 is a block diagram showing an internal configuration of a basic unit cell.

FIG. 3 is a block diagram showing an internal configuration of a switch control circuit 5.

FIG. 4 is a block diagram showing an internal configuration of the input / output control circuit 6.

FIG. 5 is a flowchart showing a basic procedure for realizing a sequence processing circuit having a desired function.

FIG. 6 is a flowchart illustrating a process when an instruction set of a basic unit cell is inappropriate for realizing a processing circuit.

FIG. 7 is a flowchart showing a process when a sequence process is realized using a plurality of basic unit cells.

8 is an explanatory diagram showing connection between basic unit cells via a switch control circuit 5. FIG.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 command input signal line 2 switch setting signal line 3 input / output signal line 4 basic unit cell 5 switch control circuit 5 a switch setting control circuit 5 b switch setting memory 5 c matrix Switch, 6: input / output control circuit, 6a: buffer with output enable, 6b: buffer, 6c: input decode, 7: controller, 7a
... Program control circuit, 7b ... Cascade control circuit, 7
c: memory circuit, 7d: program counter circuit, 8:
Data path section, 8a arithmetic circuit, 8b bit processing circuit, 8c memory circuit, 8d variable instruction decoder circuit,
8e: data latch circuit, 8f: output control circuit

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Hiroshi Date 1-2-1-2 Hyakudohama, Sawara-ku, Fukuoka City Inside Kyushu System Information Technology Research Institute (72) Inventor Hiroto Yasuura 1-2-1-2 Hyakuchihama, Sawara-ku, Fukuoka-shi No. Kyushu System Information Technology Research Institute

Claims (1)

[Claims] 1. A variable instruction set is input from the outside, and a controller unit that stores the input variable instruction set, and a variable instruction set that receives an input to be processed and is stored in the controller unit. A plurality of basic unit cells comprising a data bus unit for performing a predetermined operation on the input to be processed and outputting a processed output, and an input between the basic unit cells of the plurality of basic unit cells. And a switch control circuit for switching an output connection relationship.