JP5071497B2 - AD converter, current detector using AD converter, and digital servo controller using current detector - Google Patents

Description

  The present invention relates to an AD converter that converts an analog signal into a digital signal, a current detector that detects a current using the AD converter, and a digital servo control device that uses the current detector.

In general, the ΔΣ type AD converter is a method of sampling with an AD converter and obtaining AD conversion data by averaging processing. Therefore, the AD conversion data includes a quantization error, and the smaller the number of samplings, There was a problem that AD conversion accuracy was poor.
In order to solve this problem, the applicant of the present application has proposed an AD conversion apparatus in which the AD conversion data generation unit is configured to parallelize a plurality of channels to increase the number of samplings and improve the AD conversion accuracy (for example, Patent Documents). 1).
That is, the AD converter has a plurality of channels of ΔΣ type AD converters including a ΔΣ modulator, a plurality of AD conversion data generation units that output AD conversion data and an AD conversion completion signal, an AD conversion time measurement unit, and the like. The AD conversion completion signal from the ΔΣ type AD converter that takes the longest AD conversion is selected as an interrupt signal. Therefore, when all AD conversions are completed, the digital signal processing means is interrupted and the AD conversion data is read. be able to. For this reason, there is no problem even if the AD converter has a difference in AD conversion time due to manufacturing variations, and it is only necessary to complete AD conversion once per channel while an interrupt occurs, so AD conversion per channel The time required can be increased, and the number of samplings can be increased in order to improve the conversion accuracy, thereby improving the AD conversion accuracy.

Japanese Patent Application No. 2009-050136 (pages 6-7, Fig. 1)

However, in the above conventional AD converter, all ΔΣ AD converters have a large difference in AD conversion time due to manufacturing variations, that is, the interrupt selection signal always selects a signal from the same ΔΣ AD converter. The selected AD conversion completion signal is used as it is as an interrupt signal to the digital signal processing means. However, there are ΔΣ type AD converters that have almost no difference in AD conversion time. Coincidentally, if there is almost no difference between the AD conversion time of the slowest ΔΣ type AD converter and the next slowest ΔΣ type AD converter, the AD conversion completion signal selected by the interrupt selection signal is the temperature fluctuation or voltage fluctuation. The digital signal processing means is interrupted continuously unexpectedly, interrupt processing is executed twice, the interrupt processing time is extended, the control cycle is disturbed, and the motor operates abnormally as a result. There was a problem of causing malfunctions such as
That is, referring to FIG. 2, since the AD conversion time 81 is 82 us and the AD conversion time 82 is 83 us and the AD conversion time 82 is late in the first direction, the interrupt selection signal 8 becomes “2” and the AD conversion is performed. The completion signal 72 is selected. However, before and after the AD conversion time 82 changes from 83 us to 81 us, the interrupt selection signal 8 changes from “2” to “1” immediately after the low pulse of the AD conversion completion signal 72 is output, and the AD conversion is completed. Since the selection is switched to the signal 71, the Low pulse of the AD conversion completion signal 71 is output continuously, and in the conventional method, the output signal is such that the Low pulse is continuously generated unexpectedly as an interrupt signal. For this reason, execution of the first interrupt processing is started by the first Low pulse, and the status of the second interrupt generation is held by the next Low pulse during the execution, and when the first interrupt processing is completed, A second interrupt process is executed. As a result, the interrupt processing time is doubled by the second interrupt processing that should not be executed originally, and during that time, another process cannot be executed and the process is not completed as scheduled, and the control cycle is disturbed. May occur, causing the motor to operate abnormally.

  The present invention has been made in view of such problems. Even when ΔΣ type AD converters having almost no difference in AD conversion time are used, a more reliable AD conversion apparatus and the AD conversion apparatus are provided. Provided are a current detector used and a digital servo control device using the current detector.

In order to solve the above problem, a typical configuration in the present invention is as follows.
Each of the AD conversion devices receives a plurality of ΔΣ AD converters 511, 512, and 51n that each receive an analog signal, start AD conversion by an AD conversion start signal, and output an AD conversion completion signal when AD conversion ends, A logic circuit that generates one interrupt signal 7 from AD conversion completion signals 71, 72, and 7n output from a plurality of ΔΣ AD converters; and a plurality of ΔΣ AD converters 511, 512, The digital signal processing means 21 that reads 51n AD conversion data 61, 62, and 6n and performs arithmetic processing, and the ΔΣ AD converters 511, 512, and 51n are connected in parallel to the output EO of the ΔΣ modulator 41 and ΔΣ modulator 41. The operation is performed by the connected AD conversion data generation units 181, 182, 18 m and the start trigger 23 output from the digital signal processing means 21. A timing generation circuit 20 to be started, a plurality of AD conversion start signals 121, 122, and 12m output from the timing generation circuit 20 with a time difference, and output from the AD conversion data generation units 181, 182 and 18m based on the AD conversion start signal AD conversion for selecting one AD conversion data 61 from the plurality of AD conversion data 161, 162, 16m based on a plurality of AD conversion data 161, 162, 16m and a channel selection signal 91 output from the timing generation circuit 20 A plurality of AD conversion completion signals based on a data selector 241, a plurality of AD conversion completion signals 171, 172, 17 m output from a plurality of AD conversion data generation units, and a channel selection signal 91 output from the timing generation circuit 20. 171, 172, 17m complete AD conversion An AD conversion completion signal selector 251 that selects the signal 71, an AD conversion time measurement counter 221 that starts counting when an AD conversion start signal 121 is input, and an AD conversion time holding unit 231 that holds an AD conversion time based on the AD conversion completion signal 171 The logic circuit compares a plurality of AD conversion times 81 output from the plurality of ΔΣ AD converters 511, 512, 51n, and selects a ΔΣ AD converter having the longest AD conversion time, An interrupt signal for selecting one interrupt signal from a plurality of AD conversion completion signals 71, 72, 77n output from a plurality of ΔΣ AD converters 511, 512, 51m based on the interrupt selection signal 8 output from the comparator 22. An interrupt masking the generation of an interrupt signal for a certain period of time after the generation of the interrupt signal in the selector 19 and the subsequent stage of the interrupt signal selector 19 And an embedded signal mask circuit 27.
Another typical configuration in the present invention is as follows.
The current detector detects the current supplied to the motor 11 and performs digital signal processing means 9 for performing arithmetic processing based on the detected current signal and the digital command signal C1, and the electric motor applied voltage based on the arithmetic processing result of the digital signal processing means. A power conversion means 10 that performs PWM control, detects current supplied to the motor 11 in an analog manner, and outputs current detection signals iA1 and iA2, and a digital current detection signal that digitizes the current detection signal. The AD conversion apparatus described above outputs iD1 and iD2 and outputs an interrupt signal 7 to the digital signal processing means.
Another typical configuration in the present invention is as follows.
The digital servo control device includes an electric motor 11, position detecting means for detecting the relative position of the rotor and stator of the electric motor, the above-described current detector for detecting the current supplied to the electric motor, a detected current signal, and a digital signal. The digital signal processing means 9 that performs arithmetic processing based on the command signal C1 and the power conversion means 10 that PWM-controls the motor applied voltage based on the arithmetic processing result of the digital signal processing means are provided.

According to the present invention, it is possible to prevent the occurrence of malfunctions due to the occurrence of interrupt signals continuously unscheduled, and it is possible to perform highly reliable AD conversion processing.
Further, according to the present invention, the mask time can be arbitrarily set. Therefore, even if the degree of manufacturing variation or the AD conversion time changes depending on the type of the ΔΣ AD converter, the mask time can be set as desired. It can be flexibly changed by changing the value.
In addition, according to the present invention, since a highly reliable AD converter is used, a highly reliable current detection process can be performed.
In addition, according to the present invention, since a highly reliable current detector is used, safe and highly reliable digital servo control can be performed.

1 is a circuit diagram of an AD conversion apparatus according to a first embodiment of the present invention. Timing chart showing operation in the first embodiment The system block diagram of the digital servo control apparatus using the current detector which shows 2nd Example of this invention Timing chart showing operation in the second embodiment Configuration example when the mask time setting register of the interrupt signal mask circuit in the first and second embodiments is provided

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of an AD conversion apparatus showing a first embodiment of the present invention.
In FIG. 1, reference numeral 511 denotes a ΔΣ AD converter, which receives an analog signal 101, performs ΔΣ modulation by a ΔΣ modulator 41, and outputs a code pulse EO. The ΔΣ modulator 41 compares the subtraction circuit 401 that subtracts the analog signal 101 and EO, the integration circuit 411 that integrates the subtraction result, the integration result and the reference level, and the code is synchronized with the clock 421. The comparator 431 outputs a pulse EO.
Reference numeral 141 denotes a digital filter which receives the code pulse EO, filters it, and outputs it as a digital signal. Reference numeral 151 denotes an averaging circuit, which calculates an average value of a digital signal output from the digital filter 141 in a period from input of the AD conversion start signal 121 to completion of AD conversion and output of the AD conversion completion signal 171. , And output as AD conversion data 161. Reference numeral 181 denotes an AD conversion data generation unit which includes a digital filter 141 and an averaging circuit 151.
Further, a circuit having the same configuration as the AD conversion data generation unit 181 is connected to the output EO of the comparison circuit 431 in parallel with a plurality of channels 181, 182,..., 18 m, and the AD conversion data generation unit 182 starts AD conversion. The AD conversion completion signal 172 and AD conversion data 162 are output in response to the signal 122, and the AD conversion data generation unit 18m receives the AD conversion start signal 12m and outputs the AD conversion completion signal 17m and AD conversion data 16m. Reference numeral 20 denotes a timing generation circuit which starts its operation in response to a start trigger 23 input from the digital signal processing means 21 and outputs AD conversion start signals 121, 122,..., 12m and a channel selection signal 91. Reference numeral 241 denotes an AD conversion data selector which selects AD conversion data 161 when the channel selection signal 91 is 1, AD conversion data 162 when the channel selection signal 91 is 2, AD conversion data 16m when the channel selection signal 91 is 2, and AD conversion data 61 Is output. Reference numeral 251 denotes an AD conversion completion signal selector which selects an AD conversion completion signal 171 when the channel selection signal 91 is 1, an AD conversion completion signal 172 when the channel selection signal 91 is 2, an AD conversion completion signal 17m when the channel selection signal 91 is m, An AD conversion completion signal 71 is output. Reference numeral 221 denotes an AD conversion time measurement counter which is once cleared to 0 value at the rising edge of the AD conversion start signal 121, then counted up by the system clock CP, and is sent to the AD conversion time holding unit 231 at the rising edge of the AD conversion completion signal 171. The counter value is held and AD conversion time 81 is output.
Similarly, a plurality of circuits having the same configuration as the ΔΣ AD converter 511 are arranged in parallel with 511, 512,..., 51n, and the ΔΣ AD converter 512 receives the analog signal 102 and the start trigger 23, The AD conversion data 62, the AD conversion completion signal 72, and the AD conversion time 82 are output, the ΔΣ AD converter 51n receives the analog signal 10n and the start trigger 23, and the AD conversion data 6n, the AD conversion completion signal 7n, and the AD conversion Output time 8n.
A comparator 22 compares the AD conversion times 81, 82,..., 8n, determines the one with the latest AD conversion time, and outputs the interrupt selection signal 8. An interrupt signal selector 19 selects an AD conversion completion signal 71 when the interrupt signal 8 is 1, selects an AD conversion completion signal 72 when the interrupt signal 8 is 2, and selects an AD conversion completion signal 7n when the interrupt signal 8 is n. Output. The interrupt signal mask circuit 27 is composed of a counter 24 and an OR element 26. The interrupt signal mask circuit 27 calculates the logical sum of the mask signal 25 output from the counter 24 and the interrupt signal 7a, and outputs the interrupt signal 7. Upon receiving the falling edge of the interrupt signal 7, the digital signal processing means 21 reads the AD conversion data 61, 62,..., 6n and performs arithmetic processing.

Next, the operation of the present invention will be described.
FIG. 2 is a timing chart showing the operation in the first embodiment.
In FIG. 2, AD conversion of the first channel in the ΔΣ AD converter 511 starts at the rising edge of the AD conversion start signal 121. Similarly, AD conversion start signals 122,..., 12m are generated with a certain time difference from the AD conversion start signal 121, and AD conversion of the second channel,.
When the AD conversion of the first channel is completed, the channel selection signal 91 selects the first channel, the AD conversion data 161 is output to the AD conversion data 61, and the AD conversion completion signal 171 is output to the AD conversion completion signal 71. The
Similarly, when AD conversion of the second channel,..., M channel is completed, the channel selection signal 91 selects the second channel,..., M channel, and the AD conversion data 162. 16m is output to AD conversion data 61, AD conversion completion signal 172, ..., 17m is output to AD conversion completion signal 71. The AD conversion time 81 is held at the rising edge of the AD conversion completion signal 171.
Similarly, from the ΔΣ AD converters 512,..., 51n, AD conversion data 62,..., 6n and AD conversion completion signals 72,. Is output. Here, the ΔΣ type AD converters 511, 512,..., 51n have different AD conversion times due to manufacturing variations, but the latest AD conversion completion signal is selected as the interrupt signal 7a by the interrupt selection signal 8. However, when the AD conversion completion signal selected by the interrupt selection signal 8 is switched, interrupts may occur continuously unexpectedly as shown in the middle part of the interrupt signal 7a in FIG.
The counter 24 of the interrupt signal mask circuit 27 starts counting up in synchronization with the system clock CP after the counter value is once cleared to 0 immediately after the rising edge of the interrupt signal 7a, and stops counting up when full counting is performed. The mask signal 25 becomes High level for a certain time until the count is stopped, and the interrupt signal 7a is masked during this period. Therefore, the subsequent interrupt signal 7a generated continuously is not output to the digital signal processing means 21 as the interrupt signal 7. Here, if the mask time is set to about half of the interval of the Low pulse of the interrupt signal 7, the operation can be performed without any problem.
As described above, when interrupts occur unexpectedly continuously, unnecessary interrupts that occur later are masked and output to the digital signal processing means 21 as the interrupt signal 7, so that the interrupts are performed normally. AD conversion data 61, 62,..., 6n can be read.

FIG. 3 is a system configuration diagram of a digital servo control device using a current detector showing a second embodiment of the present invention.
In FIG. 3, the electric motor 11 will be described below using a three-phase electric motor as an example.
First, the current detection means 13 detects two currents of the three phases supplied to the three-phase motor 11 in an analog manner, and outputs a first current detection signal iA1 and a second current detection signal iA2.
The first ΔΣ AD converter 511 and the second ΔΣ AD converter 512 receive the first current detection signal iA1 and the second current detection signal iA2, respectively, digitize them, and perform the first digital The current detection signal iD1 and the second digital current detection signal iD2 are output.
The position detection means 12 detects the relative position between the rotor and the stator of the electric motor 11 and outputs a position detection signal S1.
Reference numeral 22 denotes a comparator that compares the AD conversion times 81 and 82, discriminates those having a slow AD conversion time, and outputs an interrupt selection signal 8. An interrupt signal selector 19 selects an AD conversion completion signal 71 when the interrupt selection signal 8 is 1, selects an AD conversion completion signal 72 when the interrupt selection signal 8 is 2, and outputs an interrupt signal 7a. The interrupt signal mask circuit 27 is composed of a counter 24 and an OR element 26. The interrupt signal mask circuit 27 calculates the logical sum of the mask signal 25 output from the counter 24 and the interrupt signal 7a, and outputs the interrupt signal 7. The digital signal processing means 9 inputs the first digital current detection signal iD1, the second digital current detection signal iD2, the position detection signal S1 and the digital command signal C1, and calculates them when the falling edge of the interrupt signal 7 is received. By processing, the first PWM command signal P1, the second PWM command signal P2, the third PWM command signal P3, the fourth PWM command signal P4, the fifth PWM command signal P5, and the sixth PWM command signal. P6 is output. The digital signal processing means 9 is constituted by a circuit including a current amplifier, a speed amplifier, a position amplifier and a PWM generation circuit by a digital circuit or software using a DSP, a microcomputer or the like.
The power conversion means 10 includes six sets of power elements and freewheeling diodes in a three-phase bridge configuration, and the first, second, third, fourth, fifth, and sixth PWM command signals P1, The motor applied voltage is PWM controlled according to P2, P3, P4, P5, and P6.
Next, the operation of the present invention will be described.
FIG. 4 is a timing chart showing the operation in the second embodiment.
In FIG. 4, the first ΔΣ type AD converter 511 and the second ΔΣ type AD converter 512 are described below with an example in which AD conversion data generation units 181, 182, 183, and 184 are parallelized in four channels. Do.
At the rising edge of the AD conversion start signal 121, AD conversion of the first channel in the ΔΣ AD converter 511 starts. Similarly, AD conversion start signals 122,..., 124 are generated with a certain time difference from the AD conversion start signal 121, and AD conversion of the second channel,. When the AD conversion time for the first channel is completed by predicting the AD conversion time in advance and switching the channel according to the set value, the channel selection signal 91 selects the first channel, and the AD conversion data 161 Are output to the AD conversion data 61, and the AD conversion completion signal 171 is output to the AD conversion completion signal 71.
Similarly, when the AD conversion of the second channel,..., And the fourth channel is completed, the channel selection signal 91 selects the second channel,..., The fourth channel, and the AD conversion data 162. 164 is output to AD conversion data 61, AD conversion completion signal 172,... 174 is output to AD conversion completion signal 71. The AD conversion time 81 is held at the rising edge of the AD conversion completion signal 171.
Similarly, the AD conversion data 62, the AD conversion completion signal 72, and the AD conversion time 82 are output from the ΔΣ AD converter 512. Here, the ΔΣ type AD converters 511 and 512 have different AD conversion times due to manufacturing variations, but the later AD conversion completion signal is selected as the interrupt signal 7 a by the interrupt selection signal 8. However, as shown in the figure, when the AD conversion completion signal selected by the interrupt selection signal 8 is switched, interrupts may occur continuously unexpectedly.
The counter 24 starts counting up in synchronization with the system clock CP after the counter value is once cleared to 0 immediately after the rising edge of the interrupt signal 7a, and stops counting up when the counter 24 is fully counted. The mask signal 25 becomes High level for a fixed time until the count is stopped. During this period, the interrupt signal 7 a is masked and output to the digital signal processing means 9 as the interrupt signal 7.
The first PWM command signal P1 is a PWM signal generated for each PWM carrier, and the current is the first current detection signal iA1.
The ΔΣ AD converter 511 samples a digital signal obtained by digitizing iA1 a plurality of times in a period obtained by multiplying the period of the PWM carrier by the number of channels of the AD data generation unit. In FIG. 4, as an example, a case where sampling is performed 16 times in a period four times the period of the PWM carrier is shown.
That is, the digitized digital signal of iA1 is sampled 16 times, and the averaging circuit 151 obtains the average value of the 16 samplings, and this is used as the digital current detection signal iD1.
As described above, when interrupts occur unexpectedly continuously, unnecessary interrupts that occur later are masked and output to the digital signal processing means 9 as the interrupt signal 7, so that the interrupt is performed normally, The digital current detection signals iD1 and iD2 can be read.
FIG. 5 shows a configuration example in the case where the mask time setting register of the interrupt signal mask circuit in the first embodiment and the second embodiment is provided.
In FIG. 5, the interrupt signal mask circuit 27 is composed of a counter 24, an OR element 26, and a mask time setting register 28. The interrupt signal mask circuit 27 takes the logical sum of the mask signal 25 output from the counter 24 and the interrupt signal 7a. Output.
The mask time setting register 28 is set to an arbitrary value in advance by the CPU or the like, and after the counter value is once cleared to 0 value immediately after the rising edge of the interrupt signal 7a, the counter is counted up in synchronization with the system clock CP. When the counter value of the counter 24 is equal to the mask time setting value set in the mask time setting register 28, the count-up is stopped. In the meantime, the interrupt signal 7 a is masked, and the subsequent interrupt signal 7 a generated continuously is not output to the digital signal processing means 21 as the interrupt signal 7.
In the above embodiment, the interrupt signal mask circuit 27 is described as an example composed of the counter 24 and the OR element 26. However, any circuit that performs the same operation may be used.

511, 512, 513 ΔΣ AD converters 7, 7a Interrupt signal 8 Interrupt selection signals 9, 21 Digital signal processing means 10 Power conversion means 11 Electric motor 12 Position detection means 13 Current detection means 19 Interrupt signal selector 20 Timing generation circuit 21 Digital Signal processing means 22 Comparator 23 Start trigger 24 Counter 25 Mask signal 26 OR element 27 Interrupt signal mask circuit 28 Mask time setting register 41 ΔΣ modulator 61, 62,..., 6n, 161, 162,. AD conversion data 71, 72, ..., 7n AD conversion completion signals 81, 82, ..., 8n AD conversion time 91 Channel selection signals 101, 102, ..., 10n Analog signals 121, 122, ... , 12m AD conversion start signal 141 Digital filter 151 Averaging , 17m AD conversion completion signal 181, 182,..., 18m AD conversion data generation unit 221 AD conversion time measurement counter 231 AD conversion time holding unit 241 AD conversion data selector 251 AD conversion completion signal Selector 401 Subtraction circuit 411 Integration circuit 421 Clock 431 Comparison circuit

Claims (5)

When an analog signal is inputted, the AD conversion starts when accepting the AD conversion start signal, terminates Then a plurality of ΔΣ-type AD converter output the AD conversion completion signal, the ΔΣ-type AD converter of the multiple AD conversion a logic circuit for generating the AD conversion complete signal or al No. one interrupt signals outputted respectively from the vessel, the AD conversion data of the interrupt by Rifuku number of the reception of the signal the ΔΣ-type AD converter is generated in AD converter that includes a digital signal processing hand stage for performing write Nde processing read data,
The ΔΣ AD converter is
A plurality of AD conversion data generation unit that will be connected in parallel to the output side of the ΔΣ modulator,
Outputs with a time difference of the AD conversion start signal to the plurality of AD conversion data generation unit, a timing generation circuits for outputting sequentially indicate channel selection signal any one of a plurality of the AD conversion data generation unit And
And the AD conversion data selector to be outputted to the digital signal processing unit selects the AD conversion data generated by the AD conversion data generation unit, wherein the channel selection signal is indicated,
AD conversion completion signal selector to be output to the logic circuit selects the AD conversion completion signal outputted by the AD conversion data generation unit, wherein the channel selection signal is indicated,
An AD conversion time which is a time from reception of the AD conversion start signal output to the predetermined AD conversion data generation unit by the timing generation circuit until reception of the AD conversion completion signal output from the AD conversion data generation unit An AD conversion time holding unit for holding
Said logic circuit,
A comparator for the AD conversion time selects the longest the ΔΣ-type AD converter by the AD conversion time holding unit of the ΔΣ-type AD converter of multiple compares the AD conversion time for holding respectively,
And the interrupt signal selector for selecting the AD conversion completion signal corresponding to the ΔΣ-type AD converter which is selected by said comparator as said interrupt signal,
The provided after the interruption signal selector, AD, wherein the over interrupt signal a predetermined time after receiving the interrupt signal from the selector, Ru and an interrupt signal masking circuit for masking the acceptance of new said interrupt signal Conversion device. It said interrupt signal mask circuits is
Consists of a counter and OR element, once cleared starts counting to the counter value is 0 values immediately interrupt signal is generated, a predetermined time to count stops by full count, to mask the interrupt signal The AD conversion apparatus according to claim 1 , wherein It said interrupt signal mask circuits is
It is composed of a counter and the OR element and the mask time setting register, previously set to an arbitrary value, an interrupt signal is generated a counter value counter is stopped with respect to the mask time setting register as a mask time set value claim counter value immediately after once started cleared and count to zero value, a predetermined time until the counter value and the mask time setting value is counted equals stop, characterized in that masking the interrupt signal AD converter according to 1. PWM and a digital signal processing hand stage, the based have been motor applied voltage to the arithmetic processing result of the digital signal processing hand stage for performing arithmetic processing based on the current supplied to the electric motor and detected by the detection current signal and the digital command signal a current detector in the digital servo control device and a power conversion means to control,
A current detecting means to output a current detection signal current supplied prior Symbol motor is detected by an analog,
An AD converter according to claim 1, 2 or 3 outputs the digital current detection signal and digitizes the current detection signal and outputs an interrupt signal to said digital signal processing means
Current detector, characterized in that it comprises a. An electric motor, a position detecting means for detecting the relative position between the rotor and the stator of the motor, a current detector for detecting a current supplied to the electric motor, and the detected current signal and the digital command signal in digital servo control device including a digital signal processing hand stage, and a power conversion means to PWM control the motor applied voltage based on the operation result of the digital signal processing means for performing arithmetic processing based on,
The current detector is
5. A digital servo control device , comprising the current detector according to claim 4 .

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