JP3319701B2 - Arithmetic unit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a system for measuring
The present invention relates to an arithmetic device that calculates electric power or electric energy based on current.

[0002]

2. Description of the Related Art As a conventional arithmetic device for calculating electric power or electric energy, there is, for example, one shown in FIG. In the figure, T1 and T2 are input terminals for inputting respective voltages V1 and A1 which are directly proportional to the voltage and current of the system to be measured.
Reference numeral 02 denotes first and second A / D converters for converting the voltages V1 and A1 into digital values, respectively. Reference numeral 203 denotes a CPU, which multiplies digital value outputs from the first and second A / D converters 201 and 202 at regular intervals by software.
Integrate. This device calculates W = V1 · A1cosψ. Such an arithmetic device generally functions as a wattmeter when integrated for one or more cycles and converted into a unit time, and functions as a watt hour meter when integrated for infinite time.

Further, when calculating the reactive power, Q =
Since it is sufficient to calculate V1 · A1sinψ, a phase shift of 90 ° is required. In practice, the voltage V1 is more likely to be phase-shifted.
Performs a process of shifting the voltage V1.

[0004]

However, in the conventional arithmetic unit, whether the power or the reactive power is obtained, (a) the multiplication is performed by the software of the CPU, so that the multiplication instruction processing takes a long time. (B) Since the multiplication is performed by the software of the CPU, the software is busy, and it is difficult to perform other tasks by the software. (C) A
Since the / D converter is used, it takes a long time for conversion, and it is difficult to increase the sampling frequency. As a result, there are various problems that if the number of bits of the A / D converter is increased in order to increase the accuracy, the conversion takes time and becomes expensive.

In particular, when the reactive power is obtained, since the data of the voltage V1 is phase-shifted by the software of the CPU, if the output of the A / D converter is 16-bit data, for example, 16 There is a problem that the bits have to be shifted, the processing becomes complicated, and excessive memories and registers are required.

[0006] The present invention has been made in view of the above,
The power meter and watt-hour meter can all be built in hardware, or the CPU can be minimized by minimizing software processing.
, The cost can be reduced as a system, and the number of analog units can be reduced, so that the LSI can be reduced in size and the cost can be reduced in this regard. In addition, the sampling frequency can be increased to increase the accuracy. It is an object of the present invention to provide an arithmetic device capable of performing the above.

It is another object of the present invention to provide an arithmetic unit capable of obtaining reactive power only by adding a simple phase shift circuit as hardware to the arithmetic unit for obtaining power.

[0008]

According to a first aspect of the present invention, there is provided a method for converting an input voltage directly proportional to a voltage and a current of a system to be measured into a 1-bit code. , A second 1-bit A / D converter, and the codes output from the first and second 1-bit A / D converters, respectively, control up / down counting of clocks, and First and second up / down counters for respectively outputting A / D converted values, a latch for holding and outputting data one clock before input data, and a first and second one-bit A / D counter. Under the control of each output data of the D converter and the exclusive OR of each output data, the first and second output data of the latch are added to the output data of the latch.
An adder / subtracter that adds / subtracts each output data of the up / down counter and a numerical value 1 to output operation data proportional to a product of the respective input voltages to the latch, and an adder that integrates data output from the latch. And the gist.

With this configuration, each input voltage that is directly proportional to the voltage and current of the system to be measured is converted into a 1-bit code by the first and second 1-bit A / D converters.
The A / D conversion value of each input voltage is obtained by the first and second up-down counters. Based on this A / D conversion value, operation data proportional to the product of each input voltage is obtained by an adder / subtracter,
The amount of power is measured by adding the operation data by an adder. The power calculation device can be composed entirely of hardware, and can perform calculations without the intervention of CPU software.
It is possible to reduce the size of the LSI even if it is very small with only the D converter. Further, the A / D conversion function unit can increase the sampling frequency to achieve higher accuracy.

According to a second aspect of the present invention, in the arithmetic unit according to the first aspect, the data output from the adder is configured to be cleared at regular intervals. With this configuration, it is possible to realize a power computing device having substantially the same functions as the first aspect of the present invention.

According to a third aspect of the present invention, in the arithmetic unit according to the first aspect, provided between the first 1-bit A / D converter and the first up / down counter,
The output data of the first 1-bit A / D converter is output to the first up / down counter with a time delay of 1/4 phase of the signal of the input voltage which is directly proportional to the voltage of the measured system. The gist is that a delay circuit is further provided. With this configuration, it is possible to obtain a reactive power calculator having the same operation and effect as the above-described power calculator.

According to a fourth aspect of the present invention, in the arithmetic unit according to the third aspect, a frequency of an input voltage signal that is directly proportional to the voltage of the measured system is sequentially detected, and information on the frequency is provided to a delay circuit. The gist is that a frequency detection circuit is further provided. With this configuration, even when the frequency of the voltage of the system to be measured fluctuates, a time delay of １ ／ phase can be accurately performed.

According to a fifth aspect of the present invention, in the arithmetic unit according to the fourth aspect, the delay circuits are connected in series, and an output signal of a first 1-bit A / D converter is provided in a first stage. A plurality of shift registers that are input and operate using a clock φ as a reference signal, a decoder that decodes a signal from the frequency detection circuit, and an output signal of the decoder that is input to one input terminal and the plurality of shift registers are input. A plurality of AND gates for inputting the respective output signals of the shift register to the other input terminal, and an OR gate for inputting the respective output signals of the plurality of AND gates;
The gist is to provide.

According to a sixth aspect of the present invention, in the arithmetic unit of the third to fifth aspects, the data output from the adder is configured to be cleared at regular intervals. Make a summary. With this configuration, it is possible to realize a reactive power calculation device.

According to a seventh aspect of the present invention, in the arithmetic unit according to the first to sixth aspects, at least one of the first and second up / down counters, the adder / subtractor, the latch, and the adder is provided. The gist is that the functions of the units are configured to be executed by CPU software. With this configuration, it is possible to realize an arithmetic device that calculates the amount of power, the amount of power, the amount of reactive power, and the amount of reactive power with higher accuracy and lower cost than at least in the related art.

[0016]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a block diagram of a first embodiment of the arithmetic unit according to the present invention. In FIG. 1, T1 and T2 are input terminals for inputting voltages V1 and A1 that are directly proportional to the voltage and current of the system under test, and 101 and 102 are first and second 1-bit A / D converters called delta modulators. And incorporates comparators 103 and 104, integrators 105 and 106, and D-type flip-flops 107 and 108, respectively, and converts input voltages V1 and A1 into pulse trains f (n) and g, respectively.
(N) and output. The output timing is determined by the clock φ. That is, the first
(Or second) 1-bit A / D converter 101 (or 10
2) The comparator 103 (or 104) compares the output voltage F (n) (or G (n)) of the integrator 105 (or 106) with the magnitude of the input voltage V1 (or A1) when the clock φ rises. V1> Fa (n) (or A1> G
In the case of a (n)), an H level is output via the D-type flip-flop 107 (or 108), and the output of the integrator 105 (or 106) is added by + Δv. V1 <
When Fa (n) (or A1 <Ga (n)), the L level is output via the D-type flip-flop 107 (or 108), and the output of the integrator 105 (or 106) is added by -Δv, that is, It is subtracted by Δv. 109,110
Denote first and second up / down counters, and outputs f (n) and g (n) of the 1-bit A / D converters 101 and 102.
Up / down count is controlled by clock φ
Count the number of. The outputs of the first and second up / down counters 109 and 110 are Fd (n-1),
Gd (n-1), which is a value obtained by A / D converting the input voltages V1 and A1. 111 is an exclusive OR gate,
An exclusive OR h (n) of the outputs f (n) and g (n) of the first and second 1-bit A / D converters 101 and 102 is output. 112 is an adder / subtractor, which has four inputs A, B, C,
D digital value (output value W (n-1) of latch 113,
The output value Fd (n−
1), output value Gd of second up / down counter 110
(N-1) and numerical value +1) are added and subtracted, and B, C, D
As for the input, the signal (g) input to the (+/-) terminal
(N), f (n), h (n)) determine the adjustment. That is, if the (+/-) terminal is at the H level, addition is performed, and if the (L / L) level is at the L level, subtraction is performed. The output of the adder / subtractor 112 is a value W (n) proportional to the product V1 · A1 of the input voltage at each instant. Reference numeral 113 denotes a latch, which outputs a signal W (n-n) one clock before the output W (n) of the adder / subtractor 112 according to the clock φ.
Latch 1). Therefore, its output is W (n-1)
It is. Reference numeral 114 denotes an adder. The sum of the output W (n-1) of the latch 113 and the adder 114 up to one clock before, that is, W (i), i.
Performs addition with the integral value from 1 to (n−2). As a result, the integrated value ∫W (i) of the multiplication value of the input voltages V1 and A1 at each instant is obtained.

Next, the operation of the arithmetic unit configured as described above will be described with reference to FIGS. 2 (a) to 2 (g). 2 (a) to 2 (g) show the waveforms of the respective parts, where V1 in FIG. 2 (a) and A1 in FIG. 2 (d) are a voltage and a voltage in direct proportion to the voltage and current of the measured system. F of 2 (c)
(N) and g (n) in FIG. 2 (f) are pulses obtained by delta-modulating V1 and A1, respectively, and their values are only +1 or -1. Fa (n) in FIG. 2B and Ga in FIG.
(N) is the first and second 1-bit A / D converters 101, 1
02 are the outputs of the integrators 105 and 106 and are the coded values of the respective input voltages V1 and A1. FIG.
N in (g) represents the n-th in FIGS. 2 (a) to 2 (f).

The purpose of the arithmetic unit of this embodiment is to find the product V1 · A1 of the input voltage. V1 is F
(N) and A1 is approximately equal to G (n), so F
(N) · G (n) = W (n). The output of the first 1-bit A / D converter 101 up to n operations is represented by f
(1), f (2), f (3), ..., f (n),
The output voltage Fa (n) of the integrator 105 at that time can be expressed by equation (1).

## EQU1 ## Fa (n) = (f (1) + f (2) + f (3) +... + F (n)). Δv (1)

The first up / down counter 109
Up / down count is controlled by f (n), and the number of clocks φ is counted.
Is a digitally coded value Fd. However, due to the clock φ, the value of the (n−1) -th value Fd is not Fd (n).
(N-1) will be output. The value F to be obtained now
(N) · G (n) = W (n) can be expressed by equation (2).

W (n) = F (n) · G (n) = (f (1) + f (2) + f (3) +... + F (n)) (g (1) + g (2) + g (3) + ... + g (n)) = (F (n-1) + f (n)). (G (n-1) + g (n)) (2)

Here, in equation (2), f (n) = ±
Since 1, g (n) = ± 1, Equation (2) can be represented by the following four states.

## EQU3 ## When f (n) = + 1 and g (n) = + 1, W (n) = (F (n-1) + f (n)). (G (n-1) + g (n)) = F (n-1) .G (n-1) + F (n-1) + G (n-1) + 1 = W (n-1) + F (n-1) + G (n-1) +1 ... (3 ) When f (n) = + 1 and g (n) = − 1, W (n) = (F (n−1) + f (n)) · (G (n−1) + g (n)) = F (N-1) G (n-1) -F (n-1) + G (n-1) -1 = W (n-1) -F (n-1) + G (n-1) -1 ... (4) When f (n) = − 1 and g (n) = + 1, W (n) = (F (n−1) + f (n)) · (G (n−1) + g (n)) = F (n-1) .G (n-1) + F (n-1) -G (n-1) -1 = W (n-1) + F (n-1) -G (n-1)- 1 ... (5) When (n) =-1, g (n) =-1, W (n) = (F (n-1) + f (n)). (G (n-1) + g (n)) = F ( (n-1) .G (n-1) -F (n-1) -G (n-1) + 1 = W (n-1) -F (n-1) -G (n-1) +1 ... ( 6)

Accordingly, the adder / subtractor 11 is operated by the latch 113.
2 is sampled from the output data W (n),
Sampled as W (n-1) using a clock delay, the output data W (n-1) of the latch 113 by the adder / subtractor 112, the first up / down counter 10
By adding / subtracting the output data Fd (n-1) of No. 9, the output data Gd (n-1) of the second up / down counter 110, and the numerical value 1, W (n) can be obtained.

The meaning of the addition / subtraction will be explained in an easy-to-understand manner with reference to FIGS. 3 (a) to 3 (d). The above cases correspond to FIGS. 3A to 3D, respectively.
In each figure, the portion surrounded by a solid line is W (n).
And the portion surrounded by the dotted line is W (n-1). Also, the portion of the diagonally oblique line to the right is F (n-1), and the portion of the diagonal line to the left is G (n-1).

In the above case, as shown in FIG. 3A, when W (n) is obtained, F (n-1) is added to W (n-1).
If only (n-1) and G (n-1) are added, 1 is insufficient, so 1 is added. In the above case, as shown in FIG. 3 (b), when W (n) is obtained, F (n-1) is subtracted from W (n-1) to obtain G (n).
When -1) is added, 1 is added, so 1 is subtracted. In the above case,
As shown in FIG. 3C, when calculating W (n), W
When F (n-1) is added to (n-1) and G (n-1) is subtracted, one extra is added, so 1 is subtracted. In the above case, FIG.
As shown in (1), when W (n) is obtained, when F (n-1) and G (n-1) are subtracted from W (n-1), 1 is lacking, so 1 is added. .

By the way, in this case, each data Fd (n-
1), Gd (n-1), and addition and subtraction of 1 are g
(N), f (n), h (n) (E of f (n) and g (n)
Xnor). Thereby, the adder / subtractor 11
The output data of No. 2 is a value W (n) that is directly proportional to the product V1 · A1 of the input voltages. Since W (n) is a multiplied value of V1 and A1 at the n-th instant, V1 · A1 = W (n) or W (n−1) in order to actually obtain the power amount and power.
Is required. Therefore, in the adder 114, the output data of the adder 114 itself, that is, W (i),
The integration is performed by adding the integral value of i = 1 to (n−2) and W (n−1).

In this embodiment having the above-described configuration and operation, by performing infinite integration by the adder 114,
An electric energy calculation device for measuring the electric energy is realized.

As described above, according to this embodiment, the electric energy calculation device can be entirely constituted by hardware, and the calculation can be performed without the intervention of CPU software, and the size of the CPU can be reduced. it can. Further, the analog section is only a 1-bit A / D converter, and the analog section is very small. Further, the A / D conversion function unit can increase the sampling frequency to achieve higher accuracy.

The adder 114 is operated for a predetermined time, for example, 1
By clearing every second or every several cycles of the AC signal to be measured and converting the integrated value up to that time into a unit time, a power calculation device for measuring power is realized.

Furthermore, the whole of or a part of the first and second up-down counters 109 and 110 and thereafter can be implemented by CPU software, thereby realizing a low-cost power amount or power calculation device. . In particular, it is realistic and effective to perform the operations after the adder / subtractor 112 by the CPU software.

In the above embodiment, the adder 11
4 may be used as the output W (n) of the adder / subtractor 112 instead of the output W (n-1) of the latch 113, and the delta modulator (1 bit A / D converters 101 and 10)
2) A delta-sigma modulator can be used as a delta-sigma modulator,
The effect is obtained.

FIG. 4 is a block diagram of a second embodiment of the arithmetic unit according to the present invention, showing an embodiment for calculating the reactive power or the amount of reactive power. As described above, in order to calculate the reactive power or the reactive power amount, a phase shift of 90 ° is required, but in this embodiment, the first 1
A delay circuit 115 is provided between the bit A / D converter 101 and the first up / down counter 109. The delay circuit 115 includes, for example, a shift register or a digital P
LL, CCD, etc., and outputs the output f (n) of the first 1-bit A / D converter 101 for a time corresponding to a quarter phase of a signal input to the terminal T1 (for example, when the frequency of the signal is The signal is delayed as 5 ms at 50 Hz) and output as the signal fr (n).

First and second 1-bit A / D converters 10
1,102, first and second down counters 109,1
10, adder / subtractor 112, latch 113, and adder 11
Operation 4 is the same as in the first embodiment. However,
In this embodiment, the signal f
Since (n) is shifted by 90 °, the adder / subtractor 112 calculates Fr (n) · G (n), and as a result, the reactive power or the reactive power amount can be calculated.

FIG. 5 is a block diagram of a third embodiment of the arithmetic unit according to the present invention. In this embodiment, a frequency detection circuit 116 is further added to the configuration of the second embodiment. The frequency detection circuit 116 sequentially detects the frequency of the signal V1 and supplies the information to the delay circuit 115. Since the delay circuit 115 receives the information on the frequency of the signal V1 from the frequency detection circuit 116, the signal f (n)
Can be accurately performed.

FIG. 6 is a diagram showing a specific configuration example of the delay circuit 115 in the third embodiment. In this figure, this delay circuit is connected in series,
, A plurality of shift registers 122 that operate with the clock φ as a reference signal, a decoder 121 that decodes a signal from the frequency detection circuit 116, and a decoder. A plurality of AND gates 123 that input each of the output signals of the shift registers 121 to one input terminal and input the respective output signals of the plurality of shift registers 122 to the other input terminal
And an OR gate 124 to which each output signal of the plurality of AND gates 123 is input.

Each AND gate 123 and OR gate 1
24, an output of an appropriate number of stages is selected from the outputs of each shift register 122 and output as a signal fr (n). With such a configuration, even if the frequency of the signal V1 fluctuates, the phase of the signal f (n) can be accurately shifted based on the frequency information from the frequency detection circuit 116.

[0036]

As described above, according to the first aspect of the present invention, each input voltage that is directly proportional to the voltage and current of the system to be measured is converted by the first and second 1-bit A / D converters. Each code is converted into a 1-bit code, and the A / D converted value of each input voltage is obtained by the first and second up-down counters. Operation data proportional to the product of the input voltages is obtained by the adder / subtractor based on the A / D conversion value, and the electric energy is measured by adding the operation data by the adder. The power calculation device can be composed entirely of hardware, and calculation can be performed without CPU software,
In addition, the analog section is only a 1-bit A / D converter and is very small. Further, the A / D conversion function unit can increase the sampling frequency to achieve higher accuracy.

According to the second aspect of the present invention, since the data output from the adder is configured to be cleared at regular intervals, the power having substantially the same effect as the first aspect of the present invention is obtained. It is possible to realize an arithmetic device.

According to the present invention, the first 1-bit A / D converter is provided between the first 1-bit A / D converter and the first up / down counter. A delay circuit that delays the output data by a quarter of a phase of the signal of the input voltage that is directly proportional to the voltage of the measured system and outputs the delayed data to the first up / down counter; A reactive energy calculator having the same operation and effect as that of the calculator can be obtained.

According to the fourth aspect of the present invention, there is further provided a frequency detecting circuit for sequentially detecting the frequency of the signal of the input voltage which is directly proportional to the voltage of the measured system, and providing the information of the frequency to the delay circuit. Therefore, even when the frequency of the voltage of the system to be measured fluctuates, a time delay of 1/4 phase can be accurately performed.

According to the fifth aspect of the present invention, the delay circuits are connected in series, and the first one bit A /
A plurality of shift registers to which an output signal of the D converter is input and which operates using a clock φ as a reference signal, a decoder that decodes a signal from the frequency detection circuit, and an output signal of each of the decoders is provided to one input terminal. A plurality of AND gates for inputting, and inputting respective output signals of the plurality of shift registers to the other input terminal,
And an OR gate for inputting the output signal of each of the plurality of AND gates, so that it is possible to reliably adapt to fluctuations in frequency.

According to the sixth aspect of the present invention, since the data output from the adder is configured to be cleared at regular intervals, substantially the same effect as the first aspect of the present invention is obtained. It is possible to realize a reactive power calculation device having the same.

According to the invention of claim 7, the first,
A second up / down counter, the adder / subtractor, the latch, and at least a part of the adder
Because it is configured to be executed by software, at least the accuracy and cost compared to the conventional, energy, power,
It is possible to realize an arithmetic device for calculating the reactive power and the reactive power.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a first embodiment in an arithmetic unit of the present invention.

FIG. 2 is a diagram showing waveforms of respective units for explaining the operation of the first embodiment.

FIG. 3 is a diagram for explaining the meaning of addition and subtraction by an adder / subtractor in the present invention.

FIG. 4 is a configuration diagram of a second embodiment in the arithmetic device of the present invention.

FIG. 5 is a configuration diagram of a third embodiment in the arithmetic device of the present invention.

FIG. 6 is a circuit diagram illustrating an example of a delay circuit.

FIG. 7 is a block diagram of a conventional arithmetic device.

[Explanation of symbols]

 101, 102 First and second 1-bit A / D converters 109, 110 First and second up / down counters 111 Exclusive OR gate 112 Adder / subtractor 113 Latch 114 Adder 115 Delay circuit 116 Frequency detection circuit 121 Decoder 122 shift register 123 AND gate 124 OR gate

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G01R 21/133 G01R 21/00 G01R 22/00 110-130

Claims (7)

(57) [Claims] A first and a second 1-bit A / D converter for converting each input voltage directly proportional to a voltage and a current of a system to be measured into a 1-bit code, respectively; Up / down counting of a clock is controlled by the code output from the 1-bit A / D converter, and first and second up / down counters respectively outputting A / D conversion values of the input voltages; A latch for holding and outputting data one clock before the input data, and a control for controlling each output data of the first and second 1-bit A / D converters and an exclusive OR of the output data. Then, by adding / subtracting each output data of the first and second up / down counters and a numerical value 1 to the output data of the latch, operation data proportional to the product of the respective input voltages is output to the latch. An arithmetic unit comprising: an adder / subtracter; and an adder for integrating data output from the latch. 2. The arithmetic unit according to claim 1, wherein data output from said adder is cleared at regular intervals. 3. The system according to claim 1, further comprising a first bit A / D converter provided between the first 1-bit A / D converter and the first up / down counter. 2. The arithmetic device according to claim 1, further comprising a delay circuit for delaying the input voltage signal by a time corresponding to 1/4 phase of the input voltage in direct proportion to the first voltage and outputting the delayed signal to the first up / down counter. 4. The apparatus according to claim 3, further comprising a frequency detection circuit for sequentially detecting a frequency of an input voltage signal that is directly proportional to the voltage of the measured system, and providing information of the frequency to a delay circuit. Arithmetic unit. 5. The delay circuit according to claim 1, wherein the delay circuit is connected in series, and
An output signal of the first 1-bit A / D converter is input to the stage, a plurality of shift registers that operate using a clock φ as a reference signal, a decoder that decodes a signal from the frequency detection circuit, A plurality of AND gates for inputting each of the output signals to one input terminal and inputting the respective output signals of the plurality of shift registers to the other input terminal; and an output signal of each of the plurality of AND gates 5. The arithmetic unit according to claim 4, further comprising: an OR gate for inputting the following. 6. The arithmetic unit according to claim 3, wherein data output from said adder is cleared at predetermined time intervals. 7. The apparatus according to claim 1, wherein at least some of the functions of said first and second up / down counters, said adder / subtractor, said latch and said adder are executed by CPU software. The arithmetic unit according to claim 1, wherein: