RU2182724C2 - Fourier transform execution device - Google Patents

Abstract

FIELD: computer engineering; random signal analyses. SUBSTANCE: device has clock generator, synchronizing unit, auxiliary random signal generator, comparison unit, binary counter, read-only memory unit, and adder/subtractor accumulators. EFFECT: enhanced precision. 2 dwg

Description

 The invention relates to automation and computer technology and can be used in radio engineering and measuring systems to determine the Fourier transform coefficients in the harmonic analysis of deterministic and random signals in real time.

 A device is known for performing the Fourier transform, which contains an input information setting unit, a clock pulse generator, a pseudorandom number generator, a strobe pulse generation block, a memory block, two groups, each of which contains n encoders and n adders-subtracters, an intermediate coefficient register and a computational block, and the information input of the input information setting block is the information input of the device, the output of the clock generator is connected to the input of the pseudo-random generator number of outputs, the output of which is connected to the address input of the memory block and to the input of the strobe pulse generation block, the output of which is connected to the control input of the input information setting unit, the sign discharge output of which is connected to the first inputs of all encoders, the second inputs of which are connected to the corresponding outputs of the memory block, the outputs of the encoders of the first and second groups are connected to the control inputs of the respective adders-subtractors of the first and second groups, respectively, the information inputs of all adders-subtracters connected to the information output of the input information setting unit, the outputs of the adders-subtractors of the first and second groups are connected to the inputs of the first and second registers of intermediate coefficients, the outputs of which are connected to the inputs of the first and second computing blocks, respectively, the inputs and outputs of which are the outputs of the device (A. FROM. USSR 928363, MKI G 06 F 15/332. Bull. 18, 1982).

 The disadvantage of this device is the complexity of the technical implementation, due to the presence in its composition of two groups of encoders.

 The closest in technical essence to the present invention is a device for performing the Fourier transform containing an analog-to-digital converter, a clock pulse generator, a pseudo-random number generator, a counter, a read-only memory block, two groups of comparison blocks and accumulating adders-subtracters, the information input of the analog- the digital converter is the information input of the device, the output of the clock generator is connected to the clock input of the pseudo-random generator sat, to the counter counter input and to the synchronization input of the analog-to-digital converter, the output of the analog-to-digital converter is connected to the information inputs of the accumulating adders-subtractors of the first and second groups, the outputs of which are the information outputs of the device of the first and second groups, respectively, the information output of the counter is connected to the address input of the read-only memory block, the information outputs of the first and second groups of which are connected to the first inputs of the comparison blocks, respectively, of the first and second groups UPP, the outputs of which are connected to the inputs of the selection of the operating mode of accumulating adders-subtractors of the first and second groups, respectively, the output of the pseudo-random number generator is connected to the second inputs of the comparison blocks of the first and second groups (A.S. USSR 1177822, MKI G 06 F 15/332. Bull. 33, 1985).

 The disadvantage of this device is the technical complexity of its implementation. It contains two groups of digital comparison blocks, which should perform the comparison operation in the general case of multi-bit samples of a sequence of pseudorandom numbers and numerical codes corresponding to the values of the filtering functions at the outputs of the first and second groups of the read-only memory block.

 The aim of the invention is to simplify a device for performing Fourier transform.

(k = 1, 2, 3,..., K) коэффициентов преобразования Фурье, введен блок синхронизации, причем первый вход блока сравнения является входом устройства, а выход соединен с входами выбора режима работы накапливающих сумматоров-вычитателей первой и второй групп, выход генератора тактовых импульсов соединен с тактовым входом блока синхронизации, выход которого соединен со счетным входом двоичного счетчика и с тактовыми входами накапливающих сумматоров-вычитателей первой и второй групп, выходы первой и второй групп блока постоянной памяти соединены с информационными входами накапливающих сумматоров-вычитателей соответственно первой и второй групп, вход запуска блока синхронизации, вход сброса двоичного счетчика и входы сброса накапливающих сумматоров-вычитателей первой и второй групп объединены и подключены к входу "Пуск" устройства.The goal is achieved in that in a device for performing the Fourier transform containing a clock generator, an auxiliary random signal generator, the output of which is connected to the second input of the comparison unit, a binary counter, the output of which is connected to the address input of the read-only memory unit, the first and second groups of accumulating adders - subtractors whose outputs are outputs of the first and second groups, respectively, of estimates

(k = 1, 2, 3, ..., K) of the Fourier transform coefficients, a synchronization block is introduced, and the first input of the comparison block is the input of the device, and the output is connected to the inputs of the operation mode selection of accumulating adders-subtractors of the first and second groups, the output the clock generator is connected to the clock input of the synchronization unit, the output of which is connected to the counting input of the binary counter and to the clock inputs of the accumulating adders-subtractors of the first and second groups, the outputs of the first and second groups of the read-only memory are connected to nformatsionnymi inputs accumulator-subtractors, respectively, the first and second groups, start-sync block input, a reset input of the binary counter and reset inputs of the accumulators-subtractors of the first and second groups are coupled and connected to the input of "Start" of the device.

 Figure 1 presents the structural diagram of a device for performing Fourier transform; figure 2 is a structural diagram of a synchronization unit in one of the possible variants of its execution.

The device comprises a comparison unit 1, an auxiliary random signal generator 2, a clock pulse generator 3, a synchronization unit 4, a binary counter 5, a permanent memory unit 6, the first 7 ₁ and second 7 ₂ groups, each containing K accumulating adders-subtractors 8 ₁ -8 _K each.

 Block 4 synchronization contains a divider 9, RS-trigger 10, D-trigger 11 and the element And 12.

(k=1,2,3,..K) коэффициентов преобразования Фурье.The first input of the comparison unit 1 is the input of the device, and the second input is connected to the output of the auxiliary random signal generator 2, the output of the comparison unit 1 is connected to the inputs of the operation mode selection of accumulating adders-subtractors 8 ₁ -8 _{K of the} first 7 ₁ and second 7 ₂ groups, the output the clock generator 3 is connected to the clock input of the synchronization unit 4, the output of which is connected to the counting input of the binary counter 5 and to the clock inputs of the accumulating adders-subtractors 8 ₁ -8 _{K of the} first 7 ₁ and second 7 ₂ groups, the output of the binary counter 5 connected to the address input of the permanent memory block 6, the outputs of the first and second groups of which are connected to the information inputs of the accumulating adders-subtractors 8 ₁ -8 _K, respectively, of the first 7 ₁ and second 7 ₂ groups, the trigger input of the synchronization block 4, the binary counter 5 reset input, and the reset inputs of accumulating adders-subtractors 8 ₁ -8 _{K of the} first 7 ₁ and second 7 ₂ groups are combined and connected to the "Start" input of the device, the outputs of the accumulating adders-subtractors 8 ₁ -8 _{to the} first 7 ₁ and second 7 ₂ groups are outputs of the first and second groups respectively veno assessments

(k = 1,2,3, .. K) Fourier transform coefficients.

 In the synchronization block 4, the first input of the And element 12 and the clock input of the D-trigger 11 are combined and are the clock input of the block, the S-input of the RS-trigger 10 is the start input of the block, the R-input of the RS-trigger 10 and the R-input of the D-trigger 11 combined and connected to the output of the divider 9, the direct output of the RS-trigger 10 is connected to the D-input of the D-trigger 11, the direct output of which is connected to the second input of the element And 12, the output of which is connected to the input of the divider 9 and is the output of the unit.

The operation of the device is based on the sign method of converting the signal x (t) under study using an auxiliary random signal ξ (t), which in the general case has the following form
Z (t) = Sgn {x (t) -ξ (t)}, (1)
where Sgn {...} is the operator of the sign function.

The auxiliary signal ξ (t) is independent of the signal under study x (t). The instantaneous values of the signal ξ (t) are evenly distributed within the interval from -A to + A. Moreover, the value of A must satisfy the condition
| x (t) | _max ≤A, (2)
where | x (t) | _max - the maximum possible absolute value that the signal x (t) can take.

The theoretical justification of the invention is based on the well-known relation (see Mirsky G. Ya. Characteristics of stochastic interconnection and their measurements - M .: Energoizdat, 1982. - P. 194, relation (4.79))
M [x (t) = AM [z (t)], (3)
where M [...] is the mathematical expectation operator.

коэффициентов дискретного преобразования Фурье можно вычислять по формулам

k = 1, 2, 3,..., K; (4)

k = 1, 2, 3,..., K; (5)
где z(nT₀) - дискретные значения знакового сигнала z(t); N - общее число выборок за интервал времени вычисления оценок; Т₀ - период следования тактовых импульсов (импульсов опроса);

дискретные значения фильтрующих функций.Given the relation (3) estimates

discrete Fourier transform coefficients can be calculated by the formulas

k = 1, 2, 3, ..., K; (4)

k = 1, 2, 3, ..., K; (5)
where z (nT ₀ ) are the discrete values of the sign signal z (t); N is the total number of samples over the time interval for calculating estimates; T ₀ - the repetition period of clock pulses (polling pulses);

discrete values of filtering functions.

k = 1, 2, 3,..., K; (6)

k = 1, 2, 3,..., K; (7)
Принимая во внимание соотношение (3), а также то, что операция нахождения математического ожидания и операции суммирования являются линейными операциями, будем иметь

k=1,2,3,..., K; (8)

k=1,2,3,..., K. (9)
Из (8) и (9) нетрудно видеть, что оценки

коэффициентов преобразования Фурье являются несмещенными.The expected value of estimates (4) and (5) will be equal to

k = 1, 2, 3, ..., K; (6)

k = 1, 2, 3, ..., K; (7)
Taking into account relation (3), as well as the fact that the operation of finding the mathematical expectation and the operation of summation are linear operations, we will have

k = 1,2,3, ..., K; (8)

k = 1,2,3, ..., K. (9)
From (8) and (9) it is easy to see that the estimates

Fourier transform coefficients are unbiased.

. Пусть {t₁, t₂, ..., t_Q-1} моменты времени, в которые знаковый сигнал z(t) меняет свой знак на противоположенный на интервале времени t₀≤t≤t_Q.Denote by t ₀ and t _{Q the} moments of time corresponding to the beginning and end of the process of computing estimates

. Let {t ₁ , t ₂ , ..., t _Q-1 } be the moments of time at which the sign signal z (t) changes its sign to the opposite in the time interval t ₀ ≤t≤t _Q.

будет равно N = N_Q-N₀.With a discrete representation of the sign signal z (t), time moments belonging to the time interval t ₀ ≤t≤t _Q can be written as follows
t _q = N _q T ₀ , g = 0, 1, 2, 3, ..., Q. (10)
Moreover, the total number of samples of the sign signal z (t) in the time interval t ₀ ≤t≤t _Q estimates

will be equal to N = N _Q -N ₀ .

k = 1, 2, 3,..., K; (11)

k = 1, 2, 3,..., K. (12)
Из полученных выражений нетрудно видеть, что вся процедура вычисления оценок

коэффициентов преобразования Фурье сводится к выполнению простейших арифметических операций суммирования и вычитания значений фильтрующих функций

При этом необходимость выполнения операции суммирования или вычитания определяется текущим знаком сигнала z(t).Due to the fact that the sign signal z (t) can take values equal to only “-1” or “+1”, and also taking into account expression (10), estimates (4) and (5) take the form

k = 1, 2, 3, ..., K; (eleven)

k = 1, 2, 3, ..., K. (12)
From the obtained expressions it is easy to see that the whole procedure for calculating the estimates

Fourier transform coefficients is reduced to performing the simplest arithmetic operations of summing and subtracting the values of filtering functions

In this case, the need to perform the operation of addition or subtraction is determined by the current sign of the signal z (t).

 Expressions (11) and (12) directly form the basis of the device.

 The device operates as follows.

 The studied signal x (t) is fed to the input of the device, that is, to the first input of the comparison unit 1, the second input of which receives the signal ξ (t) from the output of the auxiliary random signal generator 2.

 As an auxiliary signal ξ (t), it is allowed to use a linearly varying periodic signal (see Mirsky G.Ya. Characteristics of stochastic interconnection and their measurements - M .: Energoizdat, 1982. P. 190). In particular, you can use a triangular waveform (for a triangular wave generator circuit, see the book: The use of precision analog microcircuits / A.G. Aleksenko, E.A. Colombet, G.I. Starodub. -M .: Radio and communications, 1985. - S. 165-168, Fig. 4.11-4.13).

 Block 1 comparison compares the signals x (t) and ξ (t). As a result of this operation, the sign signal z (t) will be present at the output of the comparison unit 1.

При технической реализации устройства в качестве блока 1 сравнения можно использовать интегральный компаратор (см. Нефедов А.В. Интегральные микросхемы и их зарубежные аналоги: Справочник. Т.5. - М.: КУбК-а, 1997. - С. 113-119). В этом случае уровень логической единицы на выходе блока 1 сравнения будет соответствовать значению "+1" знакового сигнала z(t), а уровень логического нуля на выходе этого блока будет соответствовать значению "-1" знакового сигнала z(t).Since, in practice, comparison schemes always record zero values of sign signals with equal probability either as “-1” or as “+1”, in measurements usually use a sign function that takes the values “-1” and “+1” (see Mirsky G.Ya. Characteristics of the stochastic relationship and their measurement - M .: Energoizdat, 1982. P.179). In accordance with this, the signal z (t) can be represented as follows

In the technical implementation of the device, an integral comparator can be used as a comparison unit (see Nefedov A.V. Integrated circuits and their foreign analogues: Reference. V. 5. - M .: KUBK-a, 1997. - P. 113-119 ) In this case, the level of the logical unit at the output of the comparison unit 1 will correspond to the value "+1" of the sign signal z (t), and the level of the logical zero at the output of this block will correspond to the value "-1" of the sign signal z (t).

 The start of operation of the device is carried out by the signal "Start", which is a short pulse.

The Start signal is fed to the start input of the synchronization unit 4, to the reset input of the binary counter 5 and to the reset inputs of the accumulating adders-subtractors 8 ₁ -8 _{K of the} first 7 ₁ and second 7 ₂ groups.

As a result of the “Start” signal, the binary counter 5 and the accumulating adders-subtractors 8 ₁ -8 _{K of the} first 7 ₁ and second 7 ₂ groups are reset.

According to the “Start” signal, clock pulses appear at the output of the synchronization unit 4, which are fed to the counting input of the binary counter 5 and to the clock inputs of the accumulating adders-subtractors 8 ₁ -8 _{K of the} first 7 ₁ and second 7 ₂ groups.

 Consider in more detail the operation of block 4 synchronization and one of the possible options for its execution (see figure 2).

коэффициентов преобразования Фурье и соответствует моменту времени t₀, который условно можно считать равным нулю. D-триггер 11 используется для синхронизации начала процесса вычисления с началом периода следования тактовых импульсов. (В качестве RS-триггера 10, D-триггера 11 и элемента И 12 могут быть использованы соответственно элементы К555ТМ2 и К555ЛИ1. См. Нефедов А.В. Интегральные микросхемы и их зарубежные аналоги: Справочник. Т.5. - М.: КУбК-а, 1997. - С.255, 281. В качестве делителя 9 можно использовать, например, хорошо известную интегральную микросхему программируемого таймера К580ВИ53 или его аналоги. См. Алексенко А.Г., Галицын А.А., Иванников А.Д. Проектирование радиоэлектронной аппаратуры на микропроцессорах: Программирование, типовые решения, методы отладки. - М.: Радио и связь, 1984. С. 65-72. )
Тактовые импульсы с выхода блока 4 синхронизации поступают на счетный вход двоичного счетчика 5, выход которого соединен с адресным входом блока 6 постоянной памяти. (В качестве двоичного счетчика можно использовать, например, счетчик К555ИЕ10. См. Нефедов А.В. Интегральные микросхемы и их зарубежные аналоги: Справочник. Т.5. - М.: КУбК-а, 1997. - с. 166. Блок постоянной памяти может быть построен, например, на основе микросхем серии К573. См. Полупроводниковые БИС запоминающих устройств: Справочник / В.В. Баранов, Н. В. Бекин, А.Ю. Гордонов и др.; Под ред. А.Ю. Гордонова и Ю.Н. Дьякова. - М.: Радио и связь, 1987. - С. 305-312.)
Блок 6 постоянной памяти имеет две группы выходов по К выходов в каждой. На выходах первой группы блока 6 постоянной памяти формируются числовые последовательности, соответствующие значениям фильтрующих функций

(где k = 1, 2, 3,..., К) для первой 7₁ группы накапливающих сумматоров-вычитателей 8₁-8_K. На выходах второй группы блока 6 постоянной памяти формируются числовые последовательности, соответствующие значениям фильтрующих функций

(где k = 1, 2, 3,..., К) для второй 7₂ группы накапливающих сумматоров-вычитателей 8₁-8_K. Значения фильтрующих функций с выходов первой и второй групп блока 6 постоянной памяти поступают на информационные входы накапливающих сумматоров-вычитателей 8₁-8_K соответственно первой 7₁ и второй 7₂ групп, на входы выбора режима работы которых поступает сигнал z(t) с выхода блока 1 сравнения. Если сигнал z(t) имеет уровень логической единицы, то выполняется операция суммирования поступающих значений фильтрующих функций с содержимым накапливающих сумматоров-вычитателей 8₁-8_K первой 7₁ и второй 7₁ групп. Если же сигнал z(t) имеет уровень логического нуля, то выполняется операция вычитания поступающих значений фильтрующих функций из содержимого накапливающих сумматоров-вычитателей 8₁-8_K первой 7₁ и второй 7₂ групп. Синхронизация выполнения операций накапливающими сумматорами-вычитателями 8₁-8_K первой 7₁ и второй 7₂ групп осуществляется с помощью тактовых импульсов, которые поступают на их тактовые входы с выхода блока 4 синхронизации. (Накапливающие сумматоры-вычитатели могут быть реализованы, например, на основе микросхем К555ИМ7 или с использованием арифметическо-логических схем, например, К584ВМ1. См. Цифровые интегральные микросхемы: Справочник / М.И. Богданович, И.Н. Грель, С.А. Дубина и др. - 2-е изд., перераб. и доп. -Мн.: Беларусь, Полымя. 1996. -С. 249, 508.)
После прохождения N тактовых импульсов на выход блока 4 синхронизации, которые одновременно поступают и на вход делителя 9 (см. фиг.2), на выходе делителя 9 вырабатывается короткий импульс, который поступает на R-входы RS-триггера 10 и D-триггера 11 и возвращает эти триггеры в исходное нулевое состояние, то есть на их прямых выходах устанавливаются уровни логического нуля. Уровень логического нуля с прямого выхода D-триггера 11 поступает на второй вход элемента И 12 и запрещает прохождение на выход этого элемента тактовых импульсов с его первого входа. Соответственно прекращается прохождение тактовых импульсов и на выход блока 4 синхронизации. На этом процесс вычисления оценок

коэффициентов преобразования Фурье завершается. К этому моменту времени, который соответствует моменту времени t_Q, в накапливающих сумматорах-вычитателях 8₁-8_K первой 7₁ и второй 7₂ групп будут накоплены соответственно следующие результаты

k = 1, 2, 3,..., K; (14)

k = 1, 2, 3,..., K. (15)
Полученные результаты S_a(k) и S_b(k) с точностью до постоянного множителя

совпадают с оценками

коэффициентов преобразования Фурье, определяемых выражениями (11) и (12). Постоянный коэффициент

может быть учтен путем простого масштабирования, что не представляет особого труда.In the initial state, at the direct outputs of the RS-flip-flop 10 and the D-flip-flop 11 there are logical zero levels. The logic zero level from the direct output of the D-flip-flop 11 goes to the second input of the And 12 element and prevents the clock pulses from passing to the output of this element from its first input, which is the clock input of the synchronization unit 4 and is connected to the output of the clock generator 3. The “Start” signal is input to the start input of the synchronization unit 4 and then goes to the S-input of the RS-flip-flop 10, at the direct output of which the logical unit level is set. The level of a logical unit from the direct output of the RS-trigger 10 is supplied to the D-input of the D-trigger 11, to the clock input of which clock pulses are received. When the next clock pulse arrives at its leading edge at the direct output of the D-flip-flop 11, the level of the logical unit is set, which goes to the second input of the And 12 element and allows the passage of clock pulses to the output of this element from its first input. The clock pulses from the output of the element And 12 go to the output of the synchronization unit 4, and also go to the input of the divider 9. The time instant of the appearance of the clock pulses at the output of the synchronization unit 4 determines the beginning of the evaluation calculation

of the Fourier transform coefficients and corresponds to the time t ₀ , which can conditionally be considered equal to zero. D-flip-flop 11 is used to synchronize the beginning of the calculation process with the beginning of the repetition period of clock pulses. (As an RS-trigger 10, a D-trigger 11 and an And 12 element, K555TM2 and K555LI1 elements can be used, respectively. See Nefedov A.V. Integrated circuits and their foreign analogues: Reference book. T.5. - M .: KUBK -a, 1997. - P.255, 281. For example, a well-known integrated timer chip K580VI53 or its analogs can be used as a divider 9. See Aleksenko AG, Galitsyn AA, Ivannikov A.D. Design of electronic equipment on microprocessors: Programming, standard solutions, debugging methods. - M.: Radio and communications, 1984. S. 65-72.)
Clock pulses from the output of the synchronization unit 4 are fed to the counting input of the binary counter 5, the output of which is connected to the address input of the permanent memory unit 6. (For example, the K555IE10 counter can be used as a binary counter. See Nefedov A.V. Integrated circuits and their foreign counterparts: Reference. V.5. - M .: KUBK-a, 1997. - p. 166. Constant block memory can be built, for example, on the basis of K573 series microcircuits. See Semiconductor LSI memory devices: Reference / VV Baranov, NV Bekin, A.Yu. Gordonov and others; Edited by A.Yu. Gordonova and Yu.N. Dyakova. - M.: Radio and Communications, 1987. - S. 305-312.)
Block 6 of permanent memory has two groups of outputs for K outputs in each. At the outputs of the first group of block 6 of constant memory, numerical sequences are formed corresponding to the values of filtering functions

(where k = 1, 2, 3, ..., K) for the first 7 ₁ group of accumulating adders-subtractors 8 ₁ -8 _K. At the outputs of the second group of block 6 of constant memory, numerical sequences are formed corresponding to the values of filtering functions

(where k = 1, 2, 3, ..., K) for the second 7 ₂ group of accumulating adders-subtractors 8 ₁ -8 _K. The values of the filtering functions from the outputs of the first and second groups of the unit 6 of constant memory are supplied to the information inputs of accumulating adders-subtractors 8 ₁ -8 _K, respectively, of the first 7 ₁ and second 7 ₂ groups, to the inputs of the choice of the operating mode of which a signal z (t) is output block 1 comparison. If the signal z (t) has a logical unit level, then the operation of summing the incoming values of the filtering functions with the contents of the accumulating adders-subtractors 8 ₁ -8 _{K of the} first 7 ₁ and second 7 ₁ groups is performed. If the signal z (t) has a logic zero level, then the operation is performed to subtract the incoming values of the filtering functions from the contents of the accumulating adders-subtractors 8 ₁ -8 _{K of the} first 7 ₁ and second 7 ₂ groups. The synchronization of operations by accumulating adders-subtractors 8 ₁ -8 _{K of the} first 7 ₁ and second 7 ₂ groups is carried out using clock pulses that are received at their clock inputs from the output of synchronization unit 4. (Accumulating adders-subtractors can be implemented, for example, on the basis of K555IM7 microcircuits or using arithmetic logic circuits, for example, K584VM1. See Digital Integrated Circuits: Reference Book / M.I. Bogdanovich, I.N. Grel, S.A. Dubina et al. - 2nd ed., Revised and enlarged. - Mn .: Belarus, Polymya. 1996. - S. 249, 508.)
After passing N clock pulses to the output of the synchronization unit 4, which are simultaneously input to the input of the divider 9 (see Fig. 2), a short pulse is generated at the output of the divider 9, which is fed to the R-inputs of the RS-trigger 10 and D-trigger 11 and returns these triggers to the initial zero state, that is, at their direct outputs, logical zero levels are set. The logic zero level from the direct output of the D-flip-flop 11 goes to the second input of the And 12 element and prohibits the passage of the output of this element of clock pulses from its first input. Accordingly, the passage of clock pulses to the output of the synchronization unit 4 is stopped. This is the process of calculating grades

Fourier transform coefficients is completed. To this point in time, which corresponds to time t _Q , in the accumulating subtractors-subtractors 8 ₁ -8 _{K of the} first 7 ₁ and second 7 ₂ groups, the following results will be accumulated, respectively

k = 1, 2, 3, ..., K; (14)

k = 1, 2, 3, ..., K. (15)
The obtained results S _a (k) and S _b (k) up to a constant factor

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Fourier transform coefficients defined by expressions (11) and (12). Constant coefficient

can be taken into account by simple scaling, which is not difficult.

коэффициентов преобразования Фурье являются несмещенными.From the above description it is seen that in comparison with the prototype device, the proposed device is technically simpler. It contains only one unit of comparison. Moreover, the resulting estimates

Fourier transform coefficients are unbiased.

 Technically, the proposed device is implemented on standard elements that are widely known and used in modern technology. Moreover, at the current level of technology for the development and production of integrated circuits in the future, such a device or its individual blocks can be implemented in the form of integrated circuits.

Claims (1)

A device for performing a Fourier transform containing a clock generator, an auxiliary random signal generator, the output of which is connected to the second input of the comparison unit, a binary counter, the output of which is connected to the address input of the read-only memory, the first and second groups of accumulating adders-subtracters, the outputs of which are outputs of the first and second groups, respectively, estimates

(k = 1,2,3,.. K) of the Fourier transform coefficients, characterized in that a synchronization block is introduced into it, the first input of the comparison block being the input of the device, and the output connected to the inputs of the selection of the operating mode of accumulating adders-subtractors of the first and the second group, the output of the clock generator is connected to the clock input of the synchronization block, the output of which is connected to the counting input of the binary counter and to the clock inputs of the accumulating adders-subtractors of the first and second groups, the outputs of the first and second groups of the post block memory are connected to the information inputs of the accumulating adders-subtractors of the first and second groups, respectively, the trigger input of the synchronization unit, the binary counter reset input and the reset inputs of the accumulating adders-subtractors of the first and second groups are combined and connected to the "Start" input of the device.

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