JPS59200505A - Digital processing type envelope detector - Google Patents

Abstract

PURPOSE:To eliminate phase distortion and to improve time responsiveness by using a DLPF which has linear phase characteristics and is not cyclic. CONSTITUTION:A digital signal from an AD converter 1 is supplied to the DLP19 through an absolute value calculator 2. This DLPF19 consists of the delay circuit composed of (m) sets of delay devices 20, adder and subtracter 21 feedback circuit including a delay device 26, and coefficient device 17. The adder and subtracter 21 adds the output of the absolute value calculator 2 and the output of the delay device 26 together and subtracts the output of the delay device 20 from the sum. The output of the adder and subtracter 21 is divided by (m) through the coefficient device 17. The phase characteristics of the DLPF19 formed as mentioned above are linear, so phase distortion is eliminated. Further, the DLPF19 is not cyclic, so the time responsiveness is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a device for extracting an envelope component signal of a continuous analog signal such as voice by digital processing.

In principle, the method shown in FIG. 1 is used to extract the envelope component signal from the analog signal.

FIG. 1(a) shows the input analog signal.

The first step is to perform full-wave rectification of (a) to obtain the signal shown in b).

The second step is to filter (b) to remove its high frequency components and obtain c).

FIG. 1(c) is the envelope component signal. At this time, if the cutoff frequency of the low-pass filter is lowered (c')
The envelope component signal shown in is obtained.

(e') is a signal obtained by smoothing (c).

Conventionally, a device for extracting this type of envelope component signal had a configuration shown in FIG.

In Fig. 2, 1 is an analog-to-digital converter (hereinafter referred to as AD converter), 2 is an absolute value calculator that controls the first step, and 3 is a digital low-pass filter (
(hereinafter referred to as DLPF) and executes the second step.

Note that the double line in the figure corresponds to n (natural number) bits.
This is a summary of the wiring in the book.

Further, the absolute value calculator 2 outputs an n-bit digital value corresponding to the sample value of the analog/4G signal in offset binary code. Here, the offset binary code is a code commonly used in AD converters and DA converters, and the code for the maximum positive analog input is "0...
...0", the code for the maximum negative input is "1...
...I11 zero input is assigned "01, song, 1', and the bit array is "MSB,"...
, LSB'.

The absolute value calculator 2 calculates and outputs the exclusive OR (hereinafter referred to as EX/OR) of the signal with the sign bit inverted and the non-MSB bit of the output value of the AD converter 1 on a bit-by-bit basis.

5 is an MSH inverter, and 6 is an EX/OR gate that calculates EX/OR between the output of the inverter 5 and the non-MSB bit.

The DLPF 3 performs a low-pass filter function on the signal at the input terminal 7 and outputs a filtered output to the output terminal 8 . A subtracter 9 outputs the difference between the input value at the input terminal 10 and the input value at the input terminal 11 to the output terminal 12.

13 is an adder, which outputs the sum of the input values of the input terminal 14 and 15 to the output terminal 16. 17 is a coefficient unit consisting of a multiplier, etc., which combines the constant 1/m and the input value to the coefficient unit 17. Output the product.

Reference numeral 18 denotes a delay device that holds and outputs a large output value for one sample period T. The output of AD converter 1 is converted to absolute value calculator 2.
In addition, by applying the output to the input terminal 7 of the DLPF 3 and to the clock pulse input terminal of the AD converter 1 or the delay device 18, which is the output of the clock generator 4 that generates a pulse at a fixed period T, The output shown in FIG. 3 is obtained.

FIG. 3(a) shows sample values in the AD converter 1,
The value of the digital quantity appearing at the output terminal 19 is (b)
appears at the output terminal of the absolute value calculator 2 as the absolute value of the sample value, and (c) or (C') appears at the output terminal 8 by low-pass filtering.

Note that the dotted lines in FIG. 3 correspond to the analog values shown in FIG.

The transfer function Ho(Z-') of DLPF3 is expressed as,
Its frequency characteristics can be obtained by setting z=e-.

・・・・・・・・・・・・(2) Ha (e=”) amplitude characteristic Go(a+), phase characteristic φ
. (→ can be obtained separately from equation (2). Here, ω is the normalized angular frequency, and ω=
2πTf, where f is the frequency.As the amplitude characteristic of equation (3) clearly shows, DLPF3 has a low-pass characteristic, but as the phase characteristic of equation (3) shows at the same time, its linearity is poor, and Impulse inputs such as click noises remain in the DLPFa by circulating for a long time through a circulation path consisting of the delay unit 18, the coefficient unit 17, and the subtracter 9, and therefore have the disadvantage that they are easily affected by the adverse effects of such signals. As mentioned above, the drawbacks of conventional envelope detection circuits are summarized as follows: First, the envelope component signal has a non-linear phase characteristic with respect to the original signal, causing phase distortion.

Second, since a cyclic filter is used, it has serious drawbacks such as poor time response and susceptibility to impulsive noise. In order to eliminate these drawbacks, the present invention uses a low-pass filter. In order to avoid phase distortion, FIG. 4 shows an embodiment of the present invention, and the AD converter 1 and absolute value calculator 2 are the same as those in FIG. The structure is different from DLPF3 in Figure 2.

In D L P F 19, 20 is a delay device;
Its function is the same as the delay device 18 of the DLPF3, and has an input end, an output end, and a clock input end.A predetermined number (m) of delay devices 20 are connected in series to form an m-stage delay circuit. , the signal input to the first-stage delay device 20 appears at the output terminal of the final-stage delay device 20 after mT waiting time, where T is the delay time of one delay device.

21 is an adder/subtractor, which has input terminals shown as 9.22.23.24, and converts the value inputted to input terminal 22 into 81 and input terminal 2.
If the value input to the input terminal 3 is 82 and the value input to the input terminal 24 is 83, a signal of 81+82-Ss is output to the output terminal 25.

Reference numeral 17 denotes a coefficient unit composed of a multiplier or the like, which is the same as that shown in FIG.

The transfer function H(Z) of D L P F 19 is expressed by the following equation.

That is, the output of the absolute value calculator 2 is input to the input terminal 22 every clock. A summator composed of an adder/subtracter 21 and a delay device 26 acts on this, and the sum from the past to the present time is obtained. However, m delay devices 20
When t='mT, the output signal S1 of the absolute value calculator 2 corresponding to t=0 appears at the output terminal of the final stage delay device 20, and the adder/subtractor 21 and the delay device 26 Sl is subtracted from the summator value consisting of . This indicates that the sum of the outputs of the absolute value calculator 2 existing at a time difference corresponding to the delay amount of the output of the absolute value calculator 2 applied to the input terminals 24 and 22 becomes the output of the adder/subtractor 21. It is.

Therefore, 0H(Z
) frequency characteristic is Z=e (ω is normalized angular frequency)
Therefore, the following is required.

It is known that the amplitude characteristic G(ω) and the phase characteristic φ←) are each constant; ■ gives the group delay characteristic, and the fact that it is a constant means that there is no phase distortion. means.

Also, as shown in FIG. 4, although it appears at first glance that the adder/subtractor 21 and the delay device 26 constitute a cyclic filter, the past D exceeding the period mT is caused by the action of the m delay devices 200.
All input values of L P F 19 are canceled and DLP
F19 acts on sample values only during the mT period, and is not affected by impulsive noise or the like at all after the mT waiting time.

As an embodiment of the present invention, an AD converter 1, an absolute value calculator 2,
Rather than realizing all of the coefficient unit 17, delay unit 20, 26, and adder/subtractor 21 as individual circuits, all or part of their circuit functions can be realized using a microprocessor, etc., with certain restrictions, and the same processing method can be used to perform analog processing. It is also possible to sample the signal and calculate the envelope component signal as a digital quantity from the sample value series.

For example, the absolute value calculator 2 can be executed by identifying the MSB of the output of the AD converter 1, and if the MSB is 0, EX/ORing the non-MSB bits with 1 bit by bit, This can be realized by sequentially reading and writing to a random access memory so as to form a cyclic group modulo m using an address space of This can be done using a multiplier.

As described above, an envelope detection device having a filter function in which all acyclic weights are equal has the advantage of no phase distortion and excellent transient response characteristics. Furthermore, the amount of processing in the conventional DLPF 3 is exactly equal to the amount of processing in the present invention, which is one addition, one subtraction, and one multiplication in the period T, but the multiplication in the present invention is particularly the case of 2 where m = 2. When setting to a power, it can be executed only by bit shifting, which has the advantage of making processing easier 0

[Brief explanation of drawings]

Figure 1 shows the principle of envelope detection using analog processing. (a) is the original signal, (b) is the full-wave rectified signal, (
C) and (C) show the envelope component signals in (a). Figure 2 shows an example of the configuration of a conventional envelope detection device using digital processing, and Figure 3 shows the principle of envelope detection using digital processing. 3(a) shows the sample value series,
(b) is a sample value 1...Analog-digital converter (AD & converter), 2...
・Absolute value calculator, 3.19・・・・・・・・・Digital
/l/ C2-lotus filter (DLPF), 4.
Song clock generator, 5... River... Inverter,
6...EX/OR gate, 7...
...Input end of digital low-pass filter 3, 8.
・・・・・・Output end of digital low-pass filter 3, 9・・・・・・・・・Subtractor, 10.11・°°°
°...Subtractor 90 input end, 12...
Output end of subtracter 9, 13...Adder, 1
4. Input terminal of 15 songs/adder 13, 16...
... Output terminal of adder 13, 17. Curvature coefficient gain, 18.
・・・・・・Delay device, 2o・・・Song delay device, 2
1. Song °°° adder/subtractor, 22-24...
・Input terminal of adder/subtractor 21, 25...Output terminal of adder/subtractor 21, 26...Song...Delay device agent Patent attorney Takashi Honma Figure 1

Claims (1)

[Claims] An analog-to-digital converter that converts the amplitude value obtained by sampling an analog signal at regular intervals into a digital quantity, a means for determining the absolute value of the amplitude of the original signal from the output of the analog-to-digital converter, and an absolute value. The adding/subtracting means is provided with a delay circuit including a plurality of delay devices for delaying the output signal of the means for determining the absolute value, and a feedback circuit including the delay device between the input and output terminals. Addition/subtraction means for adding signals from the value determining means and subtracting signals from the delay circuit; and a coefficient multiplier for multiplying the output signal from the addition/subtraction means by the reciprocal of the number of delay devices constituting the delay circuit. A digital processing type envelope detection circuit comprising: