JP2003284382A - Pwm control apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a PWM control apparatus which reduces a burden on the computbility of an arithmetic circuit and is versatile to the wide application of an inverter. <P>SOLUTION: A PWM control apparatus includes a plurality of registers at a first stage for holding a plurality of set data outputted from an arithmetic circuit, a counter circuit of peaks and bottoms of carriers for counting peaks and bottoms of a carrier generation circuit, a plurality of registers at a second stage for delivering counter circuit signals when a value which is set on the counter circuit of peaks and bottoms of carriers coincides with the counter value of peaks and bottoms of carriers, and holding them with output signals of the counter circuit of peaks and bottoms of carriers, a comparator of comparing the counter value of output on the carrier generation circuit with the register outputs at the second stage, and a current detector. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PWM controller used in a voltage type PWM inverter for varying the speed of an AC motor or the like, in particular, an inverter using a high speed switching element such as an IGBT.

[0002]

2. Description of the Related Art FIG. 3 is a block diagram showing a configuration of a conventional PWM control device. The carrier frequency setting register 3 is a register in which the frequency of the PWM signal is set, and the carrier frequency data output from the arithmetic circuit 1 is connected to the carrier frequency setting register 3 via the data bus 1a and output from the arithmetic circuit 1. It is written by the written write signal 1c. U-phase PWM setting register 4 is a U-phase PW
A register for holding M signal generation data, which is an arithmetic circuit 1
The U-phase PWM signal generation data output from the U-phase PWM signal is connected to the U-phase PWM setting register 4 via the data bus 1a and written by the write signal 1d output from the arithmetic circuit 1. V-phase PWM setting register 5 is V-phase PW
A register for holding M signal generation data, which is an arithmetic circuit 1
The V-phase PWM signal generation data output from V is connected to the V-phase PWM setting register 5 via the data bus 1a and written by the write signal 1e output from the arithmetic circuit 1. The W-phase PWM setting register 6 is a W-phase PW
A register for holding M signal generation data, which is an arithmetic circuit 1
The W-phase PWM signal generating data output from the output terminal is connected to the W-phase PWM setting register 6 via the data bus 1a and is written by the write signal 1f output from the arithmetic circuit 1.

The carrier generation circuit 15 is composed of an up / down counter, inputs the output data 3a of the carrier frequency setting register 3 and the count clock 16, and when the counter value 15c matches the carrier frequency register 3a, the overflow signal 15a and the counter When the value 15c matches 0, the underflow signal 15b is output. P
The WM signal generation circuit 19 is a U-phase PWM signal generation circuit 19a.
And a V-phase PWM signal generation circuit 19c and a W-phase PWM signal generation circuit 19e. The U-phase comparator compares the counter value 15c with the U-phase PWM setting register output 4a, and outputs the U-phase PWM.
The signal 19b is output. The U-phase PWM signal 19b is connected to the gate driver circuit 20, generates U-phase and / U-phase signals, and is applied to the gate of an IGBT (not shown). The V-phase comparator has a counter value of 15c and V-phase PWM setting register output 5
a is compared, and the V-phase PWM signal 19d is output. V phase P
The WM signal 19d is connected to the gate driver circuit 20 and V
Phase and / V phase signals are generated and applied to the gate of the IGBT (not shown). The W-phase comparator has a counter value of 15c and W-phase P
WM setting register output 6a is compared, W-phase PWM signal 1
9e is output. The W-phase PWM signal 19e is connected to the gate driver circuit 20, generates W-phase and / W-phase signals, and is applied to the gate of an IGBT (not shown). The gate driver outputs 20a, 20b, 20c are connected to the electric motor 22.

The AD converters 13 and 14 are connected to the outputs of the current transformers 21a and 21b connected to the two phases of the gate driver outputs, for example, 20a and 20b. The U-phase AD data register 7 is a U-phase A output from the arithmetic circuit 1.
It is connected to the D data read signal 1g and the data bus 1a, and is connected to the AD converter output 13a. V phase AD
The data register 8 is connected to the V-phase AD data read signal 1h output from the arithmetic circuit 1 and the data bus 1a and connected to the AD converter output 14a. In addition,
The PWM setting register data to be written in each PWM setting register 4, 5, 6 by the arithmetic circuit 1 is the PW to be generated.
This is data for setting the H (high level) period and the L (low level) period of the PWM signal, which is determined by the combination of the M waveforms. Further, the carrier generation circuit 15 is commonly used for three phases.

Next, the operation of the above conventional PWM generator will be described. To generate the PWM waveform, first, the carrier generation circuit 15 is caused to count by the count clock 16. Then, the rewritable U by the arithmetic circuit 1
U-phase PWM held in the phase PWM setting register 4
When the contents of the counter value 15c match the setting register output 4a, the U-phase PWM signal 19b is output from the comparator. The PWM signals 19d and 19f similarly generated are connected to the gate driver circuit 20 to drive the induction motor 22. Further, when the arithmetic circuit 1 writes the data of the PWM signal generation period into the carrier frequency setting register 3, the PWM comparison period is changed. The larger the value, the longer the cycle of pulse generation, and the smaller the value, the shorter the cycle of pulse generation.

FIG. 4 shows a signal waveform diagram in the case of the triangular wave modulation method. In FIG. 4, the overflow signal 15a is set to L (low level) when the output data 3a of the carrier frequency setting register matches the counter value 15c, and the underflow signal 15b is set to the counter value 15c.
When c matches 0, it is set to L (low level).
Moreover, writing to the PWM setting registers 4, 5, 6 and the carrier frequency setting register 3 for each phase is always performed before the peaks or valleys of the carrier. Further, the AD conversion start signal is output from the arithmetic circuit in a constant cycle, and the output timing is immediately after the peak or valley of the carrier.
When the AD conversion process and the PWM calculation process are completed, the monitoring process is performed to count the occurrences of the overflow signal 15a and the underflow signal 15b. Overflow signal 15a in the monitoring process
When the number of occurrences of the underflow signal 15b reaches the set count, the AD conversion start signal is generated. The carrier frequency setting is changed, for example, by setting an integral multiple of the upper limit frequency setting value of the carrier. Therefore, even if the carrier frequency is changed, the upper limit for counting the number of overflow signals 15a and underflow signals 15b can be changed. , AD conversion start signal is kept in a constant cycle.

[0007]

In the conventional PWM generator described above, reading of the AD data registers 7 and 8 for each phase, the carrier frequency setting register 3 and the PWM setting register 4 are performed.
6 and the conversion start signal 1i for the AD converter, the arithmetic circuit 1 always outputs the overflow signal 15i.
a Underflow signal 15b is monitored, an AD conversion start signal is generated, the AD data registers 7 and 8 of each phase are read out, and PWM calculation processing is performed using the current data 7a and 8a. Data was written in 5, and 6. Therefore, the PWM signals 19b and 19 of each phase are detected by comparing and detecting the contents of the counter value 15c of the carrier generation circuit 15 and the contents of the PWM setting registers 4 to 6.
d and 19f are repeatedly output, but when the carrier cycle becomes short, PW is performed to generate the PWM signal.
Since the overflow signal 15a or the underflow signal 15b is generated during the M operation processing time, the above 1
Since 5a and 15b cannot be counted, there is a problem that the processing capacity of the arithmetic circuit 1 is heavily burdened.
That is, in order to control the PWM output with high accuracy, an AD conversion start signal is generated at a constant cycle, the AD conversion data register is read, and the write data to the PWM setting registers 4 to 6 and the carrier frequency setting register 3 are calculated at high speed. , Need to write this result.

The carrier synchronous output type PWM control device lowers the carrier frequency at low speed and uses three-phase modulation for the modulation method, and raises the carrier frequency at high speed (3/2 times) for the two-phase modulation method to control the carrier frequency. It is variable. Since general control keeps the sampling period constant,
Even if the carrier cycle is changed, the current detection and voltage command update cycle is constant. In FIG. 4, the AD conversion start signal, the carrier frequency, and the PWM waveform when the induction motor 22 is operated from the low speed operation to the high speed operation are the U phase, and the PW
Although it is shown only when the M setting register 4 is written, the PWM setting data 4a, 5 for three phases is actually shown.
a and 6a and the carrier comparison value are calculated during the PWM calculation process and written in the registers 3, 4, and 5. Such a waveform is output for many cycles. Overflow signal 15a and underflow signal 15b every 1 cycle
Is frequently counted by the arithmetic circuit 1, and when the desired count value is reached, an AD conversion start signal is generated to read the AD data values of the respective phases of the AD converters 13 and 14, and the registers 3, 4, 5,
It is necessary to write data in 6 and detect the coincidence by the comparator to realize the PWM signals 19b, 19d and 19f of each phase. Start signal output of these AD conversions, each register 7, 8
In order to read out the data and write the set values to the registers 3, 4, 5, and 6, the arithmetic circuit 1 needs to perform these processes before the next overflow signal 15a and the underflow signal 15b are generated. Otherwise, there was a problem that the frequency could not be increased and high-speed driving could not be performed. Further, when the carrier frequency is increased to reduce the noise of the inverter, there are problems that the PWM calculation process is limited and the load on the calculation circuit is further increased, and high-precision control cannot be performed.

The present invention has been made in order to solve these problems, and its purpose is to reduce the load on the processing capacity of the sub-arithmetic circuit and to realize a highly accurate A by the arithmetic circuit.
Achieves D conversion start timing, P at high carrier
An object of the present invention is to provide a PWM control device which can eliminate the WM calculation processing time limit, reduce the load on the processing capacity of the calculation circuit, and can be used for a wide range of inverter applications. That is, the data of the PWM signal in an arbitrary carrier cycle can be set in the previous sampling cycle, the processing time by monitoring the overflow signal and the underflow signal output from the carrier generation circuit by the arithmetic circuit is eliminated, and the inverter device Allows you to provide more processing time for other features of. In addition, it is possible to generate a PWM waveform that can be applied to a wide range of inverter applications even when the carrier frequency is increased. In addition, PWM
Even when the carrier frequency is changed during the operation of the control device, the pulse width of the PWM signal of each phase is controlled with high accuracy and a stable waveform of the PWM signal is generated.

[0010]

In order to solve the above problems, a PWM generator of the present invention is a PWM controller for performing pulse width modulation from comparison data between a value output from an arithmetic circuit and carrier generator output. , A plurality of registers at the first stage for holding a plurality of setting data output from the arithmetic circuit, a carrier mountain / valley counter circuit for counting the mountains / valleys of the carrier generation circuit, and the carrier mountain / valley counter circuit is the carrier mountain / valley counter. A second stage that outputs a carrier mountain valley counter circuit signal when the value set in the circuit and the carrier mountain valley counter value match, and holds the plurality of register outputs of the first stage by the carrier mountain valley counter circuit output signal. Of a plurality of registers of the carrier generation circuit and the counter value of the output of the carrier generation circuit and the output of the register of the second stage When, in which a current detector for detecting a motor current. Further, in synchronization with the carrier mountain / valley counter circuit output signal, when the lowest signal of the carrier mountain / valley counter circuit set value is "L", the previous output is inverted, and when it is "H", the carrier output signal is continued. It is characterized by Further, the AD converter is activated and the current is detected by the current detector in synchronization with the output signal of the carrier mountain / valley counter circuit. Further, the second stage register is a carrier counter frequency value register, and the carrier frequency is updated in synchronization with the carrier peak / valley counter circuit output signal. Further, the second stage register is used as a comparison value register, and the comparator register value which is a voltage command is updated in synchronization with the carrier peak / valley counter circuit output signal.

[0011]

BEST MODE FOR CARRYING OUT THE INVENTION Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a PWM signal generation portion in a PWM control device according to an embodiment of the present invention. Carrier frequency setting register 3, U-phase PWM setting register 4, V-phase PWM setting register 5, W-phase PWM setting register 6, U-phase AD data register 7, V-phase AD data register 8, carrier generation circuit 15, count clock 16, The PWM generation circuit 19, the gate driver 20, the current detector 21, and the electric motor 22 are shown in FIG.
Is the same as that shown in. In the PWM control device of the present invention, the carrier mountain / counter counter setting register 2, the carrier frequency register setting register 3, the U-phase PWM setting register 4, the V-phase PWM setting register 5, and the W-phase PWM setting register 6 are used as the first-stage plural registers. Has been assigned.

On the other hand, carrier Yamatani counter value register 17
Has an initial value, and when this value and the number of occurrences of the overflow signal 15a and the underflow signal 15b match, the carrier peak / valley counter circuit output signal which is the carrier peak / valley counter circuit output is output. The outputs of the plurality of registers in the first stage are latched in the plurality of registers in the second stage by the output signal of the carrier mountain / valley counter circuit. As a plurality of registers in the second stage, carrier mountain / valley counter value register 17, carrier frequency register value register 9, U-phase comparison value register 1
0, V-phase PWM comparison value register 11 and W-phase PWM comparison value register 12 are assigned. Also, U-phase PWM
Generation circuit 19a, V-phase PWM generation circuit 19c, W-phase PW
The M generation circuit 19e compares the output data 10a, 11a, 12a of the U-phase PWM comparison value register 10, the V-phase PWM comparison value register 11, and the W-phase PWM comparison value register 12 with the counter value 15c, respectively, and outputs the U-phase PWM signal 19b. , V
The phase PWM signal 19d and the W phase PWM signal 19f are output. The output signal of the carrier Yamatani counter circuit is AD.
It is connected to the conversion start terminals of the converters 13 and 14, and AD is generated every time a carrier mountain / counter counter circuit output signal is generated.
Conversion is performed and the result is output from 13a and 14a.
U-phase AD data register 7, V-phase AD data register 8
Holds 13a and 14a, and the arithmetic circuit 1 performs read signals 1g and 1h via the data bus 1a.

The operation of the PWM control device thus configured will be described. First, the carrier generation circuit 15 is caused to count by the count clock 16. Then, the carrier peak / valley counter circuit output signal 18a is first output by the initial value operation of the carrier peak / valley counter. The AD converters 13 and 14 operate with the carrier mountain / counter counter circuit output signal, and the arithmetic circuit 1 reads out these data from the data bus 1 with read signals 1g and 1h. The arithmetic circuit 1 performs a PWM operation on the basis of the read data, and each data that becomes valid in the next carrier mountain / valley counter circuit output signal is converted into carrier mountain / valley counter setting register 2, carrier frequency register setting register 3, U phase PWM setting register 4, V phase. PW
Writing to the M setting register 5 and the W-phase PWM setting register 6.

First, frequency data 3 for generating a PWM signal
The operation when is set will be described. When changing the carrier frequency, first, data is written from the arithmetic unit to the carrier frequency setting register 3. When an output signal of the carrier ridge / valley counter circuit is generated, the value of the carrier frequency setting value register 9 is changed to the carrier frequency setting register output 3
a, and the carrier generator circuit outputs the register output 9a.
The frequency depends on the value of. Therefore, the frequency is updated by the carrier mountain trough counter circuit output signal which comes out first from the arithmetic circuit.

Next, the operation when the PWM setting of each phase is updated will be described. When the calculation results of the PWM comparison data for each phase are sequentially written in the PWM setting registers 4, 5, and 6 and the carrier peak / valley counter circuit output signal is generated,
The value of each phase comparison value register 10, 11, 12 is the PWM
The setting register outputs 4a, 5a, 6a are held, and the PWM generating circuit 19 outputs the register outputs 10a, 11a, 12a.
PWM is generated according to the value of. Therefore, when the PWM set value and the carrier frequency are set, the calculation result is output and updated with the first carrier peak / valley counter circuit output signal. FIG. 2 shows the carrier frequency setting and P when changing from low speed operation to high speed operation in the present embodiment.
The waveforms of the carrier generation circuit 15 and the U-phase PWM generation circuit 19a when the WM setting is performed are shown. The overflow signal 15a, the underflow signal 15b, and the write signal to each register are normally "H", and during operation, for example, one pulse of the count clock is "L" pulse.

The operation of the PWM controller of FIG. 1 will be described in more detail with reference to FIG. In FIG. 2, when the carrier generation circuit 15 is operating with the count clock 16, the arithmetic circuit 1 constantly repeats various calculations to control the PWM generation. The PWM operation is one of these processes. When the PWM operation is performed, the carrier peak / valley counter setting value, the carrier frequency value, and the PWM
The comparison value is calculated, and the carrier mountain / valley counter setting register 2, the carrier frequency setting register 3, the U-phase PWM setting register 4, and the V-phase PWM, which are a plurality of registers in the first stage
The calculation result is written in the setting register 5 and the W-phase PWM setting register 6. The written register outputs are respectively connected to the plurality of registers of the second stage, and when the carrier mountain / valley counter circuit output signal is generated, the carrier mountain / valley counter value register 1 which is the plurality of registers of the second stage is generated.
7, carrier frequency value register 9, U-phase comparison value register 1
0, V phase comparison value register 11, W phase comparison value register 12
Held in.

The carrier hill / valley counter circuit 18 loads the value written in the carrier hill / valley counter setting register 2 into the carrier hill / valley counter value register 17 with the carrier hill / valley counter circuit output signal. It is initialized to "0", and the carrier peak / valley counter circuit output 18a (third signal) is output at the start of the first carrier. Further, the other registers in the first and second stages are also initialized to predetermined values. The AD conversion is started by the carrier mountain / valley counter circuit output signal generated by the initial value, the arithmetic circuit 1 performs the first PWM calculation from the U-phase V-phase current value, and only the U-phase PWM is changed in the figure. . Modified U-phase PWM setting register 4
Is the output of the carrier-yama-tani counter circuit, which is the carrier-yama-tani counter output, the U-phase comparison value register 1
The U-phase PWM signal 19b is held at 0 and compared with the carrier counter value 15c in the U-phase PWM generation circuit 19a at the next stage.
Occurs. Next, the carrier frequency is raised in order to achieve high-speed operation in the second arithmetic processing, and after the processing is completed, the carrier peak / valley counter setting register 2 is set to "1" and the carrier frequency setting register 3 is set to 1/2 of the previous value. Desired data is written in the set value and the U-phase PWM setting register 4. Then, these writings are held in the register of the second stage in the valley where carriers in the figure first occur. After that, the carrier period is halved. Further, the carrier peak / valley counter setting becomes "1", and when the underflow signal and the overflow signal are counted twice, the carrier peak / valley counter circuit output signal is output, so that the same cycle as the previous cycle can be maintained.

The carrier status signal is synchronized with the carrier peak / valley counter circuit output signal, the previous output is inverted when the lowest signal of the carrier peak / valley counter circuit setting value is "L", and the previous output is continued when it is "H". However, when this signal is "H", the carrier peak / valley counter circuit output signal is generated next at the carrier peak, and when it is "L", the carrier peak / valley counter circuit output signal is generated next at the carrier peak. Since a signal indicating that the next PWM pattern is effective in which of the carrier peaks and valleys, more advanced PWM control can be performed.

As described above, the carrier peak / valley counter setting register, the carrier frequency setting register, and the U-phase P are used with the output signal of the carrier peak / valley counter circuit having the sampling period.
WM setting register, V-phase PWM setting register, W-phase PW
Since the M setting register can be updated, the waiting time between detecting the timing of writing the carrier frequency setting value and the PWM setting value of each phase to the carrier generation circuit 15 and the PWM generation circuit 19 by the calculation circuit 1 is reduced, and the calculation is performed. Circuit 1
It is possible to reduce the load on the processing power of and to generate a PWM waveform that can be applied to a wide range of inverter applications. Although the U-phase waveform has been described in the above embodiment,
It goes without saying that the V-phase and W-phase waveforms can be realized similarly to the U-phase waveform.

[0020]

As described above, according to the present invention, a plurality of registers in the first stage for temporarily holding the data processed by the arithmetic circuit 1 based on the current value, the overflow signal 15a and the underflow signal 15a. Carrier peak / valley counter circuit which counts the number of generations of flow signal 15b, and carrier peak / valley counter circuit output signal 18a output when carrier peak / valley counter value register output 17a and carrier peak / valley counter value match
And a plurality of registers B of the second stage for holding the plurality of registers A of the first stage with the carrier peak / valley counter circuit output signals, and a case where the lowest signal of the carrier peak / valley counter value register is "L" When the output is inverted and the output is "H", by providing the carrier status signal that continues the previous output, the data of the PWM signal in a certain arbitrary carrier cycle can be set in the previous sampling cycle, and the arithmetic circuit operates as a carrier. It is possible to eliminate the processing time due to the monitoring of the overflow signal and the underflow signal output from the generation circuit, and to provide a large amount of processing time for other functions of the inverter device. Further, even when the carrier frequency is increased, the load on the processing capability of the arithmetic circuit is reduced, so that it is possible to generate a PWM waveform that can be applied to a wide range of inverter applications. Further, even if the carrier frequency is changed, the period of the AD conversion start signal, that is, the sampling period is performed at a constant period according to the carrier peak / valley counter value, so that the pulse width of the PWM signal of each phase can be controlled with high accuracy. Therefore, a stable waveform of the PWM signal can be realized.

[Brief description of drawings]

FIG. 1 is a block diagram of a PWM control device according to an embodiment of the present invention.

FIG. 2 is a timing chart of the PWM control device of FIG. 1 according to the present invention.

FIG. 3 is a block diagram of a conventional PWM control device.

FIG. 4 is a timing chart of the PWM control device of FIG. 3 which is a conventional example.

[Explanation of symbols]

1 arithmetic circuit 1a Data bus 1b Carrier Yamatani counter setting write signal 1c Carrier frequency setting write signal 1d U-phase PWM setting write signal 1e V-phase PWM setting write signal 1f W-phase PWM setting write signal 1g U-phase AD data read signal 1h V-phase AD data read signal 1i AD conversion start signal 2 Carrier Yamatani counter setting register 2a Carrier Yamatani counter setting register output 3 Carrier frequency setting register 3a Carrier frequency setting register output 4 U-phase PWM setting register 4a U-phase PWM setting register output 5 V phase PWM setting register 5a V phase PWM setting register output 6 W-phase PWM setting register 6a W-phase PWM setting register output 7 U-phase AD data register 7a U phase AD data register output 8 V phase AD data register 8a V phase AD data register output 9 Carrier frequency value register 9a Carrier frequency value register output 10 U phase comparison value register 10a U-phase comparison value register output 11 V phase comparison value register 11a V phase comparison value register output 12 W phase comparison value register 12a W-phase comparison value register output 13, 14 AD converter 15 Carrier generation circuit 15a Overflow signal 15b Underflow signal 15c counter value 16 count clock 17 Carrier Yamatani counter value register 17a Carrier Yamatani counter value register output 18 Carrier Yamatani counter circuit 18a Carrier Yamatani counter circuit output 18b Carrier status signal 19 PWM generation circuit 20 Gate driver circuit 21 Current detector 22 Electric motor

Claims (5)

[Claims] 1. A PW that performs pulse width modulation based on comparison data between a value output from an arithmetic circuit and an output from a carrier generation circuit.
In the M control device, a plurality of registers in the first stage for holding a plurality of setting data output from the arithmetic circuit, a carrier mountain / valley counter circuit for counting the mountains / valleys of the carrier generation circuit, and the carrier mountain / valley counter circuit When the value set in the carrier mountain / valley counter circuit and the carrier mountain / valley counter value match, a carrier mountain / valley counter circuit signal is output, and the plurality of register outputs of the first stage are held by the carrier mountain / valley counter circuit output signal. A plurality of registers in the second stage, a comparator for comparing the counter value of the carrier generation circuit output with the register output in the second stage, and a current detector for detecting the motor current. And a PWM control device. 2. When the lowest signal of the carrier peak / valley counter circuit set value is "L", the previous output is inverted in synchronization with the carrier peak / valley counter circuit output signal, and the previous output is continued when it is "H". The PWM control device according to claim 1, wherein the PWM control device uses a carrier state signal. 3. The PWM according to claim 1, wherein the AD converter is activated and the current is detected by the current detector in synchronization with the carrier mountain / valley counter circuit output signal.
Control device. 4. The PWM control device according to claim 1, wherein the second-stage register is a carrier counter frequency value register, and the carrier frequency is updated in synchronization with the carrier peak / valley counter circuit output signal. . 5. The comparator register value, which is a voltage command, is updated in synchronism with the carrier mountain / counter counter circuit output signal, wherein the second stage register is a comparison value register. PWM controller.