JP2005269880A - Three-phase voltage type pwm inverter device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a three-phase voltage type PWM inverter device which can detect each phase current based on the detected value of a DC bus line current by a simple and inexpensive constitution. <P>SOLUTION: A current detection circuit 8 detects the DC bus line current applied to a shunt resistor 1 of an inverter main circuit 2. A sample hold circuit 9 samples and holds a current value detected by the current detection circuit 8. A micro computer 4 detects the current value held by a capacitor 9c of the sample hold circuit 9 as a phase current of a particular phase determined by switching patterns of switching elements 2u to 2z, at the timing of the mountain vicinity or the valley vicinity of a PWM carrier signal. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a three-phase voltage type PWM inverter device, and more particularly to a three-phase voltage type PWM inverter device that detects a phase current of each phase based on a detected value of a DC bus current of an inverter main circuit. .

  Conventionally, in a three-phase voltage type PWM inverter device, a DC current detector that detects a DC bus current by providing a shunt resistor in an inverter main circuit and detecting a voltage at both ends thereof as a countermeasure against overcurrent to a semiconductor switching element. In addition, a configuration in which two current sensors are provided to detect a two-phase phase current has been adopted. However, the above-described conventional PWM inverter device has a drawback that not only the device is increased in size but also the manufacturing cost is increased by providing two current sensors for detecting the phase current.

  In view of the drawbacks of the prior art, conventionally, a single current detector is provided to detect the DC bus current of the inverter main circuit, and based on the detected value and the switching pattern of the switching element of each phase. A technique for detecting a phase current has been proposed (see, for example, Patent Document 1 and Patent Document 2).

  On the other hand, in the three-phase voltage type PWM inverter device, a phase current detector is provided on one of the three-phase alternating current lines to obtain a current phase based on the applied voltage phase at the alternating current zero cross timing, and this current phase is set to a desired value. There has been proposed a technique for stabilizing the operation or the like by controlling so as to be (see, for example, Patent Document 3).

In addition, an inverter having a switching element fed from a DC bus and controlled by a control circuit is provided, and a shunt for measuring a DC current flowing through the DC bus is supplied to the DC bus, and two components of an output voltage vector Means for calculating two vectors, each of which has at least one equal to the predetermined value, such that an average of these vectors is equal to the output voltage vector when at least one of the two is less than the predetermined value. In particular, a frequency converter for an AC motor has been proposed in which the two vectors are applied between two consecutive symmetrical PWM periods (see, for example, Patent Document 4).
Japanese Patent No. 2712470 Japanese Patent No. 2563226 JP-A-5-236789 Japanese Patent Laid-Open No. 11-4594

  However, the conventional technique described in Patent Document 1 has a problem that the configuration is complicated because the phase current of each phase is individually detected using the sample-and-hold circuit for the number of phases.

  In the prior art described in Patent Document 2, it is necessary to detect the current at any two timings within the PWM cycle. Therefore, A / D conversion for phase current detection is performed using a general microcomputer. There is a problem that it is difficult to do.

  Further, the conventional technique described in Patent Document 3 has a problem that the phase current detector is generally expensive and large in size, and does not meet the market needs of low cost and downsizing of the inverter device. In addition, since the current phase is detected at the current zero cross timing, the phase is detected every 180 degrees, and there is a problem that the instantaneous phase cannot be detected. In addition, when the current amplitude is small, there is also a problem that phase detection cannot be performed because zero cross cannot be detected.

  Further, in the prior art described in Patent Document 4, in the first PWM period in which two pulse widths are set to be equal to or longer than a predetermined time, one of the two voltage vectors is divided into two to shorten the pulse width, There is a problem that phase current detection with high accuracy may not be performed. For example, FIG. 30A is an example of a vector diagram and a switching pattern diagram when a command voltage vector is generated in a single PWM period, and FIG. 30B is a case when a command voltage vector is generated in two PWM periods. It is an example of a vector diagram and a switching pattern diagram. In FIG. 30B, current detection is performed with the pulse periods of the voltage vectors V1 and V2 being equal to or greater than a predetermined width in the first PWM period, but one voltage vector V2 is divided into two to shorten the pulse width.

  The present invention has been made in view of the above-described problems, and provides a three-phase voltage type PWM inverter device capable of detecting the phase current of each phase based on the detected value of the DC bus current with a simple and inexpensive configuration. It is a problem to be solved.

  Hereinafter, each means suitable for solving the above-described problems will be described with additional effects and the like as necessary.

  The three-phase voltage type PWM inverter device of the present invention is a three-phase voltage type PWM inverter device having an inverter main circuit using a semiconductor switching element, a DC bus current detecting means for detecting a DC bus current in the inverter main circuit, Sample hold means for sampling and holding the current value detected by the DC bus current detection means, and the current value held by the sample hold means at the timing near the peak or valley of the PWM carrier signal. Phase current detecting means for detecting a phase current of a specific phase determined by the switching pattern of the element.

  Therefore, the DC bus current detecting means detects the DC bus current in the inverter main circuit, the sample hold means samples and holds the current value detected by the DC bus current detecting means, and the phase current detecting means is the sample hold means. Is detected as a phase current of a specific phase determined by the switching pattern of the semiconductor switching element at a timing near the peak or valley of the PWM carrier signal. Therefore, it is possible to use a general and inexpensive microcomputer that performs A / D conversion at the timing of the peak or valley of the PWM carrier signal for creating the PWM signal as the phase current detection means, and the sample hold means. Since the phase current can be detected only by providing it at one place, the three-phase voltage type PWM inverter device can be made simple and inexpensive.

  In a preferred aspect of the three-phase voltage type PWM inverter device, a phase current of one specific phase is detected at a timing near the peak of the PWM carrier signal, and at a timing near a valley adjacent to the peak of the PWM carrier signal. It is characterized by detecting a phase current of another specific phase.

  Therefore, since the two-phase phase current is detected continuously at the timing near the peak of the PWM carrier signal and the timing near the adjacent valley, the instantaneous current can be detected with high accuracy.

  In a preferred aspect of the three-phase voltage type PWM inverter device, the sample hold means generates a sample signal of the current value based on a combination of drive signals of a plurality of switching elements constituting the inverter main circuit. A signal generation means is provided.

  Therefore, the sample signal is generated by the sample signal generating means based on the combination of the drive signals of the plurality of semiconductor switching elements, and the current value is sampled and held based on the sample signal. In the dead time period in which both are turned off, the execution of the sample hold is surely stopped, so that the accuracy of the detected current value does not deteriorate.

  Also, the three-phase voltage type PWM inverter device of the present invention is a three-phase voltage type PWM inverter device having an inverter main circuit using a semiconductor switching element, and a DC bus current detecting means for detecting a DC bus current of the inverter main circuit. And peak hold means for peak-holding the current value detected by the DC bus current detection means, and the current value held by the peak hold means as a phase current of a specific phase determined by the switching pattern of the semiconductor switching element Phase current detection means for detecting.

  Therefore, the DC bus current detecting means detects the DC bus current of the inverter main circuit, the peak holding means peaks the current value detected by the DC bus current detecting means, and the phase current detecting means is the peak holding means. Is detected as a phase current of a specific phase determined by the switching pattern of the semiconductor switching element. Therefore, the phase current can be detected simply by taking in the peak level current value detected by the peak hold means and resetting the peak hold means, so that the three-phase voltage type PWM inverter device is simple and inexpensive. It can be configured.

  Further, in a preferable aspect of the three-phase voltage type PWM inverter device, the reset of the peak hold means is terminated in the vicinity of the timing at which the intermediate level modulation signal and the PWM carrier signal intersect among the three PWM modulation signals. It is structured.

  Therefore, since the switching pattern of the semiconductor switching element is switched at the timing at which the intermediate level modulation signal and the PWM carrier signal among the three PWM modulation signals intersect, by terminating the reset of the peak hold means around this timing, The phase current of each phase can be detected sequentially.

  In a preferred aspect of the three-phase voltage type PWM inverter device, the reset of the peak hold means is started after completion of taking in the current value held by the peak hold means.

  Therefore, after the phase current of one specific phase is reliably detected by taking in the current value held by the peak hold means, the reset of the peak hold means is started to prepare for the detection of the phase current of the other specific phase. State.

  Further, the three-phase voltage type PWM inverter device of the present invention has an inverter main circuit using semiconductor switching elements, and two-phase modulation for switching only two-phase semiconductor switching elements among the three phases with a predetermined PWM carrier cycle. In the control-type three-phase voltage type PWM inverter device, the PWM modulation means for modulating the pulse width so that the voltage vector generation period at the center of each PWM period becomes a predetermined width or more in two consecutive PWM periods, and the inverter DC bus current detection means for detecting the DC bus current of the main circuit, and the current value detected by the DC bus current detection means in the voltage vector generation period at the center of each PWM period, the switching pattern of the semiconductor switching element Phase current detection means for detecting as a phase current of a specific phase determined by And butterflies.

  Therefore, the PWM modulation means modulates the pulse width so that the voltage vector generation period at the center of each PWM period is equal to or greater than a predetermined width in two consecutive PWM periods, and the DC bus current detection means The DC bus current is detected, and the phase current detecting means detects the current value detected by the DC bus current detecting means during the voltage vector generation period at the center of each PWM period in the phase of a specific phase determined by the switching pattern of the semiconductor switching element. Detect as current. Accordingly, since a pulse having a predetermined width or more can be detected in the central part of the PWM period that is not divided into two, it is possible to avoid a decrease in accuracy of current detection.

  Further, in a preferred aspect of the three-phase voltage type PWM inverter device, the PWM modulation means sets the pulse width so that the phase difference between the voltage vectors generated at the center of each of the two consecutive PWM periods is 120 degrees. It is characterized by modulating.

  Therefore, since the phase difference between the voltage vectors generated at the center of each of the two consecutive PWM periods is not 180 degrees, it is possible to detect currents in two different phases and further increase the pulse width.

  Further, in a preferred aspect of the three-phase voltage type PWM inverter device, the PWM modulation means is configured to provide two voltage vectors having a phase difference of 120 degrees and two voltage vectors having a phase difference of 180 degrees with respect to the voltage vector. Use in successive PWM periods, and generate two voltage vectors having a phase difference of 60 degrees out of the four voltage vectors in the first PWM period and the remaining two voltage vectors in the second PWM period, respectively. It is characterized by.

  Accordingly, even when the degree of modulation is low, opposing vector components (with a phase difference of 180 degrees) can be provided, so that a long pulse width can be generated.

  In addition, a preferable aspect of the three-phase voltage type PWM inverter device is that the current value Ia (n) detected during the current PWM period and the current value Ia (n−2) detected during the previous PWM period. Based on the average value and the current value Ib (n-1) detected in the previous PWM period, at least one of current amplitude, current phase, d-axis current Id on the rotation coordinate axis, and q-axis current Iq. It is characterized by calculating.

  Therefore, since the current detection simultaneity can be ensured, the detection accuracy of the current phase, current amplitude, d-axis current Id, and q-axis current is improved.

  Further, the three-phase voltage type PWM inverter device of the present invention has an inverter main circuit using semiconductor switching elements, and two-phase modulation for switching only two-phase semiconductor switching elements among the three phases with a predetermined PWM carrier cycle. In the control-type three-phase voltage type PWM inverter device, the DC bus current detection means for detecting the DC bus current of the inverter main circuit, and the current value detected by the DC bus current detection means are set near the peak of the PWM carrier signal. Or a phase current detection means for detecting a phase current of a specific phase determined by a switching pattern of the semiconductor switching element at a timing near the valley.

  Therefore, the DC bus current detection means detects the DC bus current of the inverter main circuit, and the phase current detection means uses the current value detected by the DC bus current detection means as a timing near the peak or valley of the PWM carrier signal. Thus, it is detected as a phase current of a specific phase determined by the switching pattern of the semiconductor switching element. That is, in the two-phase modulation control, the center of the generation period of two different basic voltage vectors having a magnitude is near the peak or valley of the PWM carrier signal, so the peak or valley of the PWM carrier signal for creating the PWM signal It is possible to use a general and inexpensive microcomputer that performs A / D conversion at the timing as the phase current detection means, and to detect the phase current without providing a sample hold circuit, a peak hold circuit, a logic circuit, etc. Therefore, the three-phase voltage type PWM inverter device can be made very simple and inexpensive.

  In a preferred aspect of the three-phase voltage type PWM inverter device, one command voltage vector is created in a specific period composed of two or more PWM carrier periods, and the command voltage vector is generated in each PWM carrier period in the specific period. The basic voltage vector component is changed.

  Therefore, for example, even when it is difficult to accurately detect the current value, for example, when the command voltage vector is close to a single basic voltage vector or when the modulation degree is low, the PWM carrier period within a specific period is larger than usual. By generating the basic voltage vector and changing the basic voltage vector component in each PWM carrier cycle so that the average of them becomes the command voltage vector, a sufficient time width for capturing the current value is secured. Therefore, the phase current can be detected with high accuracy.

  In a preferred aspect of the three-phase voltage type PWM inverter device, a zero voltage vector having no magnitude and a single basic voltage vector having a magnitude are generated in each PWM carrier cycle of the specific period. Features.

  Therefore, even when it is difficult to accurately detect the current value, for example, when the command voltage vector is close to a single basic voltage vector or when the modulation factor is low, for example, the peaks or valleys of the PWM carrier signal in each PWM carrier cycle By generating a single basic voltage vector that is larger than normal, which is the generation center, and changing the basic voltage vector component so that the average thereof becomes the command voltage vector, the time required for capturing the current value Since the phase current is sufficiently secured, the phase current can be detected with high accuracy.

  Further, in a preferable aspect of the three-phase voltage type PWM inverter device, the specific period includes a first period and a second period each having one PWM carrier cycle, and a modulation degree of one phase in three phases is It is approximately 100% in the first period and the second period, and the modulation degree of one phase in the other two phases is approximately 0% in the first period, or the modulation of one phase in the three phases The degree is approximately 0% in the first period and the second period, and the degree of modulation of one phase in the other two phases is approximately 100% in the first period.

  Therefore, when the PWM carrier signal is a valley at the boundary between the first period and the second period, the modulation degree of the phase where the modulation degree is approximately 0% is set to approximately 0% in the second period as it is. When the PWM carrier signal has a peak at the boundary between the first period and the second period, the modulation degree of the phase where the modulation degree is approximately 100% is approximately 100% even in the second period. By doing this, it is possible to use different voltage vector generation centers at successive peaks and troughs of the PWM carrier signal, so that it is possible to capture two-phase current values in a short period of time and capture instantaneous current with high accuracy. it can.

  In a preferred aspect of the three-phase voltage type PWM inverter device, each PWM carrier cycle in the specific period is changed at a peak or valley of the PWM carrier signal, and a single basic voltage vector in each PWM carrier cycle Is generated.

  Therefore, by making a change that shortens the PWM carrier cycle within a specific period, the difference between the two-phase current capture timings is reduced, and a single basic voltage vector is generated within each PWM carrier cycle, resulting in high accuracy. Instantaneous current can be detected.

  Further, a preferred aspect of the three-phase voltage type PWM inverter device is configured to perform control for switching between a period in which normal PWM modulation is performed and the specific period.

  Therefore, since the PWM modulation control in the specific period is thinned and executed by switching the period for performing the normal PWM modulation and the specific period at a predetermined timing and using them together, every carrier cycle performed in the specific period The number of times the PWM timer is set in the microcomputer can be reduced, and the load of software processing in the microcomputer can be reduced.

  In addition, in a preferable aspect of the three-phase voltage type PWM inverter device, in each of the first states in which each time width of each PWM carrier cycle in which a basic voltage vector having a magnitude is output is equal to or greater than a predetermined value, The current value is detected in the PWM carrier cycle, and the detection of the current value is prohibited in the second state in which the time width of any one of the PWM carrier cycles is less than a predetermined value.

  Therefore, since the current value is likely to be erroneously detected when the time width of the PWM carrier cycle in which the phase of the output voltage vector is close to the basic voltage vector is small, each time width of each PWM carrier cycle is a predetermined value or more. The current value is detected only in a certain first state, and the detection of the current value is prohibited in the second state in which any time width of each PWM carrier cycle is less than a predetermined value, thereby detecting the current value incorrectly. Can be prevented.

  In addition, a preferable aspect of the three-phase voltage type PWM inverter device is a q-axis current on a rotational coordinate axis, a d-axis current calculated from each current value and rotor position information detected in each PWM carrier cycle in the first state, It is characterized in that at least one information of a current phase or a current amplitude based on an applied voltage phase of a specific phase is stored in a memory.

  Therefore, in the second state in which the detection of the current value is prohibited, at least one of the q-axis current, the d-axis current, the current phase based on the applied voltage of the specific phase, and the current amplitude stored in the memory. Information can be read and used for motor control.

  Further, the three-phase voltage type PWM inverter device of the present invention is a three-phase voltage type PWM inverter device having an inverter main circuit using a semiconductor switching element, and a DC bus current detecting means for detecting a DC bus current in the inverter main circuit. And six types of basic voltage vectors V1 (1, 0, 0), V2 (1, 1, 0), V3 (0, 1, 0), V4 (0, 1, 1), V5 ( 0, 0, 1), at least one of V6 (1, 0, 1) and at least one of two types of zero voltage vectors V0 (0, 0, 0), V7 (1, 1, 1) having no magnitude. Drive signal generating means for generating a drive signal for the semiconductor switching element by a method of generating a command voltage vector by combining them, and a current value detected by the DC bus current detecting means in the semiconductor switch Phase current detection means for detecting a phase current of a specific phase determined by the switching pattern of the switching element, wherein the drive signal generation means is substantially in the middle of each generation period of the odd-numbered basic voltage vectors V1, V3, V5. Is configured to select the zero voltage vector V7, and to select the zero voltage vector V0 at substantially the center of each generation period of the even-numbered basic voltage vectors V2, V4, and V6. .

  Accordingly, the drive signal generating means synthesizes at least one of the six types of basic voltage vectors V1 to V6 having a magnitude and at least one of the two types of zero voltage vectors V0 and V7 having no magnitude to generate a command voltage. When the drive signal of the semiconductor switching element is generated by the method of generating the vector, the DC bus current detecting means detects the DC bus current of the inverter main circuit, and the phase current detecting means is detected by the DC bus current detecting means. The current value is detected as a phase current of a specific phase determined by the switching pattern of the semiconductor switching element. Here, since the drive signal generating means selects the zero voltage vector V7 in the substantially central part of each generation period of the odd-numbered basic voltage vectors V1, V3, V5, the odd-numbered basic voltage vectors V1, V3, V5 are Each consists of one long pulse. On the other hand, since the zero voltage vector V0 is selected at substantially the center of each generation period of the even-numbered basic voltage vectors V2, V4, and V6, the even-numbered basic voltage vectors V2, V4, and V6 are each composed of one long pulse. Is done. Therefore, since a voltage vector having a large pulse width can be generated at all times, it is possible to improve the detection accuracy of the DC bus current by the DC bus current detecting means and expand the detectable region.

  Further, in a preferred aspect of the three-phase voltage type PWM inverter device, the drive signal generating means is configured to use the zero voltage vectors V0 and V7 by switching the electrical angle approximately every 60 degrees. Features.

  Therefore, selection of a zero voltage vector for constantly generating a voltage vector having a large pulse width can be realized with extremely simple logic.

  Further, in a preferred aspect of the three-phase voltage type PWM inverter device, the drive signal generating means is larger in size than the basic voltage vectors V2, V4, V6 in which the odd-numbered basic voltage vectors V1, V3, V5 are even-numbered. Is greater than zero voltage vector V7, and even-numbered basic voltage vectors V2, V4, and V6 are larger than odd-numbered basic voltage vectors V1, V3, and V5, and zero-voltage vector V0 is selected. It is characterized by selecting.

  Accordingly, among the odd-numbered basic voltage vector and the even-numbered basic voltage vector, a relatively large basic voltage vector can be formed by one long pulse, so that the DC bus current detecting means can detect the DC bus current. It can be detected with higher accuracy.

  Further, a preferred aspect of the three-phase voltage type PWM inverter device is characterized in that the drive signal generating means changes the PWM frequency in accordance with the rotational speed.

  Therefore, by changing the PWM frequency according to the rotational speed, it is possible to expand the area where the DC bus current can be detected by the DC bus current detecting means. For example, the power factor angle detectable region can be expanded by reducing the PWM frequency in the low rotation region.

  Further, the three-phase voltage type PWM inverter device of the present invention is a three-phase voltage type PWM inverter device having an inverter main circuit using a semiconductor switching element, and a DC bus current detecting means for detecting a DC bus current in the inverter main circuit. Driving signal generating means for generating a driving signal for the semiconductor switching element, and a phase value for detecting a current value detected by the DC bus current detecting means as a phase current of a specific phase determined by a switching pattern of the semiconductor switching element. Current phase and amplitude for calculating the current phase and current amplitude from the current detection means, the phase current value at an arbitrary timing θ1 detected by the phase current detection means, and the phase current value at timing θ1 + Δθ after lapse of Δθ from the θ1 And detecting means.

  Therefore, when the drive signal generating means generates a drive signal for the semiconductor switching element, the DC bus current detecting means detects the DC bus current of the inverter main circuit, and the phase current detecting means is detected by the DC bus current detecting means. The detected current value is detected as a phase current of a specific phase determined by the switching pattern of the semiconductor switching element. The current phase / amplitude detection means calculates the current phase and current amplitude from the phase current value at an arbitrary timing θ1 detected by the phase current detection means and the phase current value at timing θ1 + Δθ after the lapse of Δθ from the θ1. . Therefore, the current phase and current amplitude can be reliably calculated at an arbitrary timing using two phase current values having different timings.

  Also, a preferred aspect of the three-phase voltage type PWM inverter device is characterized in that the Δθ is set to approximately 60 degrees in electrical angle.

  Therefore, by calculating the current phase and current amplitude at a constant period, the number of calculations can be reduced and the calculation map can be reduced, and the load on the microcomputer executing the calculation process can be reduced.

  According to the three-phase voltage type PWM inverter device of the present invention, it is simple and inexpensive using a general and inexpensive microcomputer that performs A / D conversion at the timing of a peak or valley of a PWM carrier signal for generating a PWM signal. The phase current can be reliably detected with a simple configuration.

  In addition, according to the three-phase voltage type PWM inverter device of the present invention, the current phase and current amplitude can be reliably calculated at arbitrary timing using two phase current values having different timings based on detection of the DC bus current. Can do.

  Embodiments of a three-phase voltage type PWM inverter device embodying the present invention will be described below with reference to the drawings.

  First, an overall configuration of a three-phase voltage type PWM inverter device (hereinafter referred to as an inverter device) 1 of the first embodiment will be described with reference to the circuit diagram of FIG.

  The inverter device 1 includes an inverter main circuit 2 that supplies driving power to the U-phase, V-phase, and W-phase of a three-phase AC motor (hereinafter referred to as a motor) M based on a PWM switching signal, and an inverter main circuit DC power supply 3 for supplying power to motor M via 2 and a PWM signal having a duty ratio proportional to the output voltage command of the inverter and an A / D converter (ADC) for phase current detection are incorporated. The microcomputer 4, the dead time generating circuit 5 for generating a PWM switching signal based on the PWM signal inputted from the microcomputer 4, and the switching elements 2u, 2v, 2w of the upper arm of the inverter main circuit 2 based on the PWM switching signal The upper gate drive circuit 6 for turning on / off the inverter and each of the lower arms of the inverter main circuit 2 based on the PWM switching signal Switching element 2x, 2y, and lower gate drive circuit 7 for turning on and off the 2z, a current detecting circuit 8, and a sample-and-hold circuit 9. The microcomputer 4 constitutes the phase current detection means of the present invention, and the sample hold circuit 9 constitutes the sample hold means.

  The inverter main circuit 2 includes a U-phase upper switching element 2u, a U-phase lower switching element 2x, a V-phase upper switching element 2v, a V-phase lower switching element 2y, and a W-phase upper stage between the DC buses 2a and 2b. This is a three-phase inverter circuit having a well-known configuration in which six switching elements including a switching element 2w and a W-phase lower switching element 2z are bridge-connected. A shunt resistor 10 for current detection is provided on the DC bus 2b of the inverter main circuit 2.

  The dead time generating circuit 5 provides a dead time for preventing a short circuit with respect to the PWM signal input from the microcomputer 4, and drives the switching elements 2u, 2v, 2w, 2x, 2y and 2z above and below the arm of the inverter main circuit 2. A PWM switching signal is generated as an (on / off command).

  The current detection circuit 8 includes an operational amplifier and two resistors. The current detection circuit 8 detects a DC bus current flowing through the DC bus 2b by detecting a voltage at one end of the shunt resistor 10. The shunt resistor 10 and the current detection circuit 8 constitute the DC bus current detection means of the present invention.

  The sample hold circuit 9 is a circuit for sample-holding the detected value of the linear bus current by the current detection circuit 8, and includes a sample signal generation circuit 9a, an analog switch 9b, and a capacitor 9c. The sample signal generation circuit 9a is a logic circuit for generating a sample signal based on the PWM switching signal output from the dead time generation circuit 5, and the analog switch 9b is based on the sample signal input by the sample signal generation circuit 9a. On / off. Further, when the analog switch 9b is turned on, the current value of the linear bus current detected by the current detection circuit 8 is sampled and held by the capacitor 9c. The sample signal generation circuit 9a constitutes the sample signal generation means of the present invention.

  Next, the principle by which the phase current of each phase can be detected by detecting the DC bus current flowing through the shunt resistor 10 will be described.

First, a method for generating a PWM switching signal will be described using a space vector method. In the space vector method, a command voltage vector is expressed by eight basic voltage vectors, and is converted into time to determine on / off of six switching elements. The basic voltage vectors are 2 ³ = 8 kinds of voltage vectors determined by a combination of on / off of six switching elements in the voltage type inverter. In addition, as shown in FIG. 2, the eight types of basic voltage vectors V0 to V7 have six types of voltage vectors V1 to V6 that are different in phase by 60 degrees and have the same magnitude, and two types that have no magnitude. It consists of zero voltage vectors V0 and V7. Here, the eight types of vectors (Sa, Sb, Sc) correspond to eight switching modes, and when the positive-side switching elements 2u, 2v, 2w of each phase are on, Sa, Sb, Sc Is represented as “1”, and conversely, “0” is represented when the negative-side switching elements 2x, 2y, and 2z are on. In this embodiment, a three-phase PWM voltage is generated by synthesizing eight types of basic voltage vectors in any combination.

  Next, referring to the table shown in FIG. 3, the types of phase currents detected by the basic voltage vectors V1 to V6, the switching patterns of the switching elements corresponding to the basic voltage vectors, and the detected value of the DC bus current. Will be described. The reason why the zero voltage vectors V0 and V7 are excluded in the table of FIG. 3 is that the phase current is not detected because the reflux mode occurs at the zero voltage vector V0 or V7.

  In the table of FIG. 3, each column of the U-phase arm, the V-phase arm, and the W-phase arm indicates the U, V, and W phases that are turned on when the basic voltage vectors V1 to V6 shown at the left end of the table are generated. The “High” indicates that the switching element of the upper arm is turned on, and “Low” indicates that the switching element of the lower arm is turned on. The column of the detected phase current (Idc) indicates the type of phase current equal to the detected value Idc of the DC bus current when each of the basic voltage vectors V1 to V6 shown at the left end is generated, and Iu, Iv, and Iw are The phase currents flowing from the inverter main circuit 2 to the U phase, V phase, and W phase of the motor M are respectively represented as -Iu, -Iv, and -Iw from the U phase, V phase, and W phase of the motor M, respectively. 2 represents the phase current that flows to 2.

  For example, when the basic voltage vector V2 is generated, as shown in FIG. 4, the switching element 2u of the U-phase upper arm, the switching element 2v of the V-phase upper arm, and the switching element 2z of the W-phase lower arm are turned on. The DC bus current Idc flowing through the shunt resistor 10 instantaneously is equal to the W-phase current -Iw.

  Next, the flow of the phase current detection process in the present embodiment will be described with reference to the timing chart of FIG. FIG. 5 is a timing chart showing an example of each phase of PWM modulation degree signal, PWM carrier signal, PWM switching signal, basic voltage vector, DC bus current, sample hold value, sample signal, and A / D conversion interrupt timing. .

  When the basic voltage vector V4 is generated, the DC bus current Idc flowing through the shunt resistor 10 is detected by the current detection circuit 8. On the other hand, a sample signal is generated by the sample signal generation circuit 9a based on the PWM switching signal output from the dead time generation circuit 5. When the analog switch 9b is turned on by the input of the sample signal, the current detection value in the current detection circuit 8 is sampled and held by the capacitor 9c. Then, the microcomputer 4 generates an A / D conversion interrupt at a timing near the peak of the PWM carrier signal, takes in the current detection value sampled and held by the capacitor 9c, and performs A / D conversion. Here, when the basic voltage vector V4 is generated, the U-phase lower arm, the V-phase upper arm, and the W-phase upper arm are turned on, as is apparent from the table of FIG. 3, and the shunt resistor 10 has the phase current −Iu. Since the equal DC bus current Idc flows, the U-phase current -Iu can be detected by A / D converting the detected current value sampled and held by the capacitor 9c.

  Subsequently, when the basic voltage vector V <b> 5 is generated, the DC bus current Idc flowing through the shunt resistor 10 is detected by the current detection circuit 8. On the other hand, a sample signal is generated by the sample signal generation circuit 9a based on the PWM switching signal output from the dead time generation circuit 5. Then, the microcomputer 4 generates an A / D conversion interrupt at a timing near the valley of the PWM carrier signal, takes in a current detection value sampled and held by the capacitor 9c, and performs A / D conversion. Here, when the basic voltage vector V5 is generated, as apparent from the table of FIG. 3, the U-phase lower arm, the V-phase lower arm, and the W-phase upper arm are turned on, and the shunt resistor 10 is equal to the phase current Iw. Since the DC bus current is flowing, the W-phase current Iw can be detected by A / D converting the current detection value sampled and held by the capacitor 9c.

  As is clear from the above detailed description, according to the present embodiment, the current detection circuit 8 detects the DC bus current flowing through the shunt resistor 1 of the inverter main circuit 2, and the sample hold circuit 9 is connected to the current detection circuit 8. The microcomputer 4 samples and holds the detected current value, and the microcomputer 4 determines the current value held by the capacitor 9c of the sample hold circuit 9 according to the switching pattern of the switching element at the timing near the peak or the valley of the PWM carrier signal. Detect as phase current of specific phase. Therefore, it is possible to use a general and inexpensive microcomputer that performs A / D conversion at the timing of the peak or valley of the PWM carrier signal for generating the PWM signal, and only provides a sample hold circuit in one place. Thus, the phase current of each phase can be detected, so that the three-phase voltage type PWM inverter device can be configured simply and inexpensively.

  Further, since the two-phase phase current is detected continuously at the timing near the peak of the PWM carrier signal and the timing near the valley adjacent to the peak of the PWM carrier signal, the instantaneous current can be detected with high accuracy. .

  In addition, since the sample signal is generated by the sample signal generation circuit 9a based on the combination of the driving signals of the switching elements, the sample hold is surely executed in the dead time period in which the upper and lower switching elements of each phase are turned off. Since it is stopped, the accuracy of the detected current value does not deteriorate.

  Next, a three-phase voltage type PWM inverter device 21 according to a second embodiment of the present invention will be described with reference to the drawings. First, the overall configuration of the three-phase voltage type PWM inverter device 21 will be described with reference to the circuit diagram of FIG. In addition, the same code | symbol is attached | subjected about the structure same as 1st embodiment mentioned above, and detailed description about them is abbreviate | omitted.

  The inverter device 21 includes an inverter main circuit 2, a DC power source 3, a microcomputer 4, a dead time generation circuit 5, an upper gate drive circuit 6, a lower gate drive circuit 7, a current detection circuit 8, and a peak hold circuit. 29. The peak hold circuit 29 constitutes the peak hold means of the present invention.

  The peak hold circuit 29 is a circuit for holding (peak hold) the peak level value of the current value of the linear bus current detected by the current detection circuit 8, and includes an operational amplifier 29a, a diode 29b, a resistor, and a capacitor. 29c and a reset circuit 29d. The reset circuit 29d is composed of a transistor whose emitter is grounded and whose base is connected to the microcomputer 4. When a reset signal is input from the microcomputer 4 to the base, the charge accumulated in the capacitor 29c is discharged and reset. .

  Next, the flow of the phase current detection process in the present embodiment will be described with reference to FIG. FIG. 7 is a timing chart showing an example of each phase of the PWM modulation degree signal, PWM carrier signal, DC bus current, peak hold value, reset signal, and A / D conversion interrupt timing.

  When the basic voltage vector V4 is generated, the DC bus current Idc flowing through the shunt resistor 10 is detected by the current detection circuit 8. On the other hand, the peak level of the current detection value in the current detection circuit 8 is held (peak hold) by the capacitor 29c by the peak hold circuit 29. Then, the microcomputer 4 generates an A / D conversion interrupt at a timing near the peak of the PWM carrier signal, takes in the current detection value peak-held by the capacitor 29c, and performs A / D conversion. Here, when the basic voltage vector V4 is generated, the U-phase lower arm, the V-phase upper arm, and the W-phase upper arm are turned on, as is apparent from the table of FIG. 3, and the shunt resistor 10 has the phase current −Iu. Since the equal DC bus current Idc flows, the U-phase phase current -Iu can be detected by A / D converting the current value (peak hold value) held by the capacitor 29c.

  Subsequently, after the microcomputer 4 completes the acquisition of the peak hold value, a reset signal is input from the microcomputer 4 to the reset circuit 29d, and the reset of the peak hold circuit 29 is started. Then, the resetting of the peak hold circuit 29 is completed in the vicinity of the timing at which the intermediate level modulation signal and the PWM carrier signal among the three PWM modulation signals intersect. For example, in FIG. 7, since the V-phase modulation degree signal is at an intermediate level, the reset is completed near the timing at which the V-phase modulation degree signal and the PWM carrier signal intersect.

  Next, when the basic voltage vector V5 is generated, the DC bus current Idc flowing through the shunt resistor 10 is detected by the current detection circuit 8. On the other hand, the peak level of the current detection value in the current detection circuit 8 is held (peak hold) by the capacitor 29c by the peak hold circuit 29. Then, the microcomputer 4 generates an A / D conversion interrupt at a timing near the valley of the PWM carrier signal, takes in the current detection value peak-held by the capacitor 29c, and performs A / D conversion. Here, when the basic voltage vector V5 is generated, as apparent from the table of FIG. 3, the U-phase lower arm, the V-phase lower arm, and the W-phase upper arm are turned on, and the shunt resistor 10 is equal to the phase current Iw. Since the DC bus current flows, the W-phase current Iw can be detected by A / D converting the current value (peak hold value) held by the capacitor 29c.

  As is clear from the above detailed description, according to the present embodiment, the current detection circuit 8 detects the DC bus current flowing through the shunt resistor 10 of the inverter main circuit 2, and the peak hold circuit 29 includes the current detection circuit. The microcomputer 4 detects the peak hold value held by the peak hold circuit 29 as a phase current of a specific phase determined by the switching pattern of the switching element. Therefore, since the phase current can be detected only by taking in the current value of the peak level detected by the peak hold circuit 29 and resetting the peak hold circuit 29, the three-phase voltage type PWM inverter device can be simply and An inexpensive configuration can be obtained.

  Further, since the switching pattern of the switching element is switched at the timing at which the intermediate level modulation signal and the PWM carrier signal among the three PWM modulation signals cross, by terminating the reset of the peak hold circuit 29 around this timing, The phase current of each phase can be detected sequentially.

  Further, after the current value held in the peak hold circuit 29 is taken in, the phase current of one specific phase is reliably detected, and then the reset of the peak hold circuit 29 is started to detect the phase current of the other specific phase. Therefore, a plurality of phase currents can be detected continuously.

  Next, a three-phase voltage type PWM inverter device 41 according to a third embodiment of the present invention will be described with reference to the drawings. The three-phase voltage type PWM inverter device 41 is a two-phase modulation control type three-phase voltage type PWM inverter device that switches only two-phase semiconductor switching elements in three phases at a predetermined PWM carrier cycle. First, the overall configuration of the three-phase voltage type PWM inverter device 41 will be described with reference to the circuit diagram of FIG. In addition, the same code | symbol is attached | subjected about the structure same as 1st, 2nd embodiment mentioned above, and detailed description about them is abbreviate | omitted.

  The inverter device 41 includes an inverter main circuit 2, a DC power supply 3, a microcomputer 4, a dead time generation circuit 5, an upper stage gate drive circuit 6, a lower stage gate drive circuit 7, and a current detection circuit 8. Yes.

  Next, the flow of the phase current detection process in the present embodiment will be described with reference to FIG. FIG. 9 is a timing chart showing an example of the timing of the PWM carrier signal, basic voltage vector, and A / D conversion interrupt.

  When the basic voltage vector V5 is generated, the DC bus current Idc flowing through the shunt resistor 10 is detected by the current detection circuit 8. Here, since the two-phase modulation control is performed as described above in the present embodiment, the center of the generation period of the basic voltage vector is near the peak or valley of the PWM carrier signal. For this reason, in the example of FIG. 9, when the microcomputer 4 generates an A / D conversion interrupt at a timing near the valley of the PWM carrier signal, the current detection value detected by the current detection circuit 8 is captured and A / D conversion is performed. can do. Here, when the basic voltage vector V5 is generated, as apparent from the table of FIG. 3, the U-phase lower arm, the V-phase lower arm, and the W-phase upper arm are turned on, and the shunt resistor 10 is equal to the phase current Iw. Since the DC bus current is flowing, the W-phase current Iw can be detected by taking the current detection value detected by the current detection circuit 8 and performing A / D conversion.

  Subsequently, when the basic voltage vector V4 is generated, the DC bus current Idc flowing through the shunt resistor 10 is detected by the current detection circuit 8. At this time, since the center of the generation period of the basic voltage vector V4 is near the valley of the PWM carrier signal, the microcomputer 4 generates an A / D conversion interrupt at this timing, and is detected by the current detection circuit 8. The current detection value can be taken in and A / D converted. Here, when the basic voltage vector V4 is generated, as apparent from the table of FIG. 3, the U-phase lower arm, the V-phase lower arm, and the W-phase upper arm are turned on, and the shunt resistor 10 has the phase current −Iu. Since the equal DC bus current Idc flows, the U-phase phase current -Iu can be detected by A / D converting the current detection value detected by the current detection circuit 8.

  As is clear from the above detailed description, according to this embodiment, in the two-phase modulation control, the center of the generation period of two different basic voltage vectors having a magnitude is near the peak or valley of the PWM carrier signal. Therefore, it is possible to use a general and inexpensive microcomputer that performs A / D conversion at the timing of the peak or valley of the PWM carrier signal for creating the PWM signal, as well as the sample hold circuit, peak hold circuit, logic The phase current can be detected without providing a circuit or the like, and the three-phase voltage type PWM inverter device can be made extremely simple and inexpensive.

  Next, a first modification of the third embodiment will be described with reference to the drawings. First, a first modification will be described with reference to FIGS. 10 and 11. FIG. 10A shows the basic voltage vector component of the command voltage vector in the normal modulation period, and FIG. 10B shows the basic voltage vector component of the command voltage vector in the specific period.

  In the normal modulation period, as shown in FIG. 10A, a command voltage vector is created by synthesizing basic voltage vectors V4 and V5 having a normal length sandwiching the command voltage vector.

  On the other hand, in the specific period, the command voltage vector is created by changing the basic voltage vector component between the first period and the second period each having one PWM carrier cycle. That is, in the first period, the basic voltage vector V4 is set to a normal length and V5 is set to a length twice the normal length, and in the second period, the three-phase modulation degree is changed to change the normal length. Only the basic voltage vector V4 is generated.

  FIG. 11 is a timing chart showing the modulation degree signal, PWM carrier signal, basic voltage vector, DC bus current, and A / D conversion interrupt timing for each phase in the specific period shown in FIG.

  First, at the timing of the first valley of the PWM carrier signal, the microcomputer 4 generates an interrupt for taking in current. At this time, since the center of the generation period of the basic voltage vector V5 is in the vicinity of the valley of the PWM carrier signal, the current detection value detected by the current detection circuit 8 can be reliably captured and A / D converted. Here, when the basic voltage vector V5 is generated, as apparent from the table of FIG. 3, the U-phase lower arm, the V-phase lower arm, and the W-phase upper arm are turned on, and the shunt resistor 10 is equal to the phase current Iw. Since the DC bus current flows, the W-phase current Iw can be detected by A / D converting the current detection value detected by the current detection circuit 8.

  Next, the modulation degree of the three phases is changed at the timing of the peak of the PWM carrier signal. Subsequently, an interrupt for current capture is generated by the microcomputer 4 at the timing of the valley of the PWM carrier signal. At this time, since the center of the generation period of the basic voltage vector V4 is in the vicinity of the valley of the PWM carrier signal, the current detection value detected by the current detection circuit 8 can be reliably captured and A / D converted. Here, when the basic voltage vector V4 is generated, as apparent from the table of FIG. 3, the U-phase lower arm, the V-phase lower arm, and the W-phase upper arm are turned on, and the shunt resistor 10 has the phase current −Iu. Since the equal DC bus current Idc flows, the U-phase phase current -Iu can be detected by A / D converting the current detection value detected by the current detection circuit 8.

  FIG. 12 is a flowchart showing a flow of interrupt processing for A / D conversion in the specific period described above. As shown in FIG. 12, when an interrupt for A / D conversion occurs at the peak or valley timing of the PWM carrier signal, it is determined whether or not the PWM carrier signal is at the peak timing (step 1; hereinafter). , Abbreviated as S1, and other steps are the same). If it is the valley timing (S1: No), the current value is taken in by A / D conversion (S5), and the interrupt process is terminated. In S1, when it is a mountain timing (S1: Yes), it is determined whether it is the first period (S2). If it is the first period (S2: Yes), the modulation degree of the three phases is changed to the modulation degree for the first period (S3). On the other hand, when it is the second period (S2: No), the modulation degree of the three phases is changed to the modulation degree for the second period (S4).

  Therefore, according to this modification example, each PWM within a specific period is difficult even when accurate detection of the current value is difficult, for example, when the command voltage vector is close to a single basic voltage vector or when the modulation degree is low. A basic voltage vector larger than normal is generated in the carrier cycle, and the basic voltage vector component is changed for each PWM carrier cycle so that the average of them becomes the command voltage vector. Since a sufficient time width is ensured, the phase current can be detected with high accuracy.

  Next, a second modification of the third embodiment will be described with reference to the drawings. The second modification is characterized in that a zero voltage vector having no magnitude and a single basic voltage vector having a magnitude are generated in each PWM carrier cycle in a specific period.

  For example, FIG. 13A is a timing chart showing an example of the modulation degree signal of each phase, the PWM carrier signal, the basic voltage vector, the DC bus current, and the A / D conversion interrupt timing in one PWM cycle in the normal period. The basic voltage vector component of the period is constituted by basic voltage vectors V4 and V5 having a magnitude and a zero voltage vector V7. On the other hand, FIG. 13B shows a timing chart in the specific period of the present modified example, and the basic voltage vector component in the first period is the second voltage based on the basic voltage vector V4 and the zero voltage vector V7 which are longer than usual. The basic voltage vector component in this period is composed of a basic voltage vector V5 and a zero voltage vector V7 which are longer than usual.

  Therefore, according to the present modification, even when it is difficult to accurately detect the current value, such as when the command voltage vector is close to a single basic voltage vector or when the modulation degree is low, for example, PWM is performed in each PWM carrier cycle. A basic voltage vector component is changed so that a single basic voltage vector larger than usual with a peak or valley of the carrier signal as a generation center is generated, and the average of them is a command voltage vector. Since a sufficient time required for capturing the phase current is ensured, the phase current can be detected with high accuracy.

  Next, a third modification of the third embodiment will be described with reference to the drawings. In the third modification, the modulation degree of one phase in the three phases is approximately 100% in the first period and the second period, and the modulation degree of one phase in the other two phases is in the first period. The modulation degree of one phase in three phases is substantially 0% in the first period and the second period, and the modulation degree of one phase in the other two phases is in the first period. It is approximately 100%.

  For example, in the normal modulation period, as shown in FIG. 14A, the command voltage vector is created by combining the basic voltage vectors V4 and V5. In the specific period, as shown in FIG. During this period, the basic voltage vector V4 and V5 (which is longer than normal) are combined, and in the second period, the basic voltage vectors V4 and V3 are combined to create a command voltage vector. Here, a timing chart of the modulation degree signal, the PWM carrier signal, the basic voltage vector, and the DC bus current in each phase in one PWM cycle in the normal modulation period shown in FIG. 14A is expressed as shown in FIG. The On the other hand, the timing chart in the specific period of FIG. 14B is expressed as shown in FIG. That is, in the first period, the U-phase modulation factor is approximately 100 and the W-phase modulation factor is approximately 0%, and the phase current Iw is captured at the timing of the valley of the PWM carrier signal in the first period. . Next, the modulation degree of the U phase is maintained almost 100% even in the second period, and the modulation degree of the V phase and the W phase is changed, and is a boundary between the first period and the second period. The phase current -Iu is captured at the timing of the adjacent peaks of the PWM carrier signal.

  Therefore, according to this modification, when the PWM carrier signal is a valley at the boundary between the first period and the second period, the modulation degree of the phase where the modulation degree is approximately 0% is directly used as the second modulation degree. In this period, when the PWM carrier signal has a peak at the boundary between the first period and the second period, the modulation degree of the phase having the modulation degree of approximately 100% is directly set to the second degree. By setting the ratio to approximately 100% even during the period of time, it is possible to set the generation center of different voltage vectors at successive peaks and valleys of the PWM carrier signal, so that two-phase current values can be captured in a short period of time and high accuracy. Instantaneous current can be captured.

  Next, a fourth modification of the third embodiment will be described with reference to the drawings. The fourth modification is characterized in that the PWM carrier period within a specific period is changed at the peak or valley of the PWM carrier signal, and a single basic voltage vector is generated within each PWM carrier period.

  For example, with respect to an example of the modulation degree signal, the PWM carrier signal, the basic voltage vector, and the DC bus current of each phase in one PWM cycle in the normal modulation period shown in FIG. Is represented as shown in FIG. That is, the specific period is composed of three PWM carrier periods (first period, second period, and third period) that are shorter than usual. In the first period, only the basic voltage vector V4 is used in the second period. A command voltage vector is created by generating only the basic voltage vector V5 and only the zero voltage vector V7 in the third period.

  Therefore, according to the present modification, the change in shortening the PWM carrier cycle reduces the difference between the two-phase current capture timing, and a single basic voltage vector is generated in each PWM carrier cycle. Instantaneous current can be detected with high accuracy.

  Next, a fifth modification of the third embodiment will be described with reference to the drawings. This modification is characterized in that control is performed to switch between the specific period in the fourth modification described above and the period during which normal PWM modulation is performed. For example, as shown in FIG. 17, the modulation method is switched so that the PWM modulation in the specific period is performed once every time the normal PWM modulation period is continued 5 to 6 times.

  Therefore, according to the present modification, the PWM modulation control in the specific period is thinned out and executed by switching and using the specific period and the normal modulation period at a predetermined timing. The number of times the PWM timer is set in the microcomputer for each carrier cycle can be reduced, and the load of software processing in the microcomputer 4 can be reduced.

  Next, a sixth modification of the third embodiment will be described with reference to the drawings. In the present modification, the microcomputer 4 modulates the pulse width so that the voltage vector generation period at the center of each PWM period is equal to or greater than a predetermined width in two consecutive PWM periods, and the current detection circuit 8 The DC bus current Idc of the inverter main circuit 2 detected during the voltage vector generation period in the center is detected as a phase current of a specific phase determined by the switching pattern of the semiconductor switching element. The microcomputer 4 constitutes the PWM modulation means of the present invention.

  FIG. 18A is a vector diagram and a switching pattern diagram of each phase in an example in which a command voltage vector is generated in a single PWM period, and FIG. 18B is a diagram illustrating first and second PWM periods in the present modification. FIG. 5 is a vector diagram and an example of switching pattern of each phase in an example in which a command voltage vector is generated in FIG. As shown in FIG. 18B, current detection is performed in a voltage vector generation period that occurs in the center of the PWM period that is not divided into two. Specifically, current detection is performed in the voltage vector V1 generation period in the first PWM period, and in the voltage vector V3 generation period in the second PWM period. In addition, during these two consecutive PWM periods, PWM modulation is performed so that the voltage vector generation period at the center portion is not less than a predetermined width. According to this modification, since a pulse having a predetermined width or more can be detected in the central part of the PWM period that is not divided into two, a decrease in accuracy of current detection can be avoided.

  Next, a seventh modification of the third embodiment will be described with reference to the drawings. This modification is characterized in that, in the sixth modification, the microcomputer 4 modulates the pulse width so that the phase difference of the voltage vector generated at the center of each of the two consecutive PWM periods becomes 120 degrees. To do.

  FIG. 19A is a vector diagram and a switching pattern diagram of each phase in an example in which a command voltage vector is generated in a single PWM period, and FIG. 19B is a diagram illustrating first and second PWM periods in this modification. FIG. 5 is a vector diagram and an example of switching pattern of each phase in an example in which a command voltage vector is generated in FIG. As shown in FIG. 19B, current detection is performed in the voltage vector V1 generation period in the first PWM period, and current detection is performed in the voltage vector V3 generation period having a phase difference of 120 degrees from the voltage vector V1 in the second PWM period. . According to this modification, the phase difference between the voltage vectors generated at the center of each of the two consecutive PWM periods is not 180 degrees, so that it is possible to detect the currents of two different phases and further expand the pulse width. It becomes.

  Note that, in the example of FIG. 18B described above, the pulse width is set so that the phase difference of the voltage vector generated at the center of each of the two consecutive PWM periods is 120 degrees as in the example of FIG. 19B. In particular, two voltage vectors having a phase difference of 120 degrees and two voltage vectors having a phase difference of 180 degrees with respect to the voltage vector are used in two consecutive PWM periods. Of the voltage vectors, two voltage vectors having a phase difference of 60 degrees are generated in the first PWM period, and the remaining two voltage vectors are generated in the second PWM period. That is, the phase difference between the voltage vectors V1 and V3 not divided into two is 120 degrees, and the voltage vectors V1 and V6 having a phase difference of 60 degrees generated in the first PWM period and the phase difference of 60 degrees generated in the second PWM period. Are 180 degrees out of phase with voltage vectors V3 and V4. The example of FIG. 18B has an advantage that a long pulse width can be generated because it is possible to have opposing vector components (different in phase by 180 degrees) even at a lower modulation degree.

  Next, an eighth modification of the third embodiment will be described with reference to the drawings. In this modification, the microcomputer 4 as the drive signal generating means has at least one of six kinds of basic voltage vectors V1 to V6 having a magnitude and at least one of two kinds of zero voltage vectors V0 and V7 having no magnitude. In the method of generating the command voltage vector by combining the two, the zero voltage vector V7 is selected at substantially the center of each generation period of the odd-numbered basic voltage vectors V1, V3, V5, and the even-numbered basic voltage vector V2, The zero voltage vector V0 is selected at substantially the center of each generation period of V4 and V6.

  FIG. 20 is a diagram showing a voltage vector selection pattern in an example of the present modification. In FIG. 20A, since V1 pulse width (T1A + T1B) <V2 pulse width (T2), the zero voltage vector V0 is selected as the zero voltage vector, so that the even voltage vector V2 is composed of one long pulse. Has been. In FIG. 20B, since V1 pulse width (T1)> V2 pulse width (T2A + T2B), when the zero voltage vector V7 is selected as the zero voltage vector, the odd voltage vector V1 is composed of one long pulse. Has been.

  On the other hand, FIG. 21 is a diagram illustrating a comparative example in which a large voltage vector pulse is divided into two. In the comparative example, the V1 pulse width is larger than the V2 pulse width, but V0 is selected as the zero voltage vector, so the pulse of the basic voltage vector V1 exists in two, and each pulse width is halved. It is one.

  Next, an effect obtained by configuring the basic voltage vector with a long pulse by switching the zero voltage vectors V0 and V7 in the present modification will be described. First, the relationship between the match rate of the shunt detection phase current value (phase current value based on detection of the DC bus current flowing through the shunt resistor 10) with respect to the actual phase current value and the pulse width will be described. FIG. 22 is a graph showing the measurement results of the phase current value match rate when a synchronous reluctance motor (rated 0.53 Nm-2000 rpm) is driven by vector control at a torque of 0.137 Nm and a rotation speed of 500 rpm. However, the phase current value match rate = shunt detection phase current value / actual phase current value. The closer the match rate value is to “1”, the higher the accuracy of the shunt detection phase current value. As apparent from the graph of FIG. 20, there are cases where the coincidence rate is smaller or larger than 1 when the pulse width is less than 10 μs, and there are variations in the values, whereas the coincidence rate is almost “when the pulse width is 10 μs or more. 1 ”. From this, it is understood that the coincidence rate can be improved by setting the pulse width to 10 μs or more.

  The reason why the detection error of the phase current value becomes large when the pulse width is less than 10 μs is considered that the A / D conversion timing enters the ringing region of the bus current when the pulse width is less than 10 μs. FIG. 23 is a diagram illustrating an example of switching of voltage vectors and a change in bus current associated therewith. As is clear from FIG. 23, ringing for a predetermined time occurs in the bus current by switching the voltage vector. The dead time is 3.5 μs, the ringing time is 5 μs, and the sampling time (Tsmp) for A / D conversion is 1 μs. Since the microcomputer 4 is defined as pulse width = dead time + voltage vector generation period, it can be seen that if the pulse width is less than 10 μs, the A / D conversion timing enters the ringing region of the bus current.

  FIG. 24 is a diagram showing a modulation pattern and a pulse width in an example of this modification in which zero voltage vectors V0 and V7 under a certain operating condition are switched every 60 degrees in electrical angle. FIG. 24 shows that in the example, the pulse width is always 10 μs in all the basic voltage vectors. On the other hand, FIG. 25 is a diagram showing a modulation pattern and a pulse width in the comparative example in which the zero voltage vector V0 is always selected. From FIG. 25, in the comparative example, the pulse width is 10 μs in the odd-numbered voltage basic vectors V1, V3, and V5, but the pulse width is less than 10 μs in the even-numbered voltage basic vectors V2, V4, and V6. I understand that.

  As is clear from the above, according to the present modification, a voltage vector having a large pulse width can be generated at all times, so that the detection accuracy of the DC bus current Idc by the current detection circuit 8 is improved, thereby The phase current can be detected with high accuracy.

  In addition, since the zero voltage vectors V0 and V7 are configured to be used by switching the electrical angle approximately every 60 degrees, the selection of the zero voltage vector for constantly generating a voltage vector having a large pulse width is very simple logic. Can be realized. As the switching method between the zero voltage vectors V0 and V7, the zero voltage vector V7 is selected when the odd numbered basic voltage vectors V1, V3 and V5 are larger than the even numbered basic voltage vectors V2, V4 and V6. If the even-numbered basic voltage vectors V2, V4, and V6 are larger in size than the odd-numbered basic voltage vectors V1, V3, and V5, a method of selecting the zero voltage vector V0 may be employed. According to this method, among the odd-numbered basic voltage vector and the even-numbered basic voltage vector, a relatively large basic voltage vector can be configured by one long pulse, so that the DC bus current is higher. It can be detected with accuracy.

  Moreover, according to this modification, in addition to the effect mentioned above, the effect that a power factor angle detectable region is expanded is produced. FIG. 26 shows the pulse width at each rotation speed with the DC voltage Vdc = 390 V and the torque T = 0.5 Nm for the example shown in FIG. 24 and the comparative example shown in FIG. It is a graph which shows the result of having calculated the field which can secure the above pulse width. It can be seen that at each number of rotations, the value of the detectable region in the present modification exceeds the value of the detectable region in the comparative example. For example, at a rotational speed of 4000 rpm, it is 0% in the comparative example, while it is greatly expanded to 58% in the present modification.

  Furthermore, in this modification, the detectable region of the DC bus current can be expanded by changing the PWM frequency according to the rotational speed. For example, FIG. 27 measures the pulse width at each rotation speed with a PWM frequency of 10 kHz, 5 kHz, 2.5 kHz, a DC voltage Vdc = 390 V, and a torque T = 0.5 Nm in the present modification shown in FIG. It is a graph which shows the result of having calculated the field which can secure the pulse width of 10 microseconds or more in a 120 degree period. FIG. 27 shows that the power factor angle detectable region can be expanded by reducing the PWM frequency in the low rotation region. For example, when the rotational speed is 500 rpm, the detectable region is 0% at the PWM frequencies of 10 kHz and 5 kHz. However, by setting the PWM frequency to 2.5 kHz, the detectable region is expanded to 21%.

  Next, a ninth modification of the third embodiment will be described with reference to the drawings. In the present modification, in the third embodiment described above, the microcomputer 4 calculates the current phase and current amplitude from the phase current value at an arbitrary timing θ1 and the phase current value at timing θ1 + Δθ after the passage of Δθ from the θ1. It was configured as described above.

  Hereinafter, a method for calculating the current phase and the current amplitude will be specifically described. As shown in FIG. 28, when the shunt detection phase current at an arbitrary rotor position θ1 is + Iu (U-phase current) and the shunt detection phase current at rotor position θ1 + Δθ after the lapse of Δθ is −Iw (W-phase current). , Iu, and Iw are expressed by the following formulas 1 and 2, respectively. Here, α is the current phase, and Ia is the current amplitude.

  From the above two formulas, the current phase α and the current amplitude Ia are calculated by Formula 3 and Formula 4, respectively.

  Further, there are six patterns shown in the left column of Table 1 for combinations of shunt detection phase currents after the rotor positions θ1 and Δθ have elapsed, and the calculation formulas of current phase α and current amplitude Ia for each pattern are shown in the right column of Table 1. As shown in Note that Iu ′, Iw ′, and Iv ′ are phase current values when the detected phase current (Iu, Iw, Iv) at θ1 and the detected phase current after the lapse of Δθ are in the same phase.

  According to this modification, it is possible to reliably calculate the current phase and current amplitude at an arbitrary timing by using two phase current values at different timings. Then, by performing motor control using the calculated values of the current phase and current amplitude, it is possible to stabilize the operation and optimize the operation efficiency. Note that Δθ described above is preferably set to approximately 60 degrees in electrical angle. Thus, by calculating the current phase and current amplitude at a constant period, the number of calculations can be reduced and the calculation map can be reduced, and the load on the microcomputer 4 that executes the calculation process can be reduced.

  In addition, this invention is not limited to each embodiment mentioned above, A various change is possible in the range which does not deviate from the main point of this invention.

  For example, in the three-phase voltage type PWM inverter devices 1, 21, 41 of each of the embodiments, the time width of each PWM carrier cycle in which a basic voltage vector having a magnitude is output is a predetermined value or more. In this state, the current value is detected in each PWM carrier cycle, and in the second state in which any time width of each PWM carrier cycle is less than a predetermined value, detection of the current value is prohibited. Also good. According to this modification, since the current value is likely to be erroneously detected in a state where the time width of the PWM carrier cycle in which the phase of the output voltage vector is close to the basic voltage vector is small, the time width of each PWM carrier cycle is The current value is detected only in the first state that is equal to or greater than the predetermined value, and the current value is prohibited by detecting the current value in the second state in which any time width of each PWM carrier cycle is less than the predetermined value. It is possible to prevent erroneous detection of values.

  In the above-described modification, the q-axis current, d-axis current on the rotation coordinate axis calculated from each current value and rotor position information detected in each PWM carrier period in the first state, and the applied voltage phase of the specific phase are used as a reference. The current phase or the current amplitude may be configured to be stored in a memory. According to this modification, in the second state where the detection of the current value is prohibited, the q-axis current, the d-axis current, the current phase based on the applied voltage of the specific phase, and the current amplitude are stored in the memory. Of these, at least one piece of information can be read out and used for motor control.

  Furthermore, in the sixth or seventh modified example of the third embodiment described above, the current value Ia (n) detected during the current PWM period and the current value Ia (n) detected during the previous PWM period. -2) and the current value Ib (n-1) detected in the previous PWM period, current amplitude, current phase, d-axis current Id on the rotation coordinate axis, and q-axis current Iq Of these, at least one may be calculated. FIG. 29 is a diagram showing the modulation degree and current detection timing of each phase from the PWM period two times before to the current PWM period, and shows three current values Ia (n−2), Ib (n−1), The detection timing of Ia (n) is shown. According to this modification, since the current detection can be ensured simultaneously, the detection accuracy of the current phase, current amplitude, d-axis current Id, and q-axis current is improved.

  The present invention is applicable to a three-phase voltage type PWM inverter device having an inverter main circuit using a semiconductor switching element used for motor power control.

It is a circuit diagram which shows the electrical circuit structure of the three-phase voltage type | mold PWM inverter apparatus of 1st embodiment of this invention. It is a figure which shows a basic voltage vector. It is a table | surface which shows the relationship between a basic voltage vector, a switching pattern, and a detection phase current. It is a figure explaining the principle by which phase current -Iw is detected by detection of DC bus current at the time of basic voltage vector V2 generation. It is a timing chart which shows an example of a sample hold value capturing timing and each signal in the first embodiment. It is a circuit diagram which shows the electrical circuit structure of the three-phase voltage type PWM inverter apparatus of 2nd embodiment. It is a timing chart which shows the timing of taking in and holding a peak hold value and an example of each signal in the second embodiment. It is a circuit diagram which shows the electrical circuit structure of the three-phase voltage type PWM inverter apparatus of 3rd embodiment. It is a timing chart which shows an example of an electric current value taking-in timing in a third embodiment, and each signal. It is a figure showing the basic voltage vector component of the command voltage vector in the 1st modification of 3rd embodiment, (a) is a basic voltage vector component in a normal modulation period, (b) is in a specific period. Each of the basic voltage vector components is represented. FIG. 11 is a timing chart illustrating an example of a current value capturing timing and each signal in a specific period illustrated in FIG. It is a flowchart which shows the flow of the interruption process for A / D conversion in the specific period in the 1st modification of 3rd embodiment. (A) is a timing chart which shows an example of each signal in 1 PWM period in a normal modulation period, (b) is the electric current value taking-in timing in the specific period of the 2nd modification of 3rd Embodiment, and each 3 shows a timing chart showing an example of a signal. It is a figure showing the basic voltage vector component of the command voltage vector in the 3rd modification of 3rd embodiment, (a) is a basic voltage vector component in a normal modulation period, (b) is in a specific period. Each of the basic voltage vector components is represented. (A) is a timing chart which shows an example of each signal in 1PWM period in a normal modulation period, (b) is an example of a current value taking-in timing and each signal in a specific period shown in FIG. 14 (b). It is a timing chart which shows. (A) is a timing chart which shows an example of each signal in 1 PWM period in a normal modulation period, (b) is a current value taking-in timing in a specific period of the fourth modification of the third embodiment, and It is a timing chart which shows an example of each signal. It is a figure which shows the example of a waveform of the PWM carrier signal in the case of performing control which switches a normal modulation period and a specific period in the 5th modification of 3rd embodiment. (A) is the vector diagram in the example which generated the command voltage vector in the single PWM period, and the switching pattern figure of each phase, (b) continues in the 6th modification of a 3rd embodiment. It is the vector diagram in an example which generated the command voltage vector in two PWM periods, and the switching pattern figure of each phase. (A) is the vector diagram in the example which generated the command voltage vector in the single PWM period, and the switching pattern figure of each phase, (b) continues in the 7th modification of a 3rd embodiment. It is the vector diagram in an example which generated the command voltage vector in two PWM periods, and the switching pattern figure of each phase. In the eighth modification of the third embodiment, (a) shows an example in which the zero voltage vector V0 is selected, and (b) shows an example in which the zero voltage vector V7 is selected. It is a figure which shows the comparative example into which the pulse of the voltage vector was divided into two. It is a graph which shows the relationship between a phase current value agreement rate and a pulse width. It is a figure which shows an example of the relationship between switching of a voltage vector and a bus current change. It is a figure which shows the modulation pattern and pulse width in the Example which switches the zero voltage vectors V0 and V7. It is a figure which shows the modulation pattern and pulse width in the comparative example which always uses V0 as a zero voltage vector. It is a graph which shows the power factor angle detectable area | region when changing the rotation speed in the Example and comparative example of an 8th modification. It is a graph which shows the power factor angle detectable region in each PWM frequency in the 8th modification. It is explanatory drawing which shows the detection timing of the phase current in the 9th modification of 3rd embodiment. It is a figure which shows the modulation degree and electric current detection timing of each phase from the PWM period 2 times before in a modification to this PWM period. (A) is an example of a vector diagram and a switching pattern diagram when a command voltage vector is generated in a single PWM period, and (b) is a vector when a command voltage vector is generated in two PWM periods in the prior art. It is an example of a figure and a switching pattern figure.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1,21,41 ... Three-phase voltage type PWM inverter apparatus, 2 ... Inverter main circuit, 2u, 2v, 2w, 2x, 2y, 2z ... Semiconductor switching element, 4 ... Microcomputer (phase current detection means, drive signal generation means, PWM modulation means) 8 Current detection circuit (DC bus current detection means) 9 Sample hold circuit (sample hold means) 9a Sample signal generation circuit (sample signal generation means) 9c Capacitor (sample hold means) DESCRIPTION OF SYMBOLS 10 ... Shunt resistance (DC bus current detection means) 29 ... Peak hold circuit (peak hold means), 29c ... Capacitor (peak hold means)

Claims (24)

In a three-phase voltage type PWM inverter device having an inverter main circuit using a semiconductor switching element,
DC bus current detection means for detecting a DC bus current in the inverter main circuit;
Sample hold means for sample holding the current value detected by the DC bus current detection means;
Phase current detection means for detecting the current value held by the sample hold means as a phase current of a specific phase determined by the switching pattern of the semiconductor switching element at a timing near the peak or valley of the PWM carrier signal;
A three-phase voltage type PWM inverter device comprising:   Detecting a phase current of one specific phase at a timing near the peak of the PWM carrier signal and detecting a phase current of another specific phase at a timing near the valley adjacent to the peak of the PWM carrier signal. The three-phase voltage type PWM inverter device according to claim 1, wherein   3. The sample hold means includes sample signal generation means for generating a sample signal of the current value based on a combination of drive signals of a plurality of switching elements constituting the inverter main circuit. 3 phase voltage type PWM inverter device. In a three-phase voltage type PWM inverter device having an inverter main circuit using a semiconductor switching element,
DC bus current detection means for detecting a DC bus current of the inverter main circuit;
Peak hold means for peak-holding the current value detected by the DC bus current detection means;
Phase current detection means for detecting a current value held by the peak hold means as a phase current of a specific phase determined by a switching pattern of the semiconductor switching element;
A three-phase voltage type PWM inverter device comprising:   5. The configuration according to claim 4, wherein the resetting of the peak hold means is terminated in the vicinity of the timing at which the intermediate level modulation signal and the PWM carrier signal intersect among the three PWM modulation signals. Phase voltage type PWM inverter device.   6. The three-phase voltage type PWM inverter device according to claim 4, wherein resetting of the peak hold means is started after completion of taking in the current value held by the peak hold means. In a two-phase modulation control type three-phase voltage type PWM inverter device having an inverter main circuit using a semiconductor switching element and switching only two-phase semiconductor switching elements in three phases at a predetermined PWM carrier cycle,
PWM modulation means for modulating the pulse width so that the voltage vector generation period at the center of each PWM period is equal to or greater than a predetermined width in two consecutive PWM periods;
DC bus current detection means for detecting a DC bus current of the inverter main circuit;
Phase current detection means for detecting a current value detected by the DC bus current detection means in a voltage vector generation period at the center of each PWM period as a phase current of a specific phase determined by a switching pattern of the semiconductor switching element;
A three-phase voltage type PWM inverter device comprising:   8. The three-phase according to claim 7, wherein the PWM modulation unit modulates a pulse width so that a phase difference between voltage vectors generated at the center of each of the two consecutive PWM periods becomes 120 degrees. Voltage type PWM inverter device.   The PWM modulation means uses two voltage vectors having a phase difference of 120 degrees and two voltage vectors having a phase difference of 180 degrees with respect to the voltage vector in two consecutive PWM periods, and 9. The three-phase voltage type PWM according to claim 8, wherein two voltage vectors having a phase difference of 60 degrees are generated in the first PWM period, and the remaining two voltage vectors are generated in the second PWM period. Inverter device.   Average value of current value Ia (n) detected during the current PWM period and current value Ia (n-2) detected during the previous PWM period, and current value detected during the previous PWM period The apparatus is configured to calculate at least one of a current amplitude, a current phase, a d-axis current Id on a rotation coordinate axis, and a q-axis current Iq based on Ib (n-1). The three-phase voltage type PWM inverter device according to any one of 7 to 9. In a two-phase modulation control type three-phase voltage type PWM inverter device having an inverter main circuit using a semiconductor switching element and switching only two-phase semiconductor switching elements in three phases at a predetermined PWM carrier cycle,
DC bus current detection means for detecting a DC bus current of the inverter main circuit;
Phase current detection means for detecting the current value detected by the DC bus current detection means as a phase current of a specific phase determined by the switching pattern of the semiconductor switching element at a timing near the peak or valley of the PWM carrier signal;
A three-phase voltage type PWM inverter device comprising:   The command voltage vector is generated in a specific period including two or more PWM carrier periods, and the basic voltage vector component of the command voltage vector is changed in each PWM carrier period in the specific period. 11 is a three-phase voltage type PWM inverter device.   The three-phase voltage type PWM inverter according to claim 12, wherein a zero voltage vector having no magnitude and a single basic voltage vector having a magnitude are generated in each PWM carrier cycle of the specific period. apparatus. The specific period is composed of a first period and a second period each having a 1 PWM carrier period,
The modulation degree of one phase in three phases is approximately 100% in the first period and the second period, and the modulation degree of one phase in the other two phases is approximately 0% in the first period. A modulation degree of one phase in three or three phases is substantially 0% in the first period and the second period, and a modulation degree of one phase in the other two phases is substantially in the first period. The three-phase voltage type PWM inverter device according to claim 12 or 13, characterized in that it is 100%.   15. Each PWM carrier period in the specific period is changed at a peak or valley of a PWM carrier signal, and a single basic voltage vector is used in each PWM carrier period. 3 phase voltage type PWM inverter device.   16. The three-phase voltage type PWM inverter device according to claim 12, wherein control is performed to switch between a period in which normal PWM modulation is performed and the specific period.   In a first state in which each time width of each PWM carrier cycle in which a basic voltage vector having a magnitude is output is a predetermined value or more, a current value is detected in each PWM carrier cycle, and each PWM carrier is The three-phase voltage type PWM inverter device according to any one of claims 1 to 16, wherein detection of a current value is prohibited in a second state in which any time width of the cycle is less than a predetermined value.   Of the phase current value detected in the first state and the q-axis current on the rotational coordinate axis calculated from the rotor position information, the d-axis current, the current phase based on the applied voltage phase of the specific phase, or the current amplitude The three-phase voltage type PWM inverter device according to claim 17, wherein at least one piece of information is stored in a memory. In a three-phase voltage type PWM inverter device having an inverter main circuit using a semiconductor switching element,
DC bus current detection means for detecting a DC bus current in the inverter main circuit;
Six types of basic voltage vectors V1 (1, 0, 0), V2 (1, 1, 0), V3 (0, 1, 0), V4 (0, 1, 1), V5 (0, 0) having magnitudes 0, 1), at least one of V6 (1, 0, 1) and at least one of two types of zero voltage vectors V0 (0, 0, 0), V7 (1, 1, 1) having no magnitude Drive signal generating means for generating a drive signal of the semiconductor switching element by a method of generating a command voltage vector by combining
Phase current detection means for detecting a current value detected by the DC bus current detection means as a phase current of a specific phase determined by a switching pattern of the semiconductor switching element;
With
The drive signal generating means selects the zero voltage vector V7 at substantially the center of each generation period of the odd-numbered basic voltage vectors V1, V3, V5, and the even-numbered basic voltage vectors V2, V4, V6. A three-phase voltage type PWM inverter device configured to select the zero voltage vector V0 in a substantially central portion of each generation period.   20. The three-phase voltage type PWM inverter according to claim 19, wherein the drive signal generating means is configured to use the zero voltage vectors V0 and V7 by switching the electrical angle approximately every 60 degrees. apparatus.   The drive signal generating means selects the zero voltage vector V7 when the odd numbered basic voltage vectors V1, V3, V5 are larger in size than the even numbered basic voltage vectors V2, V4, V6. The zero voltage vector V0 is selected when the basic voltage vectors V2, V4, V6 are larger in size than the odd numbered basic voltage vectors V1, V3, V5. The three-phase voltage type PWM inverter device according to 19 or 20.   The three-phase voltage type PWM inverter device according to any one of claims 19 to 21, wherein the drive signal generating means changes the PWM frequency in accordance with the rotational speed. In a three-phase voltage type PWM inverter device having an inverter main circuit using a semiconductor switching element,
DC bus current detection means for detecting a DC bus current in the inverter main circuit;
Drive signal generating means for generating a drive signal for the semiconductor switching element;
Phase current detection means for detecting a current value detected by the DC bus current detection means as a phase current of a specific phase determined by a switching pattern of the semiconductor switching element;
Current phase / amplitude detection means for calculating a current phase and current amplitude from a phase current value at an arbitrary timing θ1 detected by the phase current detection means and a phase current value at a timing θ1 + Δθ after lapse of Δθ from the θ1. A three-phase voltage type PWM inverter device characterized by that.   24. The three-phase voltage type PWM inverter device according to claim 23, wherein the [Delta] [theta] is set to approximately 60 degrees in electrical angle.

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