JP5067385B2 - AD converter, current detector using AD converter, and digital servo controller using current detector - Google Patents

Description

The present invention relates to an AD converter for converting an analog signal into a digital signal, a current detector for controlling a motor or the like using the AD converter, and a digital servo controller using the current detector.

An AD conversion apparatus including a plurality of AD converters sequentially performs AD conversion one by one, and there is a problem that it takes time to complete all AD conversions. In order to solve this problem, a conventional AD converter starts conversion of a plurality of AD converters all at once, calculates a logical product of a plurality of AD conversion completion signals generated when AD conversion is completed, and performs digital signal processing means. It was generated as an interrupt signal to the (high-order arithmetic unit) (for example, see Patent Document 1).

FIG. 5 is a circuit diagram showing an AD converter in the prior art.
In FIG. 5, the digital signal processing means 1 gives the AD conversion start signal 4 to the AD converters 201, 202,... 20n at time to and starts the AD conversion operation. Thus, the AD conversion completion signals 301, 302,..., 30n output from the AD converters 201, 202,... 20n are input to the AND gate 3 and ANDed. The signal output from the AND gate 3 means that all the AD converters 201, 202,... 20n have completed the conversion operation, and is input to the digital signal processing means 1 as the interrupt signal 2.

FIG. 6 is a timing chart showing the operation of such a conventional AD converter, and any of the AD conversion completion signals 301, 302,..., 30n is in a low level during the period from time ta to tb. , 30n indicate that all AD conversion completion signals 301, 302,..., 30n are at a high level at time tb.

As described above, the conventional AD conversion apparatus reads the AD conversion data of all the AD converters by one interrupt signal, so that the AD conversion data can be efficiently collected.

In addition, as an example of the AD converter, there is an AD converter that uses a ΔΣ AD converter (see, for example, FIG. 4 of Patent Document 2). This ΔΣ-type AD converter is based on the fact that an AD converter composed of a general successive approximation AD converter is susceptible to noise, and a DA converter having the same number of bits as the output bits is provided inside the AD converter. It was a solution to the problem of being expensive because it was built in.

FIG. 7 is a circuit diagram of a conventional ΔΣ AD converter 5.
In FIG. 7, reference numeral 41 denotes a ΔΣ modulator, which receives an analog signal EA, performs ΔΣ modulation, and outputs a code pulse EO. Reference numeral 141 denotes a digital filter which receives the code pulse EO and outputs it as a digital signal. Reference numeral 151 denotes an averaging circuit, which calculates an average value of the digital signal output from the digital filter 141 in a period equal to the period of the PWM carrier, and outputs it as a digital signal ED.
Further, the ΔΣ modulator 41 compares the subtraction circuit 401 for subtracting EA and EO, the integration circuit 411 for integrating the subtraction result, the integration result and the reference level, and the sign pulse EO in synchronization with the clock 421. The comparator circuit 431 that outputs
Even if noise occurs in the analog signal EA, the output of the ΔΣ modulator 41 configured as described above is averaged by the integration circuit 411 and thus does not change rapidly.

As described above, the AD converter using the conventional ΔΣ AD converter 5 can reduce the influence on the digital signal output even when noise is superimposed on the analog signal. In addition, an inexpensive AD converter can be provided by using a ΔΣ AD converter as the AD converter.
Furthermore, an AD conversion device using a ΔΣ AD converter has been applied to a current detector of a digital servo control device (see, for example, FIG. 1 of Patent Document 2). This is because, when an AD converter constituted by a general successive approximation AD converter is applied to a current detector of a digital servo controller, in order to prevent superposition of switching noise of a power element on a digital current detection signal, This solves the problem that it is necessary to sample and hold each current detection signal at the timing when switching is not performed and perform AD conversion, and the problem that the cost of the digital servo controller increases because an expensive AD converter is used. Met.

FIG. 8 is a system configuration diagram of a digital servo control apparatus using a conventional current detector.
In FIG. 8, the motor 11 is a three-phase motor as an example.
First, the current detection means 13 detects two currents of the three phases supplied to the three-phase motor 11 in an analog manner, and outputs a first current detection signal iA1 and a second current detection signal iA2.
The first ΔΣ type AD converter 51 and the second ΔΣ type AD converter 52 receive the first current detection signal iA1 and the second current detection signal iA2, respectively, digitize the first current detection signal iA1 and the second current detection signal iA2, respectively. The current detection signal iD1 and the second digital current detection signal iD2 are output.
The position detection means 12 detects the relative position between the rotor and the stator of the electric motor 11 and outputs a position detection signal S1.
The digital signal processing means 9 inputs the first digital current detection signal iD1, the second digital current detection signal iD2, the position detection signal S1 and the digital command signal C1, and performs arithmetic processing on these to thereby generate the first PWM command. The signal P1, the second PWM command signal P2, the third PWM command signal P3, the fourth PWM command signal P4, the fifth PWM command signal P5, and the sixth PWM command signal P6 are output. The digital signal processing means 9 is constituted by a circuit including a current amplifier, a speed amplifier, a position amplifier and a PWM generation circuit by a digital circuit or software using a DSP or a microcomputer.
The power conversion means 10 is composed of six sets of power elements and freewheeling diodes in a three-phase bridge configuration, and the first, second, third, fourth, fifth and sixth PWM command signals P1, The motor applied voltage is PWM controlled according to P2, P3, P4, P5 and P6.

The operation of a digital servo control device using a conventional current detector will be described below.
The first ΔΣ type AD converter 51 and the second ΔΣ type AD converter 52 are constituted by a ΔΣ type AD converter 5 and digitize the first and second current detection signals iA1 and iA2 by AD conversion, respectively. To output first and second digital current detection signals iD1 and iD2. Digital control of the motor 11 is performed by the iD1, iD2, the position detection signal S1, and the digital command signal C1.

FIG. 9 is a timing chart showing the operation of the conventional current detector. The manner in which the ΔΣ AD converter 5 used in the first and second ΔΣ AD converters 51 and 52 outputs a digital current detection signal will be described with reference to FIG.
The first PWM command signal P1 shown in FIG. 9 is a PWM signal generated for each PWM carrier, and the current is the first current detection signal iA1.
The ΔΣ AD converter 5 samples a digital signal obtained by digitizing iA1 a plurality of times during a period equal to the period of the PWM carrier. FIG. 9 shows a case where sampling is performed four times in a period equal to the period of the PWM carrier as an example.
That is, the digitized digital signal of iA1 is sampled four times, and the average value of the four samplings is obtained by the averaging circuit 151 in FIG. 7, and this is used as the digital current detection signal iD1.

As described above, the digital servo control device using the conventional current detector samples the digitized result of the current detection signal a plurality of times during the period when the ΔΣ type AD converter is equal to the PWM carrier cycle, and calculates the average value thereof. By adopting a configuration for outputting as a digital current detection signal, the average value of the drive current supplied to the electric motor was obtained, and the controllability of the electric motor was improved.

JP 59-2111132 (3rd page, FIG. 4, FIG. 5) Japanese Patent No. 3412434 (page 6, FIG. 1, FIG. 4, page 7, FIG. 5)

However, in general, the ΔΣ type AD converter is a method in which sampling is performed by a 1-bit AD converter and AD conversion data is obtained by an averaging process. Therefore, the AD conversion data includes a quantization error. It is known that the smaller the number of samplings, the worse the AD conversion accuracy.
A conventional AD converter using a ΔΣ AD converter has a problem that the number of samplings within a certain time is limited, and the AD conversion accuracy of the digital signal ED with respect to the analog signal EA is poor. On the other hand, when the number of times of sampling is increased in order to increase AD conversion accuracy, there is a problem that AD conversion time increases.
Also, since the digital servo control device using the conventional current detector has to complete the AD conversion and update the digital signal ED within the PWM carrier cycle, the number of times of sampling is limited. There was a problem of poor accuracy.
Furthermore, the conversion time of each ΔΣ AD converter varies, and in an AD converter using a plurality of ΔΣ AD converters, the logical product of AD conversion completion signals is simply calculated as in the conventional AD converter. In some cases, it is not possible to cope with the problem by simply taking it, and there is a problem in that it is necessary to determine which AD converter has a long conversion time at the time of adjustment, and extra work is necessary to adjust accordingly.

The present invention has been made in view of such problems, and provides a highly accurate AD converter, a current detector using the AD converter, and a digital servo control device using the current detector. With the goal.

In order to solve the above problem, the present invention is configured as follows.
The present invention includes a plurality of ΔΣ AD converters 511, 512, and 51n each of which receives an analog signal, starts AD conversion by an AD conversion start signal, and outputs an AD conversion completion signal by the end of AD conversion, A logic circuit that generates one interrupt signal 7 from AD conversion completion signals 71, 72, and 7n output from a plurality of ΔΣ AD converters, and a plurality of ΔΣ AD converters 511, 11 by receiving the interrupt signal 7 In the AD conversion apparatus including the digital signal processing means 21 that reads the AD conversion data 61, 62, and 6n of 512 and 51n and performs arithmetic processing, the ΔΣ AD converters 511, 512, and 51n include the ΔΣ modulator 41 and the digital signal processing unit 21, respectively. A plurality of AD conversion data generation units 181, 182, 18 m connected in parallel to the output EO of the ΔΣ modulator 41, and the digital signal processing unit 21 based on a timing generation circuit 20 that starts an operation by a start trigger 23 output from 21, a plurality of AD conversion start signals 121, 122, 12 m output from the timing generation circuit 20 with a time difference, and the AD conversion start signal Based on the plurality of AD conversion data 161, 162, 16 m output from the AD conversion data generation units 181, 182, 18 m and the channel selection signal 91 output from the timing generation circuit 20, the plurality of AD conversion data 161, An AD conversion data selector 241 for selecting one AD conversion data 61 from 162, 16m;
The plurality of AD conversion completion signals 171 and 172 based on the plurality of AD conversion completion signals 171, 172 and 17 m output from the plurality of AD conversion data generation units and the channel selection signal 91 output from the timing generation circuit 20. , 17m, an AD conversion completion signal selector 251 for selecting one AD conversion completion signal 71, an AD conversion time measurement counter 221 that starts counting by the input of the AD conversion start signal 121, and AD conversion by the AD conversion completion signal 171 An AD conversion time holding unit 231 for holding time, and the logic circuit compares a plurality of AD conversion times 81 output from the plurality of ΔΣ AD converters 511, 512, and 51n, and the AD conversion time is the longest. A comparator 22 for selecting a long ΔΣ AD converter;
Based on the interrupt selection signal 8 output from the comparator 22, one interrupt signal is selected from the plurality of AD conversion completion signals 71, 72, 77n output from the plurality of ΔΣ AD converters 511, 512, 51m. It is characterized by comprising an interrupt signal selector 19.
Further, according to the present invention, the AD conversion data generation unit includes a digital filter 141 and an averaging circuit 151. The digital filter 141 samples the output EO of the ΔΣ modulator 41 a plurality of times, and the averaging circuit 151 A value is output.
In the present invention, the ΔΣ modulator 41 compares the subtraction circuit 401 that subtracts the analog signal 101 and the EO, the integration circuit 411 that integrates the subtraction result, the comparison result with the reference level, The comparison circuit 431 is configured to output a code pulse EO in synchronization with 421.
The present invention also includes a digital signal processing means 9 for detecting a current supplied to the motor 11 and performing arithmetic processing based on the detected current signal and the digital command signal C1, and applying the electric motor based on the arithmetic processing result of the digital signal processing means. In a current detector in a digital servo control device provided with power conversion means 10 for PWM control of voltage,
The current detector detects the current supplied to the motor 11 in an analog manner and outputs current detection signals iA1 and iA2, and digitizes the current detection signal to generate digital current detection signals iD1 and iD2. consists AD converter for outputting, the AD converter is characterized in that it has been constructed from the AD converter described above.
The present invention also includes the electric motor 11, position detecting means for detecting the relative position of the rotor and stator of the electric motor, a current detector for detecting the current supplied to the electric motor, and a detected current signal. In the digital servo control device comprising the digital signal processing means 9 for performing arithmetic processing based on the digital command signal C1, and the power conversion means 10 for performing PWM control of the motor applied voltage based on the arithmetic processing result of the digital signal processing means, The current detector includes the above-described current detector.

According to the present invention, the number of digital signal samplings can be increased, and the AD conversion accuracy can be improved. Further, it is not necessary to perform extra work such as selecting an AD converter having the longest AD conversion time during adjustment.

In addition, according to the present invention, the number of digital signal samplings can be increased, and AD conversion accuracy can be improved.
In addition, according to the present invention, since a highly accurate AD converter is used, current detection can be performed with high accuracy.
In addition, according to the present invention, current detection can be performed with high accuracy, so that highly accurate digital servo control can be performed.

1 is a circuit diagram of an AD conversion apparatus according to a first embodiment of the present invention. Timing chart showing operation in the first embodiment The system block diagram of the digital servo control apparatus using the current detector which shows 2nd Example of this invention Timing chart showing operation in the second embodiment Circuit diagram of conventional AD converter Timing diagram showing the operation of a conventional AD converter Circuit diagram of a conventional ΔΣ AD converter System configuration diagram of a digital servo controller using a conventional current detector Timing diagram showing the operation of a conventional current detector

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of an AD conversion apparatus showing a first embodiment of the present invention.
In FIG. 1, reference numeral 511 denotes a ΔΣ AD converter, which receives an analog signal 101, performs ΔΣ modulation by a ΔΣ modulator 41, and outputs a code pulse EO. The ΔΣ modulator 41 compares the subtraction circuit 401 that subtracts the analog signal 101 and EO, the integration circuit 411 that integrates the subtraction result, the integration result and the reference level, and the code is synchronized with the clock 421. The comparator 431 outputs a pulse EO.
Reference numeral 141 denotes a digital filter which inputs a code pulse EO and outputs it as a digital signal. Reference numeral 151 denotes an averaging circuit, which calculates an average value of a digital signal output from the digital filter 141 in a period from input of the AD conversion start signal 121 to completion of AD conversion and output of the AD conversion completion signal 171. , And output as AD conversion data 161. Reference numeral 181 denotes an AD conversion data generation unit which includes a digital filter 141 and an averaging circuit 151.
Further, a circuit having the same configuration as the AD conversion data generation unit 181 is connected to the output of the comparison circuit 431 in parallel with a plurality of channels 181, 182,..., 18 m, and the AD conversion data generation unit 182 receives the AD conversion start signal 122, the AD conversion completion signal 172 and the AD conversion data 162 are output, and the AD conversion data generation unit 18m receives the AD conversion start signal 12m and outputs the AD conversion completion signal 17m and the AD conversion data 16m. Reference numeral 20 denotes a timing generation circuit which starts its operation in response to a start trigger 23 input from the digital signal processing means 21 and outputs AD conversion start signals 121, 122,..., 12m and a channel selection signal 91. Reference numeral 241 denotes an AD conversion data selector which selects AD conversion data 161 when the channel selection signal 91 is 1, AD conversion data 162 when the channel selection signal 91 is 2, AD conversion data 16m when. Is output. Reference numeral 251 denotes an AD conversion completion signal selector which selects the AD conversion completion signal 171 when the channel selection signal 91 is 1, selects the AD conversion completion signal 172 when the channel selection signal 91 is 2, selects the AD conversion completion signal 17m when. An AD conversion completion signal 71 is output. Reference numeral 221 denotes an AD conversion time measurement counter which is once cleared to 0 value at the rising edge of the AD conversion start signal 121, then counted up by the system clock CP, and is sent to the AD conversion time holding unit 231 at the rising edge of the AD conversion completion signal 171. The counter value is held and AD conversion time 81 is output.

Similarly, a plurality of circuits having the same configuration as the ΔΣ AD converter 511 are arranged in parallel with 511, 512,..., 51n, and the ΔΣ AD converter 512 inputs the analog signal 102 and the start trigger 23, The AD conversion data 62, the AD conversion completion signal 72, and the AD conversion time 82 are output, the ΔΣ AD converter 51n receives the analog signal 10n and the start trigger 23, and the AD conversion data 6n, the AD conversion completion signal 7n, and the AD conversion Output time 8n.
A comparator 22 compares the AD conversion times 81, 82,..., 8n, determines the one with the latest AD conversion time, and outputs the interrupt selection signal 8. An interrupt signal selector 19 selects an AD conversion completion signal 71 when the interrupt signal 8 is 1, an AD conversion completion signal 72 when the interrupt signal 8 is 2, an AD conversion completion signal 7n when the interrupt signal 8 is n, and an interrupt signal 7 Is output. Upon receiving the falling edge of the interrupt signal 7, the digital signal processing means 21 reads the AD conversion data 61, 62,..., 6n and performs arithmetic processing.

The difference between the present invention and the prior art is that the ΔΣ AD converter 511 includes a timing generation circuit 20, an AD conversion time measurement counter 221, an AD conversion time holding unit 231, an AD conversion data selector 241, and an AD conversion completion signal selector 251. , 18m in which the AD conversion data generation unit is parallelized in a plurality of channels, and a logic circuit that generates an interrupt signal in an AD conversion device including a plurality of ΔΣ AD converters This is a part composed of the device 22 and the interrupt signal selector 19.

Next, the operation of the present invention will be described.
FIG. 2 is a timing chart showing the operation in the first embodiment.
In FIG. 2, AD conversion of the first channel in the ΔΣ AD converter 511 starts at the rising edge of the AD conversion start signal 121. Similarly, AD conversion start signals 122,..., 12m are generated with a certain time difference from the AD conversion start signal 121, and AD conversion of the second channel,.
When AD conversion of the first channel is completed, the channel selection signal 91 selects the first channel, the AD conversion data 161 is output to the AD conversion data 61, and the AD conversion completion signal 171 is output to the AD conversion completion signal 71. .
Similarly, when AD conversion of the second channel,..., M channel is completed, the channel selection signal 91 selects the second channel,..., M channel, and the AD conversion data 162,. .., 16m is output to AD conversion data 61. AD conversion completion signals 172,..., 17m are output to AD conversion completion signal 71. The AD conversion time 81 is held at the rising edge of the AD conversion completion signal 171.

Similarly, AD conversion data 62,..., 6n and AD conversion completion signals 72,..., 7n and AD conversion times 82,. Is output. Here, the ΔΣ type AD converters 511, 512,..., 51n cause a considerable difference in AD conversion time due to manufacturing variations, but the latest AD conversion completion signal is selected as the interrupt signal 7 by the interrupt selection signal 8. Therefore, when all AD conversions are completed, the digital signal processing means 21 can be interrupted to read the AD conversion data 61, 62,.
Also, as shown in the figure, since AD conversion only needs to be completed once per channel while m interrupts occur, the AD conversion time per channel can be increased, and the number of samplings is increased accordingly. It becomes possible.

As described above, since the AD conversion data generation units 181, 182,..., 18m are configured in parallel with a plurality of channels, the number of samplings can be increased, and the AD conversion accuracy can be improved.

FIG. 3 is a system configuration diagram of a digital servo control device using a current detector showing a second embodiment of the present invention.
In FIG. 3, the electric motor 11 will be described below using a three-phase electric motor as an example.
First, the current detection means 13 detects two currents of the three phases supplied to the three-phase motor 11 in an analog manner, and outputs a first current detection signal iA1 and a second current detection signal iA2.
The first ΔΣ AD converter 511 and the second ΔΣ AD converter 512 receive the first current detection signal iA1 and the second current detection signal iA2, respectively, digitize them, and perform the first digital The current detection signal iD1 and the second digital current detection signal iD2 are output.
The position detection means 12 detects the relative position between the rotor and the stator of the electric motor 11 and outputs a position detection signal S1.
Reference numeral 22 denotes a comparator that compares the AD conversion times 81 and 82 to determine which AD conversion time is slow, and outputs an interrupt selection signal 8. An interrupt signal selector 19 selects the AD conversion completion signal 71 when the interrupt selection signal 8 is 1, selects the AD conversion completion signal 72 when the interrupt selection signal 8 is 2, and outputs an interrupt signal 7. The digital signal processing means 9 inputs the first digital current detection signal iD1, the second digital current detection signal iD2, the position detection signal S1 and the digital command signal C1, and calculates them when the falling edge of the interrupt signal 7 is received. By processing, the first PWM command signal P1, the second PWM command signal P2, the third PWM command signal P3, the fourth PWM command signal P4, the fifth PWM command signal P5, and the sixth PWM command signal. P6 is output. The digital signal processing means 9 is constituted by a circuit including a current amplifier, a speed amplifier, a position amplifier, and a PWM generation circuit by a digital circuit or software using a DSP, a microcomputer, or the like.
The power conversion means 10 is composed of six sets of power elements and freewheeling diodes in a three-phase bridge configuration, and the first, second, third, fourth, fifth and sixth PWM command signals P1, The motor applied voltage is PWM controlled according to P2, P3, P4, P5 and P6.
The present invention is different from the prior art in that it includes a timing generation circuit 20, an AD conversion time measurement counter 221, an AD conversion time holding unit 231, an AD conversion data selector 241, and an AD conversion completion signal selector 251, and the AD conversion data generation unit A portion to which ΔΣ AD converters 181, 182,.
A logic circuit that generates an interrupt signal is a part constituted by a comparator 22 and an interrupt signal selector 19.

Next, the operation of the present invention will be described.
FIG. 4 is a timing chart showing the operation in the second embodiment.
In FIG. 4, the first ΔΣ type AD converter 511 and the second ΔΣ type AD converter 512 are described below with an example in which the AD conversion data generation units 181, 182, 183, and 184 are parallelized in four channels. Do.
At the rising edge of the AD conversion start signal 121, AD conversion of the first channel in the ΔΣ AD converter 511 starts. Similarly, AD conversion start signals 122,..., 124 are generated with a certain time difference from the AD conversion start signal 121, and AD conversion of the second channel,. When the AD conversion time for the first channel is completed by predicting the AD conversion time in advance and switching the channel according to the set value, the channel selection signal 91 selects the first channel, and the AD conversion data 161 Is converted to AD conversion data 61 and AD conversion completion signal 171 is output to AD conversion completion signal 71.
Similarly, when the AD conversion of the second channel,..., The fourth channel is completed, the channel selection signal 91 selects the second channel,..., The fourth channel, and the AD conversion data 162,. , 164 is output to the AD conversion data 61, and AD conversion completion signals 172,... 174 are output to the AD conversion completion signal 71. The AD conversion time 81 is held at the rising edge of the AD conversion completion signal 171.

Similarly, the AD conversion data 62, the AD conversion completion signal 72, and the AD conversion time 82 are output from the ΔΣ AD converter 512. Here, the ΔΣ type AD converters 511 and 512 cause a considerable difference in AD conversion time due to manufacturing variations. However, since the later AD conversion completion signal is selected as the interrupt signal 7 by the interrupt selection signal 8, When the AD conversion is completed, the digital signal processing means 9 can be interrupted to read the digital current detection signals iD1, iD2.
The first PWM command signal P1 is a PWM signal generated for each PWM carrier, and the current is the first current detection signal iA1.
The ΔΣ AD converter 511 samples a digital signal obtained by digitizing iA1 a plurality of times in a period obtained by multiplying the period of the PWM carrier by the number of channels of the AD data generation unit. In FIG. 4, as an example, a case where sampling is performed 16 times in a period four times the period of the PWM carrier is shown.
That is, the digitized digital signal of iA1 is sampled 16 times, and the averaging circuit 151 obtains the average value of the 16 samplings, and this is used as the digital current detection signal iD1.

As described above, since the AD conversion data generation unit is configured in parallel with four channels, the number of samplings can be increased four times, and the current detection accuracy can be improved.

1, 9, 21 Digital signal processing means 2, 7 Interrupt signal 3 AND gate 4, 121, 122,..., 12m AD conversion start signal 5, 51, 52, 511, 512, 513 ΔΣ type AD converter 8 Interrupt Selection signal 10 Power conversion means 11 Electric motor 12 Position detection means 13 Current detection means 19 Interrupt signal selector 20 Timing generation circuit 22 Comparator 23 Trigger signal 41 ΔΣ modulators 61, 62,..., 6n, 161, 162,. ..., 16m AD conversion data 71, 72, ..., 7n AD conversion completion signals 81, 82, ..., 8n AD conversion time 91 Channel selection signals 101, 102, ..., 10n Analog signal 141 Digital filter 151 Averaging circuits 171, 172,..., 17m, 301, 302,. 81, 182,..., 18m AD conversion data generation unit 201, 202,..., 20n AD converter 221 AD conversion time measurement counter 231 AD conversion time holding unit 241 AD conversion data selector 251 AD conversion completion signal selector 401 Subtraction circuit 411 Integration circuit 421 Clock 431 Comparison circuit

Claims (5)

When an analog signal is inputted, the AD conversion starts when accepting the AD conversion start signal, terminates Then a plurality of ΔΣ-type AD converter output the AD conversion completion signal, the ΔΣ-type AD converter of the multiple AD conversion a logic circuit for generating the AD conversion complete signal or al No. one interrupt signals outputted respectively from the vessel, the AD conversion data of the interrupt by Rifuku number of the reception of the signal the ΔΣ-type AD converter is generated in AD converter that includes a digital signal processing hand stage for performing write Nde processing read data,
The ΔΣ AD converter is
A plurality of AD conversion data generation unit that will be connected in parallel to the output side of the ΔΣ modulator,
Outputs with a time difference of the AD conversion start signal to the plurality of AD conversion data generation unit, a timing generation circuits for outputting sequentially indicate channel selection signal any one of a plurality of the AD conversion data generation unit And
And the AD conversion data selector to be outputted to the digital signal processing unit selects the AD conversion data generated by the AD conversion data generation unit, wherein the channel selection signal is indicated,
AD conversion completion signal selector to be output to the logic circuit selects the AD conversion completion signal outputted by the AD conversion data generation unit, wherein the channel selection signal is indicated,
An AD conversion time which is a time from reception of the AD conversion start signal output to the predetermined AD conversion data generation unit by the timing generation circuit until reception of the AD conversion completion signal output from the AD conversion data generation unit An AD conversion time holding unit for holding
Said logic circuit,
A comparator for the AD conversion time selects the longest the ΔΣ-type AD converter by the AD conversion time holding unit of the ΔΣ-type AD converter of multiple compares between the time the AD conversion for holding respectively,
And the interrupt signal selector for selecting the AD conversion completion signal corresponding to the ΔΣ-type AD converter which is selected by said comparator as said interrupt signal
AD converter, characterized in that it comprises a. The AD conversion data generation unit,
A digital filter for a plurality of times sampling the output of the previous SL ΔΣ modulator,
An averaging circuit for outputting an average value of a plurality of sampling data output from the digital filter;
AD converter according to claim 1, characterized in that it comprises a. The ΔΣ modulator is
A subtraction circuitry for performing a subtraction between the output of the ΔΣ modulator and the analog signal,
A path integration times for integrating the subtraction result by the subtraction circuit,
Comparing with the reference-level integration result by the integrating circuit, a comparison circuitry for outputting a code pulse in synchronism with the clock
AD converter according to claim 1 or 2, characterized in that it comprises a. A digital signal processing hand stage for performing arithmetic processing based on the detection current signal and the digital command signal which detects the current supplied to the motor, applied electric motor based on the operation result of the digital signal processing means a current detector in the digital servo control device and a power conversion means to the PWM control voltage,
A current detecting means to output a current detection signal current supplied prior Symbol motor by analog detectable,
An AD converter according to claim 1, 2 or 3 outputs the digital current detection signal and digitizes the current detection signal
Current detector, characterized in that it comprises a. An electric motor, a position detecting means for detecting the relative position between the rotor and the stator of the motor, a current detector for detecting a current supplied to the electric motor, and the detected current signal and the digital command signal in digital servo control device including a digital signal processing hand stage for performing arithmetic processing have based, and a power conversion means to PWM control the motor applied voltage based on the operation result of the digital signal processing means,
The current detector is
5. A digital servo control device , comprising the current detector according to claim 4 .

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