JP5052807B2 - Semiconductor device and power conversion device - Google Patents

Description

The present invention relates to a power conversion apparatus to be used consists of a semiconductor including a nitride-based compound semiconductor, a semi-conductor device and the semiconductor device including a field effect transistor and a diode.

  A switching element is used in an inverter circuit or a converter circuit constituting a power conversion device such as an inverter that converts direct current into alternating current or a converter that converts alternating current into direct current. The switching element includes a semiconductor device such as a field effect transistor or an IGBT (Insulated Gate Bipolar Transistor).

FIG. 7 shows a circuit diagram of an inverter as the power converter 300. The power converter 300 includes an AC power source 400, a rectifier circuit 500 that rectifies the AC supplied from the AC power source 400 into a DC, and an inverter circuit 600 that converts the DC from the rectifier circuit 500 into an AC.

The inverter circuit 600 supplies the converted AC power to the load M. A power field effect transistor 100 is used as a switching element of the inverter circuit 600, and a diode 200 is used as a protection element thereof. That is, when a reverse surge is applied between the source and the drain of the field effect transistor 100 with the field effect transistor 100 turned off, a surge current flows between the drain and the gate, and the electrode constituting the gate is destroyed. Is done. Therefore, the diode 200 is connected as a protective element in parallel to the source and drain of the field effect transistor 100, so that the surge current applied to the transistor can be bypassed and released to the diode 200.

In particular, nitride-based compound semiconductor materials such as GaN, InGaN, AlGaN, and AlInGaN have large band gap energy, high heat resistance, and excellent high-temperature operation. Therefore, field effect transistors using these materials are shown in FIG. It may be used as the field effect transistor 100 of the power converter 300 shown in FIG. This is because it is possible to lower the cost for the cooling of the element as compared with the element (device), such as Si which can not endure the high temperature operation. In addition, nitride-based compound semiconductor materials are advantageous in terms of breakdown voltage because of their large band gap energy. Furthermore, by using this feature, a diode using this nitride-based compound semiconductor material can ensure a high breakdown voltage, and therefore can be used as the diode 200 of the power conversion device 300 shown in FIG.

For example, in FIG. 8 (a), the as switching elements of the power converter, using a field effect transistor 100 constituted by using a nitride-based compound semiconductor, a field effect transistor 100, a nitride compound semiconductor as a protection element it is a circuitry diagram Schottky diode 200 that is built using. As shown in FIG. 8A, a Schottky diode 200 configured by contact between a nitride compound semiconductor and a metal electrode is connected in parallel with a field effect transistor 100 configured using a nitride compound semiconductor. .

  As shown in FIG. 8B, such a protective element is a semiconductor in which a nitride compound semiconductor field effect transistor 100 and a nitride compound semiconductor Schottky diode 200 are integrated on the same substrate. Device 700 is provided. For example, a GaN buffer layer 202, an undoped GaN layer 203, and an undoped AlGaN layer 204 are sequentially stacked on the sapphire substrate 201. Further, two n-type GaN layers 206 are formed on the GaN layer 203 so as to be connected to the heterojunction between the GaN layer 203 and the AlGaN layer 204.

Furthermore, an electrode (source / cathode combined electrode) 207a that is in ohmic contact with each other on the two n-type GaN layers 206 and serves as both the source electrode of the field effect transistor 100 and the cathode electrode of the Schottky diode 200, A drain electrode 207b of the transistor 100 is formed. A gate electrode 208a of the field effect transistor 100 is formed on the AlGaN layer 204 sandwiched between the two n-type GaN layers 206 in Schottky contact. In addition, an anode electrode 208b is formed in Schottky contact with the AlGaN layer 204 on the opposite side of the gate electrode 208a with the source / cathode combined electrode 207a interposed therebetween.

  A semiconductor device 700 shown in FIG. 8B is obtained by integrating a nitride compound semiconductor field effect transistor 100 as a switching element and a nitride compound semiconductor Schottky diode 200 as a protective element on the same substrate. (Patent Document 1).

  In addition, as a semiconductor device in which a field effect transistor and a diode as a protection element thereof are integrated on the same substrate, there is a semiconductor device described in Patent Document 2. The semiconductor device described in Patent Document 2 also includes a Schottky diode region adjacent to a region where a field effect transistor is formed.

Japanese Patent Laid-Open No. 2003-229566 JP 09-55507 A

  In a conventional semiconductor device, a field effect transistor and a diode as a protection element thereof are formed on the same surface side of the same substrate. In particular, if a large number of field effect transistors and diodes are integrated in order to cope with high power, the substrate area increases.

  Therefore, it can be considered that a current flowing as electric power flows in the vertical direction of the substrate as in the case of an IGBT so as not to increase the substrate area. For example, as described in JP-A-2002-016262, a source electrode is formed on an upper part of a semiconductor multilayer film formed on a conductive semiconductor substrate, and a drain electrode is formed on the lower part of the semiconductor multilayer film. The formed vertical field effect transistor can be given as an example.

  However, when the nitride-based compound semiconductor layer is formed on the substrate, a number of threading dislocations are generated in the vertical direction in the formed semiconductor layer. Therefore, in a field effect transistor having such a configuration, when a current that flows as power flows in the vertical direction of the substrate, the current leaks to threading dislocations, causing power loss. In addition, due to such power loss, when such a field effect transistor is used as a switching element of a power conversion device, there is a risk of reducing the conversion efficiency of the power conversion device.

  An object of the present invention is to realize a semiconductor device with little power loss without causing an increase in substrate area. Another object of the present invention is to realize a power conversion device that uses a semiconductor device with low power loss as a switching element and does not cause a decrease in conversion efficiency.

According to the present invention, there is provided a semiconductor device having a field effect transistor and a diode, and a semiconductor substrate having conductivity, and at least one buffer layer constituting the field effect transistor on one surface of the semiconductor substrate. A laminated semiconductor layer obtained by laminating a nitride compound semiconductor layer functioning as at least one nitride compound semiconductor layer, and
A gate electrode of the field effect transistor is formed on the nitride-based compound semiconductor layer on the surface of the stacked semiconductor layer;
First and second electrodes of the field effect transistor are formed on the nitride-based compound semiconductor layer,
A nitride-based compound semiconductor functioning as a buffer layer constituting the laminated conductor layer in contact with the semiconductor substrate, or a hole reaching the semiconductor substrate through the laminated semiconductor layer in a direction perpendicular to the surface of the substrate hole is formed to penetrate the laminated semiconductor layer to layer,
The first electrode of the diode is embedded to the bottom of the hole;
One electrode of the first and second electrodes of the field effect transistor and the first electrode of the diode buried up to the bottom of the hole are formed by a common electrode,
A second electrode of the diode is formed on the other surface of the substrate or on a semiconductor layer formed on the other surface of the substrate;
A semiconductor device is provided.

Preferably, the first electrode or the second electrode of the diode is a Schottky electrode, the other electrode is an ohmic electrode, and the gate electrode of the field effect transistor is a Schottky type or MIS type electrode. .

  More preferably, the Schottky electrode is formed through a nitride compound semiconductor layer as a barrier adjustment layer that changes the height of the Schottky barrier.

  More preferably, a high-resistance nitride-based compound semiconductor layer is formed between the first surface side of the substrate and the semiconductor layer constituting the stacked semiconductor layer.

Preferably, the on-voltage of the diode is lower than the gate breakdown voltage between the gate and drain of the field-effect transistor when the field-effect transistor is off, or the breakdown voltage of the diode is the field-effect transistor Is lower than the breakdown voltage between the source and drain of the field effect transistor in the off state.

Preferably, the conductive semiconductor substrate is an Al _x Ga _1-x N (0 ≦ x ≦ 1) substrate, a SiC substrate, or a Si substrate.

  Moreover, this invention is a power converter device which has a power converter circuit which uses the field effect transistor of the semiconductor device as described above as a switching element.

  Preferably, the power conversion circuit is an inverter circuit or a converter circuit.

  In the semiconductor device of the present invention, the substrate area is not increased and the power loss is small. Moreover, the power converter device using the semiconductor device of this invention has high conversion efficiency.

  FIG. 1 shows a circuit diagram of an inverter as the power converter 3 of the present invention. The power conversion device 3 includes an AC power supply 4, a rectifier circuit 5 that rectifies the alternating current supplied from the AC power supply 4 into direct current, and an inverter circuit 6 that converts the direct current from the rectifier circuit into alternating current.

  The inverter circuit 6 supplies the converted AC power to the load M. A power field effect transistor 1 is used as a switching element of the inverter circuit 6 and a diode 2 is used as a protection element thereof. The source and drain of each field effect transistor 1 constituting the inverter circuit 6 are connected in common by the anode and cathode of the diode 2, respectively. In addition, the power converter device 3 can use not only the inverter circuit 6 that converts direct current into alternating current but also a converter circuit that converts alternating current into direct current.

2A and 2B show a semiconductor device 7 according to an embodiment of the present invention, where FIG. 2A is a circuit diagram and FIG. 2B is a schematic cross-sectional view. The semiconductor device 7 is used as a switching element constituting the power conversion device 3 shown in FIG.

  As shown in FIG. 2A, the semiconductor device 7 has a field effect transistor 1 and a diode 2 as its protection element connected in parallel. The source S of the field effect transistor 1 is connected to the anode A of the diode 2. The drain D is connected in common with the cathode C.

As shown in FIG. 2B, in the semiconductor device 7, the field effect transistor 1 and the diode 2 are formed on a single semiconductor substrate 21 having conductivity.
On the surface of the substrate 21, a buffer layer 22 made of a nitride compound semiconductor, a first nitride compound semiconductor layer 23, and a second nitride compound semiconductor layer 24 are sequentially stacked.
In addition, a hole 8 is formed in the laminated nitride compound semiconductor layer. The hole 8 penetrates the stacked nitride compound semiconductor layers 22 , 23 , 24 and reaches the substrate 21.

  In order to form the field effect transistor 1 on the substrate 21, for example, the second nitride compound semiconductor layer 24 among the stacked nitride compound semiconductor layers 22, 23, and 24 is used as the channel layer of the field effect transistor 1. And Here, the laminated nitride compound semiconductor layers 22, 23, and 24 are not necessarily all nitride compound semiconductor layers, and at least one of these layers is a nitride compound semiconductor layer. Any stacked semiconductor layer containing any of the above may be used.

  The following example can be considered as a case where at least one of the laminated nitride compound semiconductor layers 22, 23, 24 includes a nitride compound semiconductor layer.

  For example, if the second nitride-based compound semiconductor layer 24 is made of AlGaN and the first nitride-based compound semiconductor layer 23 is made of high-resistance GaN, a field effect using two-dimensional electrons generated at the interface between the two layers as carriers. The transistor 1 can be formed.

Further, if the second nitride compound semiconductor layer 24 is a GaN layer to which a donor impurity such as Si is added and the first nitride compound semiconductor 23 is a high resistance GaN layer, the second nitride system is obtained. The field effect transistor 1 using electrons in the compound semiconductor layer 24 as carriers can be formed.
The concentration of these carriers can be controlled by the electric field effect applied to the gate electrode G disposed between the source electrode S and the drain electrode D. As the gate electrode G, a Schottky type or MIS type electrode can be used.

  Further, when the nitride-based compound semiconductor layer 23 is a high-resistance layer, the magnitude of the on-voltage of the electric field transistor can be controlled by the acceptor doping amount of the layer. A GaN-based field transistor generally has a normally-on type that is turned on when the gate voltage is 0 V or higher and is turned off when the gate voltage is about minus 5 V. However, by adjusting the acceptor amount of the nitride-based compound semiconductor layer 23, It is also possible to use a normally-off type having several volts or more and an off-voltage of 0V. However, in the normally-off type, it is necessary to incorporate a recess or ion implantation structure for reducing parasitic resistance such as source resistance, but since it is a well-known technique for those skilled in the art, it will not be described here.

  As described above, here, the first nitride-based compound semiconductor layer 23 is a stacked layer for supplying or generating carriers for forming a channel of the field effect transistor, and is configured by a plurality of stacked layers having different doping and composition. May be. The second nitride-based compound semiconductor layer 24 is a high breakdown voltage, high-resistance stack for obtaining sufficient insulation when the field-effect transistor 1 is in an off state, and the first nitride-based compound semiconductor layer 23. Similarly, a plurality of laminated layers having different purity and composition may be used.

  On the other hand, the buffer layer 22 is disposed on the substrate 21 to obtain a high-quality first stack, and a nitride-based compound semiconductor layer formed at a relatively low temperature is often used. However, this layer may be omitted if the quality of the first laminate is obtained. For example, it is conceivable to continuously change the film formation conditions of the first stack, or to use a stacked film other than the nitride-based compound semiconductor. Furthermore, a layer for exhibiting the characteristics of the diode described later can be formed below the buffer layer with the same material as the substrate or other materials.

  Then, a set of contact layers 9 is formed on the second nitride-based compound semiconductor layer 24 for each field effect transistor 1 in order to extract current flowing in the channel layer. Further, instead of forming the contact layer 9, a current flowing in the channel layer can be taken out by performing high concentration doping in a region where the contact layer 9 is to be formed by ion implantation.

  A gate electrode G is provided on the front side of the second nitride-based compound semiconductor layer 24 with the pair of contact layers 9 interposed therebetween, a source electrode S and a drain electrode D are provided on the set of contact layers 9, and an electric field An operation as an effect transistor is made possible.

In order to form the diode 2 on the substrate 21, a set of electrodes is required. Therefore, in the semiconductor device 7 according to the embodiment of the present invention, one electrode is formed at the bottom of the hole 8 formed so as to penetrate to the substrate 21, and the other electrode is formed on the back side of the substrate 21. Here, since the substrate 21 is a conductive semiconductor substrate, the electrode formed can be a Schottky electrode or an ohmic electrode by arbitrarily selecting the material of the electrode. When the formed electrode becomes a Schottky electrode, the diode 2 formed on the substrate 21 becomes a Schottky diode, and high speed operation is possible.

In the diode 2 of the semiconductor device 7 shown in FIG. 2B, the electrode formed at the bottom of the hole 8 formed so as to penetrate to the substrate 21 is used as the Schottky electrode and serves as the anode electrode A. In addition, an electrode formed on the back side of the substrate 21 is an ohmic electrode and a cathode electrode C. Then, the drain electrode D of the field effect transistor 1 of the semiconductor device 7 shown in FIG. 2B and the cathode electrode C of the diode 2 are connected by a wiring (not shown), as in the circuit diagram shown in FIG. The drain D and the cathode electrode C are connected in common. The electrode formed at the bottom of the hole 8 can be an ohmic electrode, and the electrode formed on the back side of the substrate 21 can be a Schottky electrode.

  In the semiconductor device 7 shown in FIG. 2, a pair of electrodes for constituting the diode 2 is formed on the front side surface and the back side surface of the substrate 21, respectively. Therefore, all of the electrodes constituting the diode 2 do not occupy the surface on the front side of the substrate. Therefore, in the semiconductor device 7 in which the field effect transistor 1 and the diode 2 are integrated on the substrate 21, it is difficult to increase the substrate area.

Further, in the semiconductor device 7, the source electrode S and the drain electrode D of the field effect transistor 1 are both formed on the front side of the substrate 21. Thus, the drain current flowing as power between the source electrode S and the drain electrode D of the field effect transistor 1 is parallel to the substrate 21 in the nitride-based compound semiconductor layers 23 and 24 stacked on the substrate 21. Flowing.

  Normally, a large number of threading dislocations are generated in the nitride-based compound semiconductor layer stacked on the substrate in the vertical direction, so that leakage occurs when a current flows perpendicularly to the substrate. However, since the direction of the drain current flowing as power between the source electrode S and the drain electrode D is parallel to the substrate, drain current leakage can be reduced. Therefore, when the field effect transistor 1 of the semiconductor device 7 is used as a switching element of the power conversion device, power loss can be reduced.

  Further, when the field effect transistor 1 of the semiconductor device 7 is used as a switching element of the power conversion device 3 as shown in FIG. 1, the conversion efficiency of the power conversion device 3 is hardly lowered.

The direction of the current flowing between the anode electrode A and the cathode electrode C of the diode 2 of the semiconductor device 7 shown in FIG. 2 is the vertical direction (vertical direction) with respect to the substrate 21, but the diode 2 is a field effect transistor. As long as the protective element 1 is used, the current of the diode 2 does not always flow. Therefore, there is little problem of current leakage due to the presence of a large number of threading dislocations in the longitudinal direction in the nitride-based compound semiconductor layers 23 and 24 .

  In the semiconductor device 7 shown in FIG. 2B, the nitride-based compound semiconductor layers sequentially stacked on the front surface of the substrate 21 are the buffer layer 22, the first nitride-based compound semiconductor layer 23, and the second The nitride-based compound semiconductor layer 24 is formed. Here, the first nitride-based compound semiconductor layer 23 sandwiched between the buffer layer 22 and the second nitride-based compound semiconductor layer 24 that becomes the channel layer of the field effect transistor 1 is a high-resistance semiconductor layer. be able to.

  By doing so, the source electrode S and the drain electrode D of the field effect transistor 1 formed on the front side of the substrate 21 and the cathode electrode C (or the anode electrode A) formed on the back side of the substrate 21 have a high resistance. The nitride compound semiconductor layer 23 can be electrically separated. As a result, the drain current flowing in the second nitride compound semiconductor layer 24 functioning as the channel layer of the field effect transistor 1 is less likely to leak to the substrate 21 side. Therefore, when the field effect transistor 1 of the semiconductor device 7 is used as a switching element of the power conversion device, the power loss can be further reduced.

  The anode A as the Schottky electrode of the diode 2 of the semiconductor device 7 shown in FIG. 2B was formed directly on the substrate 21. However, like the semiconductor device 7 shown in FIG. 3, the Schottky electrode may be formed so as to be in contact with the nitride-based compound semiconductor layer.

  The configuration of the semiconductor device 7 illustrated in FIG. 3 is the same as that of the semiconductor device 7 illustrated in FIG. However, in the semiconductor device 7 shown in FIG. 3, the third semiconductor layer 25 is formed between the substrate 21 and the buffer layer 22. The anode electrode A as a Schottky electrode of the diode 2 is formed so as to be in direct contact with the third semiconductor layer 25.

  The third semiconductor layer 25 includes (a) a nitride-based compound semiconductor layer, (b) a stack on the substrate 21 made of the same material as the substrate 21, and (c) a nitride that forms the field effect transistor 1 together with the substrate 21. In some cases, the compound compound semiconductor layers 22, 23, and 24 are different layers.

  In such a case, it is preferable to use a GaN substrate by the HVPE method as the substrate 21, and a SiC substrate is also a material having a high withstand voltage. In order to stack nitride compound semiconductor thin films 23 and 24 constituting a transistor on a SiC substrate, a nucleated GaN film or an AlN film (hereinafter referred to as a nucleated nitride compound semiconductor thin film) is buffered by low temperature growth. When used as the layer 22, it is easy to obtain a high-quality nitride compound semiconductor film (23, 24).

  Further, Si can be used for the substrate 21. However, it is difficult to increase the breakdown voltage of the Schottky barrier formed on Si. Therefore, when Si is used for the substrate 21, it is necessary to form a Schottky electrode after forming a wide gap thin film such as AlN or SiC on Si.

  Various combinations of the substrate 21, the third semiconductor layer 25 (SBD layer), the buffer layer, and the first and second nitride compound semiconductor layers 22 to 24 can be considered. It is shown in Table 1 below.

(Table 1)
Substrate Third (SBD) layer Buffer layer First (high resistance) layer Second layer example 1 n ⁺ GaN n ^- GaN High resistance AlN High resistance GaN Al _0.15 GaN
Example 2 n ⁺ SiC n ^- SiC nucleation GaN high resistance GaN Al _0.15 GaN
Example 3 n ⁺ Si nucleation AlN / n ^- GaN None High resistance GaN Al _0.15 GaN
Example 4 n ⁺ GaN n ^- GaN / n ^- Al _0.15 GaN None High resistance GaN Al _0.15 GaN
* Said 2nd layer can also be made into n < ^- > GaN in all of Examples 1-4.

  Here, when the Schottky electrode is formed so as to be in direct contact with the third semiconductor layer 25, the Schottky electrode is better than when the Schottky electrode is formed so as to be in direct contact with the substrate 21. A Schottky barrier can be formed. In other words, it is difficult to adjust the concentration of the impurity distributed uniformly in the substrate, whereas in the case of a semiconductor layer, it is easy to adjust the impurity concentration when forming the layer in the process of epitaxial growth.

  The third semiconductor layer 25 can be a barrier adjustment layer that changes the height of the Schottky barrier with respect to the Schottky electrode in contact with the third semiconductor layer 25. In this way, the on-voltage of the diode 2 can be adjusted. That is, the physical properties of the substrate 21 are uniquely determined by the impurity concentration specific to the substrate material and the size of the band gap. Therefore, when the Schottky electrode is directly formed on the substrate 21, the on-voltage of the diode 2 is uniquely determined, and it is difficult to adjust it. However, when a Schottky electrode is formed on the third semiconductor layer 25 acting as a barrier adjustment layer, the physical properties of the third semiconductor layer 25 can be arbitrarily changed, and the height of the Schottky barrier is changed. be able to. For this reason, the on-voltage of the diode 2 can be easily adjusted.

  In order to change the height of the Schottky barrier with respect to the Schottky electrode using the third semiconductor layer 25 as a barrier adjustment layer, the impurity concentration of the third semiconductor layer 25 is changed or the material of the third semiconductor layer 25 is changed. What is necessary is just to change the magnitude | size of a band gap by changing the composition of the element which comprises.

  It is desirable that the breakdown voltage of the diode 2 as described above be smaller than the breakdown voltage between the source and drain when the field effect transistor 1 is off. In this way, when a high voltage is suddenly applied between the source electrode S and the drain electrode D in a state where the field effect transistor 1 is off, the diode before the field effect transistor 1 breaks down. Since 2 breaks down, the breakdown of the gate electrode G due to the breakdown of the field effect transistor 1 can be prevented.

(Example)
4A and 4B show a semiconductor device 7 according to an embodiment of the present invention, where FIG. 4A is a circuit diagram and FIG. 4B is a schematic cross-sectional view. This semiconductor device 7 can be used, for example, as a switching element constituting the power conversion device 3 shown in FIG.

  As shown in FIG. 4A, the semiconductor device 7 has a field effect transistor 1 and a diode 2 as a protection element connected in parallel, and the source S of the field effect transistor 1 is common to the anode A of the diode 2. The drain D is connected in common with the cathode C.

  As shown in FIG. 4B, in the semiconductor device 7, the field effect transistor 1 and the diode 2 are formed on a single substrate 21 made of GaN having n-type conductivity.

A buffer layer 22 made of a GaN layer having a thickness of 10 nm is formed on the substrate 21, and a first nitride compound semiconductor layer 23 made of a GaN layer having a thickness of 2000 nm is formed on the buffer layer 22. A second nitride-based compound semiconductor layer 24 composed of an undoped Al _0.15 Ga _0.85 N layer having a thickness of 5 nm is sequentially stacked.

  In order to configure the channel of the field effect transistor 1, the second nitride compound semiconductor layer 24 is used as the channel layer of the field effect transistor 1. In order to extract the current flowing in the channel layer, the second nitride compound semiconductor layer 24 of the field effect transistor 1 has a set of contact layers made of n-GaN doped with n-type impurities at a high concentration. 9 is embedded.

Further, the source electrode S and the drain electrode D made of Al / Ti / Au (thickness 50 nm / 50 nm / 100 nm) of the field effect transistor 1 are formed so as to be in contact with the pair of contact layers 9. The source electrode S is common to the cathode electrode C of the diode 2 of the semiconductor device 7 described below. A gate electrode G made of Pt / Au (thickness: 100 nm / 200 nm) of the field effect transistor 1 is formed on the second nitride compound semiconductor layer 24 sandwiched between the pair of contact layers 9. ing.

Here, the first nitride-based compound semiconductor layer 23 composed of the first nitride-based compound semiconductor layer 23 composed of the GaN layer and the second nitride-based compound semiconductor layer 24 composed of the Al _0.15 Ga _0.85 N layer are _arranged on the first nitride-based compound semiconductor layer 23 side. At the interface, electrons are generated by a piezoelectric field due to the difference in the composition of the two semiconductor layers. For this reason, even when no voltage is applied to the gate electrode G, the first nitride-based compound semiconductor layer 23 exhibits conductivity, and a current can flow between the source electrode S and the drain electrode D. .

  Therefore, when the field effect transistor 1 that is turned off when no voltage is applied to the gate electrode G is an enhancement type, it is necessary to compensate for electrons generated in the first nitride-based compound semiconductor layer 23. In order to compensate for electrons, the GaN layer constituting the first nitride-based compound semiconductor layer 23 is doped with a p-type impurity such as Mg. By doing so, electrons are compensated for and the resistance of the first nitride-based compound semiconductor layer 23 is increased.

In addition, a hole 8 is formed in the laminated nitride compound semiconductor layer (buffer layer 22, first nitride compound semiconductor layer 23, second nitride compound semiconductor layer 24). The hole 8 penetrates the laminated nitride compound semiconductor layer and reaches the substrate 21. In the hole 8 reaching the substrate 21, the cathode electrode C of the diode 2 which is common to the source electrode S of the field effect transistor 1 is embedded. In order to reduce the contact resistance of the cathode electrode C, an n-GaN layer doped with an n-type impurity at a high concentration is formed at the bottom of the hole 9 ′.

On the back surface of the substrate 21, a third semiconductor layer 25 made of an n ⁻ GaN layer having a thickness of 1000 nm for forming a Schottky diode is formed. The third semiconductor layer 25 is not only an n ⁻ GaN layer but also an n ⁻ SiC layer, a nucleation AlN / n ⁻ GaN layer, an n ⁻ GaN / n ⁻ Al _0.15 as shown in the above (Table 1). A GaN layer can be used.

  A trench 10 for improving the breakdown voltage of the diode 2 is formed in a part of the surface of the third semiconductor layer 25. The trench 10 is for avoiding electric field concentration at the edge of the Schottky electrode formed therein, and may not be formed if a desired breakdown voltage can be obtained without a trench structure.

Further, the height of the barrier is adjusted to an Al _0.2 Ga _0.8 N layer, an n ⁺ GaN layer, or a p ⁻ GaN layer of about 10 nm on the entire surface of the third semiconductor layer 25 on which the Schottky electrode is disposed or a part of the periphery thereof. It may be formed as a layer.

A passivation film 11 made of SiO ₂ having a thickness of 200 nm is formed on the surface of the third semiconductor layer 25 other than the place where the Schottky electrode is disposed, and the electrode material is on the Schottky electrode portion and the passivation film 11. It can be arranged on the entire back surface of.

The substrate 21, in place of the substrate made of _{GaN, Al x Ga 1-x} N (0 <x ≦ 1) even better, also the conductivity of ⁿ - SiC substrate, may further uses Si substrate it can.
When an n ⁻ SiC substrate is used as the substrate 21, a nitride compound semiconductor layer can be used as the third semiconductor layer 25. Further, n ^- Si can be used for the substrate 21. In this case, in order to ensure the withstand voltage of the diode 2, the nitride compound semiconductor layer and the SiC semiconductor stack formed on the back surface of the substrate 21 need to be sufficiently thick to ensure the withstand voltage. In an element having a withstand voltage of 1 kV or more, typically about 3 μm is required. At this time, it is necessary to dispose an appropriate buffer layer on the Si substrate for realizing the lamination.

  On the inner wall of the trench 10 and the surface of the passivation film 11, an anode electrode A of the diode 2 made of Pt / Au (thickness: 100/100 nm) of the diode 2 is formed. In order to prevent an electric field from concentrating on the side wall of the trench 10 when a voltage is applied between the cathode electrode C and the anode electrode A of the diode 2, the third semiconductor layer 25 has a portion on the side wall of the trench 10. Is formed with an ion implantation region 12 into which p-type ions are implanted. The source electrode S of the field effect transistor 1 of the semiconductor device 7 shown in FIG. 4B and the anode electrode A of the diode 2 are connected by a wiring (not shown), as shown in the circuit diagram of FIG. The source S and the anode A are connected in common.

The semiconductor device 7 shown in FIG. 4B can be manufactured as follows. Such a manufacturing process will be described with reference to FIG.
First, a GaN layer (buffer layer 22, which may be an AlN layer) having a thickness of 10 nm is formed on a substrate 21 made of GaN by MOCVD, and a p-type layer having a thickness of 2000 nm is further formed thereon. A GaN layer (first nitride compound semiconductor layer 23) is formed.

An undoped Al _0.2 Ga _0.8 N layer (carrier concentration is 1 × 10 ¹⁶ / cm ³ ) (second nitride-based compound semiconductor layer 24) having a thickness of 5 nm is formed thereon, and FIG. The layer structure A ₀ was epitaxially grown.

After the epitaxial growth of the layer structure A ₀ is completed, the SiO ₂ film is formed on the entire surface of the layer structure A _0, in the semiconductor device 7 shown in FIG. 4 (b), a region where the source electrode S and the drain electrode D are formed The SiO ₂ film corresponding to is removed. Then, an n-GaN contact layer 9 doped with Si at a high concentration was formed by selective growth again by MOCVD. Thereby, a layer structure A ₁ as shown in FIG. 5B is formed.

Thereafter, the layer structure A ₁ is taken out from the MOCVD apparatus, and all the SiO ₂ that has been selectively removed is removed and covered with a metal film and an SiO ₂ film in order to protect the growth surface of the layer structure A ₁ . Thereafter, the layer structure A ₁ is turned upside down and carried into the MOCVD apparatus again. Then, an n ⁻ GaN layer (third semiconductor layer 25) having a thickness of 1000 nm is formed on the back surface of the substrate 21.

After the third semiconductor layer 25 is formed, the layer structure A _{1 in} which the third semiconductor layer 25 is formed on the back surface of the substrate 21 is taken out from the MOCVD apparatus, and a SiO ₂ film is formed on the entire surface of the layer structure A _1. In the semiconductor device 7 shown in FIG. 4B, a portion of the SiO ₂ film corresponding to the region where the drain electrode D is formed is removed. Then, the hole 8 reaching the substrate 21 is opened by a technique such as RIBE (Reactive Ion Beam Etching) using chlorine gas. After opening the hole 8, an n-GaN contact layer 9 'doped with Si at a high concentration was formed by selective growth again by MOCVD. Thereby, a layer structure A ₂ as shown in FIG. 5C is formed.

Then, a passivation film 11 made of SiO ₂ having a thickness of 200 nm is formed on the back surface of the layer structure A ₂ . Thereafter, the passivation film 11 in the region where the anode electrode A of the diode 2 is formed is contacted with the third semiconductor layer 25, and the trench 10 is opened by a technique such as RIBE using chlorine gas. Thereafter, Mg and C elements (when using a GaN substrate; when using a SiC substrate, Al is used as an element) are implanted into the side surface of the trench 10 by an oblique ion implantation method. Form. As a result, a layer structure A ₃ as shown in FIG. 5D is completed.

Then, a source electrode S and a drain electrode D (cathode electrode C) are formed on the contact layers 9 and 9 ′, and a gate electrode G is formed between the source electrode S and the drain electrode D by a conventional method. Further, the anode electrode A is formed on the back side of the layer structure A _{3 by} a conventional method, and the semiconductor device 7 shown in FIG. 4B (or FIG. 2B) is completed. Note that the source electrode S and the anode electrode A of the diode 2 are connected by a wiring (not shown) so that the semiconductor device 7 has the circuit diagram shown in FIG. 4A (or FIG. 2A).

An example in which the semiconductor device 7 having the circuit diagram shown in FIG. 4A is actually operated will be described with reference to FIG. In the circuit diagram of FIG. 4A, when the drain D side of the transistor has a high potential Vd, the source S side has a zero potential, and a transistor ON voltage is applied to the gate G, the transistor turns on. In this state, a drain current flows Id _FET between the drain D and the source S as shown in Figure 6 (a). On the other hand, in this state, the anode A of the diode in the circuit diagram of FIG. 4A has a zero potential, and the cathode C has a high potential. For this reason, since a reverse voltage is applied to the diode, the current I _SBD flowing through the diode is very small as shown in FIG.

  Note that when a transistor off voltage is applied to the gate G of the transistor 1 in the circuit diagram of the semiconductor device 7 in FIG. 4A, the transistor 1 is turned off, and no current flows between the drain D and the source S. . On the other hand, even when the off-voltage of the transistor is applied to the gate G, when the semiconductor device 7 is used as a switching element of the power conversion device, a negative high voltage suddenly appears on the drain D side. An applied so-called reverse surge phenomenon may occur.

The wiring of the gate part of the field effect transistor is vulnerable to a current surge. For example, when a reverse voltage generated by an inductive load is applied to the drain in the off state of the field effect transistor, the gate Schottky barrier is forward-biased, causing a large current surge to flow into the gate circuit and wiring. May be cut or the ignition circuit may be destroyed.
The protective diode 2 of the semiconductor device 7 of this embodiment has a function of preventing the field effect transistor 1 from being destroyed by this current surge.

When a reverse surge phenomenon occurs, the anode A of the diode 2 in the circuit diagram of FIG. 4A has a zero potential, and the cathode C has a high potential in the negative direction. At this time, since a forward voltage is applied to the diode 2, the diode 2 is turned on as shown in FIG. 6B, and the current I _SBD flowing through the diode 2 increases. Therefore, the surge current in the reverse direction does not flow between the source S and the drain D of the transistor 1 but flows to the diode 2 side, so that the transistor 1 is protected.

  The approximate magnitude of the on-voltage of the protective diode 2 determines the height of the Schottky barrier. The substrate or the semiconductor layer 25 on which the Schottky barrier of the diode is formed is GaN or SiC and has a barrier height of approximately 1 V or more, but there is a forward current by means such as adjusting the doping on the outermost surface. It is possible to adjust the effective on-voltage defined by being greater than or equal to a small value, and not to increase the breakdown voltage and the leakage current. For example, the on-voltage of the protection diode 2 can be set between 0.5 and 1.0 V against a current surge of about 100 A. On the other hand, the ON voltage of the gate portion of the field effect transistor 1 substantially matches the barrier height of the Schottky barrier of the gate portion, and can be set to about 1V or more. That is, the on-voltage of the protection diode 2 can be set smaller than the on-voltage of the gate portion of the field effect transistor 1.

  Therefore, the diode 2 can be set to be turned on before the overvoltage is applied to the drain, and the current surge flows through the diode 2 to protect the gate portion of the field effect transistor 1. Since the protection diode of the present invention can secure a sufficiently large element area, it can withstand a large surge current and be fed back to the power supply, so that a good protection function can be obtained.

Furthermore, the protection diode 2 in the semiconductor device 7 according to the embodiment of the present invention has a function of protecting the gate circuit of the field effect transistor 1 from a forward voltage surge. In a single field-effect transistor in the off state, if a voltage exceeding the breakdown voltage of the field-effect transistor is applied to the drain, the gate circuit breaks down due to breakdown of the Schottky barrier of the gate or flow of a transient current There is a case. It is possible to add a protection function by adjusting the breakdown voltage of the protection diode 2 to be smaller than the breakdown voltage of the field effect transistor 1. For example, when the drain withstand voltage of the field effect transistor 1 is 1200V, the withstand voltage of the protection diode 2 can be set to 100V. The withstand voltage can be adjusted by sufficiently increasing the element area of the protection diode 2 with respect to the gate portion. In this case, a capacitively coupled protection function can be added.

  By adding the protection function, the diode 2 breaks down before the field effect transistor 1 even when a forward surge phenomenon occurs. Thereby, the electrode destruction of the drain D by the breakdown of the field effect transistor 1 can be prevented.

  As described above, in the semiconductor device of the present invention, a high-performance field effect transistor using a nitride-based compound semiconductor having a protective diode having a sufficient function can be configured without increasing the element area. By applying the element to a power supply circuit, it is possible to provide a high-performance power supply that is low in cost, compact, and resistant to surge.

The circuit diagram of the inverter as a power converter device of the present invention is shown. The semiconductor device as a switching element used for the power converter device of the present invention is shown, and (a) is a circuit diagram and (b) is a schematic sectional view. It is a schematic sectional drawing of the semiconductor device of this invention. BRIEF DESCRIPTION OF THE DRAWINGS The semiconductor device about the Example of this invention is shown, (a) is a circuit diagram, (b) is a schematic sectional drawing. The manufacturing process of the semiconductor device about the Example of this invention is shown. The operating characteristic of the semiconductor device about the Example of this invention is shown. The circuit diagram of the inverter as a power converter device is shown. (A) is a circuit diagram which shows the field effect transistor as a switching element, and the Schottky diode as its protection element, (b) is a schematic sectional drawing which shows the field effect transistor incorporating the Schottky diode. .

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Field effect transistor, 2 ... Diode, 3 ... Power converter, 4 ... AC power supply, 5 ... Rectifier circuit, 6 ... Inverter circuit, 7 ... Semiconductor device, 8 ... Hole, 9 ... Contact layer, 10 ... Trench, 11 ... Passivation film, 12 ... Ion implantation region, 21 ... Substrate, 22 ... Buffer layer, 23 ... First nitride compound semiconductor layer, 24 ... Second nitride compound semiconductor layer, 25 ... Third semiconductor Layer (barrier adjustment layer), 26 ... electric field concentration relaxation layer, 100 ... field effect transistor, 100 ... diode, 300 ... power converter, 400 ... AC power supply, 500 ... rectifier circuit, 600 ... inverter circuit

Claims (9)

A semiconductor device having a field effect transistor and a diode,
A conductive semiconductor substrate;
A laminated semiconductor layer in which a nitride compound semiconductor layer functioning as at least one buffer layer and at least one nitride compound semiconductor layer constituting the field effect transistor are laminated on one surface of the semiconductor substrate;
Have
A gate electrode of the field effect transistor is formed on the nitride-based compound semiconductor layer on the surface of the stacked semiconductor layer;
First and second electrodes of the field effect transistor are formed on the nitride-based compound semiconductor layer,
A nitride-based compound semiconductor functioning as a buffer layer constituting the laminated conductor layer in contact with the semiconductor substrate, or a hole reaching the semiconductor substrate through the laminated semiconductor layer in a direction perpendicular to the surface of the substrate hole is formed to penetrate the laminated semiconductor layer to layer,
The first electrode of the diode is embedded to the bottom of the hole;
One electrode of the first and second electrodes of the field effect transistor and the first electrode of the diode buried up to the bottom of the hole are formed by a common electrode,
A second electrode of the diode is formed on the other surface of the substrate or on a semiconductor layer formed on the other surface of the substrate;
Semiconductor device. The first electrode or the second electrode of the diode is a Schottky electrode, and the other electrode is an ohmic electrode,
The gate electrode of the field effect transistor is a Schottky type or MIS type electrode.
The semiconductor device according to claim 1 . The Schottky electrode of the diode is formed through the nitride compound semiconductor layer as a barrier adjustment layer that changes the height of the Schottky barrier.
The semiconductor device according to claim 2 . A high resistance nitride-based compound semiconductor layer is formed between one surface side of the substrate and the semiconductor layer constituting the stacked semiconductor layer,
The semiconductor device according to claim 1 . The on-voltage of the diode is lower than the gate breakdown voltage between the gate and drain of the field-effect transistor when the field-effect transistor is off;
The semiconductor device according to claim 1 . The semiconductor device according to claim 1 , wherein a breakdown voltage of the diode is lower than a breakdown voltage between a source and a drain of the field effect transistor when the field effect transistor is in an off state. The conductive semiconductor substrate is an Al _x Ga _1-x N (0 ≦ x ≦ 1) substrate, a SiC substrate, or a Si substrate.
The semiconductor device according to claim 1 . A power conversion circuit using the field effect transistor of the semiconductor device having the field effect transistor and the diode according to claim 1 as a switching element.
Power conversion device. The power conversion circuit is an inverter circuit or a converter circuit.
The power conversion device according to claim 8 .

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