JPH02153539A - Compound semiconductor device - Google Patents
Compound semiconductor deviceInfo
- Publication number
- JPH02153539A JPH02153539A JP30819188A JP30819188A JPH02153539A JP H02153539 A JPH02153539 A JP H02153539A JP 30819188 A JP30819188 A JP 30819188A JP 30819188 A JP30819188 A JP 30819188A JP H02153539 A JPH02153539 A JP H02153539A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- electrode
- voltage
- type
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 23
- 150000001875 compounds Chemical class 0.000 title claims abstract description 13
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 239000000463 material Substances 0.000 claims description 4
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 16
- 230000015556 catabolic process Effects 0.000 abstract description 12
- 239000002184 metal Substances 0.000 abstract description 4
- 238000000034 method Methods 0.000 abstract description 3
- 230000001681 protective effect Effects 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 11
- 230000000694 effects Effects 0.000 description 7
- 239000002019 doping agent Substances 0.000 description 2
- 238000004891 communication Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 1
Landscapes
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は化合物半導体装置に関し、特に入力保護回路を
有する化合物半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a compound semiconductor device, and particularly to a compound semiconductor device having an input protection circuit.
従来から化合物半導体装置に入力保護回路内蔵するモノ
リシックＩＣが使用されているが、最近はその微細化要
望がますます強くなってきた。Monolithic ICs with built-in input protection circuits have traditionally been used in compound semiconductor devices, but recently there has been a growing demand for miniaturization.
第３図（ａ）及び（ｂ）は従来の化合物半導体装置の一
例の断面模式図及び等価回路図である。FIGS. 3(a) and 3(b) are a schematic cross-sectional view and an equivalent circuit diagram of an example of a conventional compound semiconductor device.
第３図（ａ）に示すように、化合物半導体装置は、半絶
縁性ＧａＡｓ基板１ｂの上層のＰ型半導体領域２１の上
層にｎｐｎトランジスタＴ、とそれにフィールド絶縁膜
２２を介して隣接するＭＥＳトランジスタＭＥＳを有し
ている。As shown in FIG. 3(a), the compound semiconductor device includes an npn transistor T in the upper layer of the P-type semiconductor region 21 on the upper layer of the semi-insulating GaAs substrate 1b, and an MES transistor adjacent thereto via the field insulating film 22. It has MES.
第３図（ｂ）に示すように、この作用効果については特
公昭６３−００１２３９５に記載されているが、入力端
子Ｔｌに入力したサージ電圧は抵抗Ｒ１とｎｐｎ）ラン
ジスタＴ、の接続する節点Ｎ、の電圧が数Ｖ〜数＋Ｖに
なると、ＭＥＳトランジスタＭＥＳがオンしてＩＣの回
路に接続する節点Ｎ２の電圧を接地点電位Ｖｇ５に抑え
ている。As shown in FIG. 3(b), this effect is described in Japanese Patent Publication No. 63-0012395, but the surge voltage input to the input terminal Tl is applied to the node N where the resistor R1 and the npn transistor T are connected. , when the voltage reaches several volts to several + volts, the MES transistor MES turns on and suppresses the voltage at the node N2 connected to the IC circuit to the ground potential Vg5.
その他に、電子通信学会技術研究報告（第８６号、論文
番号５ＳＤ−８５−１３８，１９８６年、第７７頁）に
は、内蔵するショットキーダイオードを逆方向にバイア
スさせてＧａＡｓのＩＣの内部回路にダイオードの逆耐
圧電圧以上が印加されないようにしている。In addition, the Institute of Electronics and Communication Engineers Technical Research Report (No. 86, Paper No. 5SD-85-138, 1986, page 77) describes how to reverse bias the built-in Schottky diode to improve the internal circuit of a GaAs IC. This prevents a voltage higher than the reverse breakdown voltage of the diode from being applied to the diode.
上述した従来の化合物半導体装置は、まずバイポーラト
ランジスタとＭＥＳトランジスタを用いる方法では、入
力保護回路の素子面積が大きい上２種類の素子を構成し
なければならないので、素子の特性の製造ばらつきによ
って入力保護回路の動作がばらつくという欠点があった
。In the conventional compound semiconductor device described above, first, in the method using bipolar transistors and MES transistors, the element area of the input protection circuit is large, and two types of elements must be configured, so the input protection may be affected by manufacturing variations in the characteristics of the elements. The disadvantage was that the circuit operation varied.
また、ショットキーダイオードの逆方向耐圧を利用する
方法では、ＩＣの内部回路の前段にショットキーダイオ
ードを構成しないといけない為、平面に余分な面積が必
要となり、チップ小型化が困難な上に、ダイオードの逆
方向耐圧を任意に設定しにくいという欠点もあった。In addition, in the method that utilizes the reverse breakdown voltage of a Schottky diode, the Schottky diode must be configured in the front stage of the internal circuit of the IC, which requires an extra surface area, making it difficult to miniaturize the chip. Another drawback was that it was difficult to arbitrarily set the reverse breakdown voltage of the diode.
本発明の目的は、耐圧特性が均一な入力保護回路を有す
る小形の化合物半導体装置を提供することにある。An object of the present invention is to provide a compact compound semiconductor device having an input protection circuit with uniform breakdown voltage characteristics.
〔課題を解決するための手段〕
本発明の半導体装置は、裏面にバイアホール部を有する
半絶縁性基板と、該半絶縁性基板の表面に該半絶縁性基
板の材料よりも広いバンドギャップを有する半導体材料
で形成されかつ前記バイアホール部を介して前記半絶縁
性基板の裏面に接続する一導電型半導体領域と、該一導
電型半導体領域の表面に形成された逆導電型半導体領域
とを含んで構成されている。[Means for Solving the Problems] A semiconductor device of the present invention includes a semi-insulating substrate having a via hole portion on the back surface and a bandgap wider than the material of the semi-insulating substrate on the surface of the semi-insulating substrate. a semiconductor region of one conductivity type formed of a semiconductor material and connected to the back surface of the semi-insulating substrate via the via hole portion, and a semiconductor region of opposite conductivity type formed on the surface of the semiconductor region of one conductivity type. It is composed of:
次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図（ａ）〜（ｃ）は本発明の第１の実施例のパター
ン図、対応するチップのＡ−Ａ’ 線断面図及び等価回
路図である。FIGS. 1(a) to 1(c) are a pattern diagram of a first embodiment of the present invention, a sectional view taken along line AA' of a corresponding chip, and an equivalent circuit diagram.
第１図＜ａ）及び（ｂ）に示すように、まず、半絶縁性
ＧａＡｓ基板１の上にｐ型ＧａｘＡｔ’ ＋ｔ−ｘ＋Ａ
Ｓ層４及びｎ型ＧａＡｓ層５をエピタキシャル成長によ
り形成する。As shown in FIGS. 1A and 1B, first, a p-type GaxAt' +t-x+A
An S layer 4 and an n-type GaAs layer 5 are formed by epitaxial growth.
さらにその上層にＭＯＳトランジスタＱｌを形成する。Furthermore, a MOS transistor Ql is formed in the upper layer.
ドレイン電極６とソース電極９の下には、ＭＯＣＶＤ法
にて選択成長させたｎ＋型ＧａＡｓ層７が設けである。An n+ type GaAs layer 7 selectively grown by MOCVD is provided below the drain electrode 6 and source electrode 9.
またドレイン電極６下の半絶縁性ＧａＡｓ基板１にはバ
イアホール部３゜があり、裏面接地用金属層２を通して
ｐ型ＧａｘＡＪ’ ＋１−ＸｌｋＳ層４を接地している
。Further, the semi-insulating GaAs substrate 1 under the drain electrode 6 has a via hole portion 3°, and the p-type GaxAJ' +1-XlkS layer 4 is grounded through the back surface grounding metal layer 2.
第１図（ｃ）に示すようにトレイン電極６に正電圧ＶＤ
Ｓを印加すると、ｐ型ＧａｘＡＮ Ｔｌ−ＸｌＡＳ層４
とｎ型ＧａＡｓ層５で構成されているｐｎ接合のダイオ
ードＤＤには逆方向バイアスが加わる。As shown in FIG. 1(c), a positive voltage VD is applied to the train electrode 6.
When S is applied, the p-type GaxAN Tl-XlAS layer 4
A reverse bias is applied to the pn junction diode DD composed of the n-type GaAs layer 5 and the n-type GaAs layer 5.
このダイオードＤＤの逆方向耐圧をＶｒ及びＭＯＳトラ
ンジスタＱ１のドレイン耐圧をＢＶｄｓとするとき、Ｖ
ｒがＢＶｄｓより小さい範囲内でしかもＭＯＳ）ランジ
スタＱ１の動作を制限しない値となるように、ｐ型Ｇａ
ｘＡｆ （１−Ｘ）＾Ｓ層４の厚みとドーパント濃度を
選ぶ。When the reverse breakdown voltage of this diode DD is Vr and the drain breakdown voltage of the MOS transistor Q1 is BVds, V
The p-type Ga
Select the thickness and dopant concentration of xAf (1-X)^S layer 4.
今、ドレイン電極６に過大電圧Ｖが加わると、トランジ
スタＱｌにはｐｎ接合のダイオードＤ。Now, when an excessive voltage V is applied to the drain electrode 6, a pn junction diode D is applied to the transistor Ql.
のアバランシェ降伏による逆耐圧Ｖｒ以上の電圧は加わ
らないことになり、そのなめにダイオードＤＤの平面チ
ップ面積を必要としない分だけ微細化できる効果がある
。A voltage higher than the reverse withstand voltage Vr due to avalanche breakdown is not applied, which has the effect of miniaturizing the planar chip area of the diode DD by an amount that is not required.
一方、動作領域１０の下部にｐ型のバッファ層を埋込ん
だ構造なのでＧａＡｓ基板１への漏れ電流が減りバック
ゲート効果の発生を防ぐ効果もある。On the other hand, since the structure has a p-type buffer layer buried below the operating region 10, leakage current to the GaAs substrate 1 is reduced, which also has the effect of preventing the back gate effect.
ここで、ダイオードＤＤの逆耐圧Ｖｒは、結晶のドーパ
ント濃度や厚みにより変化させて最適値を設定すること
ができる。Here, the reverse breakdown voltage Vr of the diode DD can be set to an optimum value by changing it depending on the dopant concentration and thickness of the crystal.
第２図（ａ）〜（ｃ）は本発明の第２の実施例のパター
ン図、対応するチップのＡ−Ａ’線断面図及び等価回路
図である。FIGS. 2(a) to 2(c) are a pattern diagram of a second embodiment of the present invention, a sectional view taken along the line AA' of the corresponding chip, and an equivalent circuit diagram.
第２図（ａ）及び（ｂ）に示すように、半絶縁性ＧａＡ
ｓ基板１．の上にｎ型ＧａｘＡｌ （１−Ｘ）Ａ４１層
１４とｐ型ＧａＡｓ１５を各々エピタキシャル成長によ
り形成する。ゲート電極ポンディングパッド８Ｂの下方
にバイアホール部３Ｂを形成し、裏面接地用金属層２．
を通してｎ型Ｇａｘ／Ｌ？ ＋１−ＸｌＡＳ層１４を接
地している。As shown in FIGS. 2(a) and (b), semi-insulating GaA
s substrate 1. An n-type GaxAl (1-X)A41 layer 14 and a p-type GaAs layer 15 are each formed on the layer by epitaxial growth. A via hole portion 3B is formed below the gate electrode bonding pad 8B, and a back ground metal layer 2.
Through n-type Gax/L? +1-XlAS layer 14 is grounded.
今、ゲート電極に負電圧ＶＧｓが印加されると、ρ型Ｇ
ａＡｓ層１５とｎ型Ｇａｘｋｅ （１−ＸＩＡＳ層１４
がら形成されるｐｎ接合のダイオードＤ、には逆方向バ
イアスが加わる。Now, when a negative voltage VGs is applied to the gate electrode, the ρ type G
aAs layer 15 and n-type Gaxke (1-XIAS layer 14
A reverse bias is applied to the pn junction diode D that is formed.
第１の実施例と同じようにＭＯＳ）ランジスタＱ２のシ
ョットキー逆方向耐圧をＢＶ、ｄとするとき、ダイオー
ドＤＧの耐圧ＶｒをＢＶ、ｄ以下でしかもトランジスタ
Ｑ２の動作を制限しないように選べば、トランジスタＱ
２のゲートＧには７１以上の電圧は加わらないことにな
る。As in the first embodiment, when the Schottky reverse breakdown voltage of transistor Q2 (MOS) is set to BV, d, if the breakdown voltage Vr of diode DG is selected to be less than BV, d and not to limit the operation of transistor Q2. , transistor Q
A voltage of 71 or more will not be applied to the gate G of No. 2.
また動作層１０．はｐ型ＧａＡｓ層１５にＳｔ＋等をイ
オン注入することでｎ型ＧａＡｓ層を形成している上述
の第１及び第２の実施例において、ｐｎ接合のダイオー
ドの２層とｎ層をエピタキシャル成長により形成したが
、イオン注入法によっても同様の効果が得られる。Also, the operating layer 10. In the first and second embodiments described above, in which the n-type GaAs layer is formed by ion-implanting St + etc. into the p-type GaAs layer 15, the two layers of the p-n junction diode and the n-layer are formed by epitaxial growth. However, similar effects can also be obtained by ion implantation.
以上説明したように本発明は、化合物半導体装置の保護
したい電極下部に、逆方向バイアスが印加されるｐｎ接
合のダイオードを形成するので、耐圧特性が均一な入力
保護回路を有する小形の化合物半導体装置が得られる効
果がある。As explained above, the present invention forms a pn junction diode to which a reverse bias is applied under the electrode to be protected in a compound semiconductor device, so that a small compound semiconductor device having an input protection circuit with uniform breakdown voltage characteristics can be achieved. There is an effect that can be obtained.
第１図（ａ）〜（Ｃ）は本発明の第１の実施例のパター
ン図、対応するチップのＡ−Ａ’線断面図及び等価回路
図、第２図（ａ）〜（Ｃ）は本発明の第２の実施例のパ
ターン図、対応するチップのＡ−Ａ’線断面図及び等価
回路図、第３図（ａ）及び（ｂ）は従来の化合物半導体
装置の一例の断面模式図及び等価回路図である。
１．１１・・・半絶縁性ＧａＡｓ基板、２，２．・・・
裏面接続用金属層、３Ｂ、３０・・・バイアホール部、
４・ｐ型ＧａｘＡｆ （１−Ｘ）＾Ｓ層、５ ・−ｎ型
ＧａＡｓ層、１４・・・ｎ型ＧａｘＡｆ （１−Ｘ）＾
Ｓ層、１５−ｐ型ＧａＡｓ層、ＤＤ 、ＤＧ・・・ダイ
オード。FIGS. 1(a) to (C) are pattern diagrams of the first embodiment of the present invention, a sectional view taken along line A-A' of the corresponding chip, and an equivalent circuit diagram, and FIGS. 2(a) to (C) are pattern diagrams of the first embodiment of the present invention. A pattern diagram of the second embodiment of the present invention, a cross-sectional view along the line A-A' of the corresponding chip, and an equivalent circuit diagram, and FIGS. 3(a) and (b) are schematic cross-sectional views of an example of a conventional compound semiconductor device. and an equivalent circuit diagram. 1.11... Semi-insulating GaAs substrate, 2,2. ...
Back side connection metal layer, 3B, 30... via hole part,
4.p-type GaxAf (1-X)^S layer, 5.-n-type GaAs layer, 14...n-type GaxAf (1-X)^
S layer, 15-p type GaAs layer, DD, DG...diode.
Claims (1)
縁性基板の表面に該半絶縁性基板の材料よりも広いバン
ドギャップを有する半導体材料で形成されかつ前記バイ
アホール部を介して前記半絶縁性基板の裏面に接続する
一導電型半導体領域と、該一導電型半導体領域の表面に
形成された逆導電型半導体領域とを含むことを特徴とす
る化合物半導体装置。A semi-insulating substrate having a via hole portion on the back surface, and a semi-insulating substrate formed of a semiconductor material having a wider bandgap than the material of the semi-insulating substrate on the surface thereof, and the semi-insulating substrate having a via hole portion formed on the surface thereof. A compound semiconductor device comprising: a semiconductor region of one conductivity type connected to the back surface of an insulating substrate; and a semiconductor region of opposite conductivity type formed on the surface of the semiconductor region of one conductivity type.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30819188A JPH02153539A (en) | 1988-12-05 | 1988-12-05 | Compound semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30819188A JPH02153539A (en) | 1988-12-05 | 1988-12-05 | Compound semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02153539A true JPH02153539A (en) | 1990-06-13 |
Family
ID=17978011
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP30819188A Pending JPH02153539A (en) | 1988-12-05 | 1988-12-05 | Compound semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02153539A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08250984A (en) * | 1995-01-13 | 1996-09-27 | Nec Corp | Logic circuit |
| JP2007266475A (en) * | 2006-03-29 | 2007-10-11 | Furukawa Electric Co Ltd:The | Semiconductor device and power conversion apparatus |
| WO2010021099A1 (en) * | 2008-08-22 | 2010-02-25 | パナソニック株式会社 | Field effect transistor |
-
1988
- 1988-12-05 JP JP30819188A patent/JPH02153539A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08250984A (en) * | 1995-01-13 | 1996-09-27 | Nec Corp | Logic circuit |
| JP2007266475A (en) * | 2006-03-29 | 2007-10-11 | Furukawa Electric Co Ltd:The | Semiconductor device and power conversion apparatus |
| WO2010021099A1 (en) * | 2008-08-22 | 2010-02-25 | パナソニック株式会社 | Field effect transistor |
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