JP2014056938A - Semiconductor device and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To achieve a semiconductor device which reliably achieves functions of first and second elements by a device configuration as simple as possible, and reduces a new material and a new process thereby to enable manufacturing in the minimum number of processes, and which has high reliability.SOLUTION: A compound semiconductor 5 is formed with: a HEMT utilizing a two-dimensional carrier gas produced in the compound semiconductor 5; and a junction element including an impurity diffusion region 3 formed on an Si substrate 1, conductive plugs 7A, 7B which are formed in the compound semiconductor 5 and electrically connected with the impurity region 3; and a 2DEG block structure 8 which is formed in the compound semiconductor 5 for electrically blocking the two-dimensional gas with respect to each of the conductive plugs 7A, 7B.

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof.

  Nitride semiconductors have been studied for application to high breakdown voltage and high output semiconductor devices utilizing characteristics such as high saturation electron velocity and wide band gap. For example, the band gap of GaN, which is a nitride semiconductor, is 3.4 eV, which is larger than the band gap of Si (1.1 eV) and the band gap of GaAs (1.4 eV), and has a high breakdown electric field strength. Therefore, GaN is extremely promising as a material for a semiconductor device for a power supply that obtains high voltage operation and high output.

  As semiconductor devices using nitride semiconductors (nitride semiconductor devices), many reports have been made on field-effect transistors, particularly high electron mobility transistors (HEMTs). For example, in a GaN-based HEMT (GaN-HEMT), AlGaN / GaN.HEMT using GaN as an electron transit layer and AlGaN as an electron supply layer has attracted attention. In AlGaN / GaN.HEMT, strain caused by the difference in lattice constant between GaN and AlGaN is generated in AlGaN. A high-concentration two-dimensional electron gas (2DEG) is obtained by the piezoelectric polarization generated thereby and the spontaneous polarization of AlGaN. Therefore, it is expected as a high-efficiency power device for high-efficiency switching elements, electric vehicles and the like.

JP 2008-198675 A JP 2008-218786 A

  When compound semiconductor elements such as HEMT and MIS transistors are mixedly mounted with silicon elements such as diodes, MIS transistors and biopolar transistors, the following configuration is adopted. The case where HEMT and a MIS transistor are mixedly mounted is illustrated.

  A stacked structure of a compound semiconductor, for example, a nitride semiconductor is formed on a semiconductor substrate. First, a gate, a source, and a drain are formed in a first region of the nitride semiconductor stacked structure, and a predetermined wiring is formed to manufacture a HEMT. . Subsequently, the second region of the nitride semiconductor multilayer structure is removed by etching. An impurity diffusion region is formed in the exposed semiconductor substrate, a gate is formed, and an interlayer insulating film covering the gate is formed in the second region so as to be adjacent to the nitride semiconductor multilayer structure. Conductive plugs are formed in the interlayer insulating film, and predetermined wiring is formed to manufacture a MIS transistor.

  It is also conceivable to manufacture a MIS transistor by fabricating a HEMT as described above and then laminating a semiconductor layer and an interlayer insulating film on the nitride semiconductor multilayer structure.

  However, in the above case, the mixed configuration of the HEMT and the MIS transistor is complicated, and in order to obtain this mixed configuration, the manufacturing process is inevitably increased, and new materials and new processes must be introduced. However, the development load is extremely large.

  The present invention has been made in view of the above problems, and is as simple as possible in a semiconductor device in which a first element that is a compound semiconductor element and a second element that is a silicon element are mixedly mounted. The first and second elements are realized by the device configuration. Accordingly, an object is to provide a highly reliable semiconductor device that can be manufactured with a minimum number of steps by reducing new materials and new steps, and a method for manufacturing the same.

  One aspect of the compound semiconductor device includes a silicon region, a compound semiconductor stacked structure formed on the silicon region, and a first element and a second element formed in the compound semiconductor stacked structure, The element 2 includes an impurity diffusion portion formed in the silicon region and a conductive portion formed in the compound semiconductor multilayer structure and electrically connected to the impurity diffusion portion.

  One aspect of a method for manufacturing a compound semiconductor device includes a step of forming an impurity diffusion portion in a silicon region, a step of forming a compound semiconductor multilayer structure on the silicon region, a first element and a first element in the compound semiconductor multilayer structure. The second element is formed in the compound semiconductor multilayer structure and is electrically connected to the impurity diffusion part. An element having a conductive portion.

  According to the above aspects, in the semiconductor device in which the first element that is a compound semiconductor element and the second element that is a silicon element are mixedly mounted, the first and second devices can be configured as simple as possible. The element is realized. Thus, a highly reliable semiconductor device that can be manufactured with a minimum number of processes by reducing new materials and new processes is realized.

It is a schematic sectional drawing which shows the manufacturing method of the semiconductor device by 1st Embodiment in order of a process. FIG. 2 is a schematic cross-sectional view showing the method of manufacturing the semiconductor device according to the first embodiment in the order of steps, following FIG. 1. FIG. 3 is a schematic cross-sectional view showing the method of manufacturing the semiconductor device according to the first embodiment in order of processes following FIG. 2. FIG. 4 is a schematic cross-sectional view subsequent to FIG. 3, illustrating the method for manufacturing the semiconductor device according to the first embodiment in the order of steps. FIG. 5 is a schematic cross-sectional view subsequent to FIG. 4, illustrating the method for manufacturing the semiconductor device according to the first embodiment in the order of steps. FIG. 6 is a schematic cross-sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment in the order of steps, following FIG. 5. FIG. 7 is a schematic cross-sectional view subsequent to FIG. 6 showing the method of manufacturing the semiconductor device according to the first embodiment in the order of steps. FIG. 8 is a schematic cross-sectional view illustrating the manufacturing method of the semiconductor device according to the first embodiment in order of processes subsequent to FIG. 7. FIG. 9 is a schematic cross-sectional view illustrating the manufacturing method of the semiconductor device according to the first embodiment in order of processes subsequent to FIG. 8. FIG. 10 is a schematic cross-sectional view showing the method of manufacturing the semiconductor device according to the first embodiment in order of processes subsequent to FIG. 9; FIG. 11 is a schematic cross-sectional view illustrating the manufacturing method of the semiconductor device according to the first embodiment in order of processes subsequent to FIG. 10. FIG. 12 is a schematic cross-sectional view subsequent to FIG. 11, illustrating the method for manufacturing the semiconductor device according to the first embodiment in the order of steps. FIG. 13 is a schematic cross-sectional view illustrating the manufacturing method of the semiconductor device according to the first embodiment in order of processes subsequent to FIG. 12. FIG. 14 is a schematic cross-sectional view subsequent to FIG. 13 showing the method of manufacturing the semiconductor device according to the first embodiment in the order of steps. FIG. 15 is a schematic cross-sectional view illustrating the manufacturing method of the semiconductor device according to the first embodiment in order of processes subsequent to FIG. 14; It is a schematic sectional drawing which shows the manufacturing method of the semiconductor device by 2nd Embodiment in order of a process. FIG. 17 is a schematic cross-sectional view showing the method of manufacturing the semiconductor device according to the second embodiment in order of processes subsequent to FIG. 16; FIG. 18 is a schematic cross-sectional view showing the method of manufacturing the semiconductor device according to the second embodiment in order of processes subsequent to FIG. 17. FIG. 19 is a schematic cross-sectional view showing the method of manufacturing the semiconductor device according to the second embodiment in order of processes following FIG. 18. FIG. 20 is a schematic cross-sectional view showing the method of manufacturing the semiconductor device according to the second embodiment in order of processes subsequent to FIG. 19. FIG. 21 is a schematic cross-sectional view showing the method of manufacturing the semiconductor device according to the second embodiment in order of processes subsequent to FIG. 20. FIG. 22 is a schematic cross-sectional view showing the method of manufacturing the semiconductor device according to the second embodiment in order of processes subsequent to FIG. 21. FIG. 23 is a schematic cross-sectional view showing the method of manufacturing the semiconductor device according to the second embodiment in order of processes subsequent to FIG. 22. FIG. 24 is a schematic cross-sectional view showing the method of manufacturing the semiconductor device according to the second embodiment in order of processes subsequent to FIG. 23. FIG. 25 is a schematic cross-sectional view showing the method of manufacturing the semiconductor device according to the second embodiment in order of processes subsequent to FIG. 24. FIG. 26 is a schematic cross-sectional view showing the method of manufacturing the semiconductor device according to the second embodiment in order of processes subsequent to FIG. 25. FIG. 27 is a schematic cross-sectional view showing the method of manufacturing the semiconductor device according to the second embodiment in order of processes subsequent to FIG. 26. FIG. 28 is a schematic cross-sectional view showing the method of manufacturing the semiconductor device according to the second embodiment in order of processes subsequent to FIG. 27. It is a schematic sectional drawing which shows the manufacturing method of the semiconductor device by 3rd Embodiment in order of a process. FIG. 30 is a schematic cross-sectional view showing the method of manufacturing the semiconductor device according to the third embodiment in order of processes subsequent to FIG. 29. FIG. 31 is a schematic cross-sectional view subsequent to FIG. 30, showing the method for manufacturing the semiconductor device according to the third embodiment in the order of steps. FIG. 32 is a schematic cross-sectional view showing the method of manufacturing the semiconductor device according to the third embodiment in the order of steps, following FIG. 31. FIG. 33 is a schematic cross-sectional view subsequent to FIG. 32 showing the method of manufacturing the semiconductor device according to the third embodiment in order of steps. FIG. 34 is a schematic cross-sectional view showing the method for manufacturing the semiconductor device according to the third embodiment in the order of processes, following FIG. 33; FIG. 35 is a schematic cross-sectional view showing the method of manufacturing the semiconductor device according to the third embodiment in order of processes subsequent to FIG. 34. FIG. 36 is a schematic cross-sectional view subsequent to FIG. 35, showing the method for manufacturing the semiconductor device according to the third embodiment in the order of steps. FIG. 37 is a schematic cross-sectional view showing the manufacturing method of the semiconductor device according to the third embodiment in the order of steps, following FIG. 36; FIG. 38 is a schematic cross-sectional view subsequent to FIG. 37, showing the method for manufacturing the semiconductor device according to the third embodiment in order of processes. FIG. 39 is a schematic cross-sectional view subsequent to FIG. 38 illustrating the method for manufacturing the semiconductor device according to the third embodiment in the order of steps. FIG. 40 is a schematic cross-sectional view showing the method of manufacturing the semiconductor device according to the third embodiment in the order of steps, following FIG. 39. FIG. 41 is a schematic cross-sectional view showing the method of manufacturing the semiconductor device according to the third embodiment in order of processes subsequent to FIG. 40. It is a connection diagram which shows the PFC circuit by 4th Embodiment. It is a connection diagram which shows schematic structure of the power supply device by 5th Embodiment. It is a connection diagram which shows schematic structure of the high frequency amplifier by 6th Embodiment.

(First embodiment)
In the present embodiment, a semiconductor device is disclosed in which an AlGaN / GaN HEMT that is a compound semiconductor element as a first element and a diode that is a silicon element as a second element are mixedly mounted.
1 to 15 are schematic cross-sectional views showing the method of manufacturing the semiconductor device according to the first embodiment in the order of steps.

As shown in FIGS. 1 to 3, the element isolation structure 2 is formed on the Si substrate 1.
First, as shown in FIG. 1, a semiconductor substrate, for example, a Si substrate 1 is prepared as a semiconductor region. A silicon oxide film 21 and a silicon nitride film 22 are sequentially formed on the Si substrate 1 to a thickness of about 10 nm and about 148 nm by sputtering or the like. A resist is applied on the silicon nitride film 22 and processed by lithography to form a resist mask 23 having an opening 23 a above the element isolation region of the Si substrate 1.

Next, as shown in FIG. 2, element isolation grooves 1 a are formed in the Si substrate 1.
Specifically, using the resist mask 23, the silicon nitride film 22, the silicon oxide film 21, and the Si substrate 1 are dry etched. As a result, an element isolation trench 1a having a depth of about 380 nm communicating with the openings 21a and 22a of the silicon oxide film 21 and the silicon nitride film 22 is formed at a position aligned with the opening 23a of the resist mask 23 of the Si substrate 1. It is formed.
The resist mask 23 is removed by ashing or wet processing.

Next, as shown in FIG. 3, the element isolation structure 2 is formed.
After the surface of the silicon nitride film 22 is wet oxidized at about 850 ° C. to form a thermal oxide film having a thickness of about 10 nm, the element isolation trench 1a and the openings 21a and 22a are embedded on the thermal oxide film by CVD or the like. A silicon oxide film is deposited to a thickness of about 675 nm. After the silicon oxide film is dry-etched by about 250 nm, the silicon oxide film is polished by chemical-mechanical polishing (CMP) using the silicon nitride film 22 as a polishing stopper. After annealing at about 1000 ° C. for about 30 minutes in a nitrogen (N ₂ ) atmosphere, the silicon oxide film 21 and the silicon nitride film 22 are removed by wet etching. Thus, the element isolation structure 2 is formed in which the element isolation groove 1a of the Si substrate 1 is filled with silicon oxide. Thereafter, the surface of the Si substrate 1 is oxidized with HCl at about 900 ° C. to form a sacrificial oxide film having a thickness of about 10 nm.

  By forming the element isolation structure 2, a second element region 1B of a diode that is a junction element is defined on the Si substrate 1, and at the same time, adjacent to the second element region 1B (right side portion in FIG. 3), AlGaN A first element region 1A of /GaN.HEMT is defined.

Subsequently, as shown in FIG. 4, a P-type diffusion region 3 a is formed in the second element region 1 </ b> B of the Si substrate 1.
Specifically, a resist is applied on the Si substrate 1, and the resist is processed by lithography to form a resist mask 24 having an opening 24a that exposes the second element region 1B of the Si substrate 1.
Using the resist mask 24, a P-type impurity such as B ⁺ is ion-implanted into the surface exposed portion of the Si substrate 1 under conditions of an acceleration energy of about 300 keV and a dose of about 3.0 × 10 ¹³ / cm ² . As a result, a P-type diffusion region 3a is formed in the second element region 1B of the Si substrate 1. The resist mask 24 is removed by ashing or wet processing.

Subsequently, as shown in FIG. 5, an N-type diffusion region 3b is formed in the P-type diffusion region 3a.
Specifically, a resist is applied on the Si substrate 1, and the resist is processed by lithography to form a resist mask 25 having an opening 25a that exposes a part of the P-type diffusion region 3a.
Using the resist mask 25, an N-type impurity, for example, As ⁺ is ion-implanted into the surface exposed portion of the P-type diffusion region 3a under conditions of an acceleration energy of about 160 keV and a dose of about 4.5 × 10 ¹² / cm ² . Thereby, the N-type diffusion region 3b is formed in a part of the P-type diffusion region 3a. The resist mask 25 is removed by ashing or wet processing.
The P-type diffusion region 3a and the N-type diffusion region 3b form an impurity diffusion region 3 that is an impurity diffusion portion.

Subsequently, as shown in FIG. 6, after forming the Si layer 4, the insulating layer 4 a is formed in the second element region 1 </ b> B of the Si layer 4.
Specifically, first, the Si layer 4 is grown on the entire surface of the Si substrate 1 to a thickness of about 500 nm by epitaxial growth.
A resist is applied on the Si layer 4 and processed by lithography to form a resist mask having an opening exposing the second element region 1B of the Si layer 4. Using a resist mask, oxygen (O ⁺ ) is ion-implanted into the surface exposed portion of the Si layer 4 under conditions of an acceleration energy of about 20 keV and a dose of about 2 × 10 ¹⁸ / cm ² . Thereby, the portion of the second element region 1B of the Si layer 4 is altered, and the insulating layer 4a is formed. In FIG. 6 only, the interface between the Si layer 4 and the Si substrate 1 is represented by a broken line.

  Subsequently, as illustrated in FIG. 7, the compound semiconductor multilayer structure 5 is formed on the Si layer 4 including the insulating layer 4 a. The compound semiconductor multilayer structure 5 includes a buffer layer 5a, an electron transit layer 5b, an electron supply layer 5c, and a cap layer 5d.

  In the completed AlGaN / GaN HEMT, during its operation, a two-dimensional carrier gas, here a two-dimensional electron gas (2DEG), is generated near the interface between the electron transit layer 5b and the electron supply layer 5c. The 2DEG is generated based on a difference in lattice constant between the compound semiconductor (here, GaN) of the electron transit layer 5b and the compound semiconductor (here, AlGaN) of the electron supply layer 5c.

Specifically, the following compound semiconductors are grown on the Si layer 4 including the insulating layer 4a by, for example, metal organic vapor phase epitaxy (MOVPE). Instead of the MOVPE method, a molecular beam epitaxy (MBE) method or the like may be used.
On the Si substrate 1, i (tensionally undoped) AlGaN is about 2.6 μm thick, i-GaN is about 1 μm thick, and n-AlGaN (Al composition: 15% to 25%) is 20 nm. N-GaN is successively grown to a thickness of about 2 nm to a thickness of about. Thereby, the buffer layer 5a, the electron transit layer 5b, the electron supply layer 5c, and the cap layer 5d are formed. As the buffer layer, AlN may be used instead of AlGaN, or GaN may be grown at a low temperature.

  As growth conditions for AlN, GaN, AlGaN, and GaN, a mixed gas of trimethylaluminum gas, trimethylgallium gas, and ammonia gas is used as a source gas. Depending on the compound semiconductor layer to be grown, whether or not to supply trimethylaluminum gas, which is an Al source gas, and trimethylgallium gas, which is a Ga source gas, is appropriately set. The flow rate of ammonia gas, which is a common raw material, is about 100 ccm to 10 LM. The growth pressure is about 50 Torr to 300 Torr, and the growth temperature is about 1000 ° C. to 1200 ° C.

When growing GaN and AlGaN as n-type, for example, SiH ₄ gas containing Si as an n-type impurity is added to the source gas at a predetermined flow rate, and Si is doped into GaN and AlGaN. The doping concentration of Si is about 1 × 10 ¹⁸ / cm ^{3 to} about 1 × 10 ²⁰ / cm ³ , for example, about 5 × 10 ¹⁸ / cm ³ .

  Subsequently, as shown in FIG. 8, an insulating film 6 is deposited to a thickness of about 300 nm on the compound semiconductor multilayer structure 5 by a CVD method or the like.

Subsequently, as shown in FIG. 9, conductive plugs 7A and 7B are formed in the second element region 1B.
Specifically, first, the insulating film 6 is processed by lithography and dry etching to form a hard mask that opens a portion where the conductive plug is to be formed in the insulating film 6.
The compound semiconductor multilayer structure 5 and the insulating layer 4a are dry-etched using a hard mask. Thereby, an opening 7a exposing a part of the surface of the P-type diffusion region 3a and an opening 7b exposing a part of the surface of the N-type diffusion region 3b are formed in the insulating layer 4a and the compound semiconductor multilayer structure 5. The The insulating film 6 used as the hard mask is removed by wet etching or the like.

Next, a base film 7c is formed on the compound semiconductor multilayer structure 5 so as to cover the inner wall surfaces of the openings 7a and 7b. The base film 7c is formed by sequentially forming, for example, Ti and TiN with a thickness of about 10 nm and about 7 nm by sputtering or the like. A conductive material 7d is deposited so as to fill the openings 7a and 7b through the base film 7c. The conductive material 7d is deposited, for example, by CVD to such a thickness that the W is embedded in the openings 7a and 7b. The conductive material 7d and the base film 7c are polished by CMP using the cap layer 5d of the compound semiconductor multilayer structure 5 as an etching stopper.
As described above, conductive plugs 7A and 7B are formed which are connected to the P-type diffusion region 3a and the N-type diffusion region 3b and are conductive portions formed by filling the openings 7a and 7b with the conductive material 7d through the base film 7c. The

Subsequently, as shown in FIG. 10, an electrode recess 5A is formed in the first element region 1A.
More specifically, a portion where the gate electrode of the compound semiconductor multilayer structure 5 is to be formed in the first element region 1A is processed by lithography and dry etching. Dry etching using a chlorine-based gas and SF _x based gas, for example, the cap layer 5d halfway the depth of penetration by the electron supply layer 5c, is executed until total 15nm~20nm about depth. The etched portion of the electron supply layer 5c remains with a thickness of about 2 nm to 7 nm. The resist used for lithography is removed by ashing or wet processing. Thus, the electrode recess 5A is formed in the first element region 1A.

Subsequently, as shown in FIG. 11, the 2DEG blocking structure 8 is formed in the second element region 1B.
A 2DEG blocking structure 8 that electrically blocks 2DEG generated in the compound semiconductor multilayer structure 5 is formed for each of the conductive plugs 7A and 7B in the second element region 1B. Specifically, a resist is applied to the entire surface, and the resist is processed by lithography to form a resist mask that opens a portion where the 2DEG blocking structure is to be formed. Using this resist mask, an element (for example, Ar, B, etc.) that can destroy the crystal structure of the compound semiconductor multilayer structure 5 (GaN, AlGaN) so as to surround each of the conductive plugs 7A, 7B, Ar here, It introduces to a region deeper than the 2DEG generation site. Specifically, Ar is continuously applied under conditions of an acceleration energy of about 170 keV and a dose of about 5.0 × 10 ¹³ / cm ² , an acceleration energy of about 100 keV and a dose of about 1.0 × 10 ¹³ / cm ^2. Inject. By the implantation of Ar, the crystal structure of GaN and AlGaN at the implantation site is destroyed and 2DEG disappears. As described above, the 2DEG blocking structure 8 that is a carrier blocking portion that electrically blocks the conductive plugs 7A and 7B for each of the conductive plugs 7A and 7B is formed.
The resist mask is removed by ashing or wet processing.

In the present embodiment, a configuration in which the compound semiconductor multilayer structure 5 is shared by the first element region 1A and the second element region 1B is adopted. In the first element region 1 </ b> A, a channel is formed using 2DEG generated in the compound semiconductor stacked structure 5. In the second element region 1B, the compound semiconductor multilayer structure 5 is substantially used as a so-called interlayer insulating film. In the latter case, the conductors in the compound semiconductor multilayer structure 5 in the second element region 1B, here, the conductive plugs 7A and 7B, 2DEG generated in the compound semiconductor multilayer structure 5 for each conductor is cut off, and each conductor is separated. It is necessary to prevent short circuit. Therefore, in the present embodiment, the 2DEG blocking structure 8 is formed as described above. As a result, it is possible to reliably obtain the effectiveness of the conductive plugs 7A and 7B as the respective conductors, and the new material and the new process are reduced by using the compound semiconductor multilayer structure 5 as the interlayer insulating film in the second element region 1B. To achieve the configuration.
Note that the 2DEG blocking structure 8 may be formed prior to the formation of the conductive plugs 7A and 7B.

Subsequently, as shown in FIG. 12, an insulating film 9 having an opening 9a is formed.
Specifically, for example, SiN is deposited to a thickness of about 200 nm on the compound semiconductor multilayer structure 5 by a CVD method or the like to form the insulating film 9. The insulating film 9 is processed by lithography and dry etching, and an opening 9a wider than the electrode recess 5A is formed at a position aligned with the electrode recess 5A of the insulating film 9. By dry etching, SiN in the electrode recess 5A is also removed, and the opening 9a communicates with the electrode recess 5A to form an electrode groove.

Subsequently, as shown in FIG. 13, the gate electrode 12 is formed in the first element region 1 </ b> A via the gate insulating film 11.
Specifically, first, the gate insulating film 11 is formed on the insulating film 9 so as to cover the inner wall surface of the electrode groove. For example, Al ₂ O ₃ is deposited to a thickness of about 20 nm by an atomic layer deposition (ALD method). Thereby, the gate insulating film 11 is formed.
Al ₂ O ₃ may be deposited by, for example, a plasma CVD method or a sputtering method instead of the ALD method. Further, instead of depositing Al ₂ O ₃ , Al nitride or oxynitride may be used. In addition, an oxide, nitride, oxynitride of Si, Hf, Zr, Ti, Ta, and W, or an appropriate selection thereof may be deposited in multiple layers to form a gate insulating film. .

  Next, an electrode material, for example, Ti, TiN, TaN, etc., such as TaN having a thickness of about 50 nm and Al having a thickness of about 400 nm are deposited on the gate insulating film 11 by sputtering or the like. The electrode material and the gate insulating film 11 are processed by lithography and dry etching. The resist used for lithography is removed by ashing or wet processing. As described above, the gate electrode 12 is formed by filling the electrode trench with the electrode material via the gate insulating film 11 and projecting upward from the surface of the insulating film 9.

Subsequently, as shown in FIG. 14, after the insulating film 13 is formed, electrode recesses 14a, 14b, 14c, and 14d are formed.
Specifically, first, for example, SiO ₂ is deposited on the insulating film 9 to a thickness for embedding the gate electrode 12 by a CVD method or the like. Thereby, the insulating film 13 is formed.
Next, the insulating films 9 and 13 are processed by lithography and dry etching. As a result, electrode recesses 14a, 14b, 14c, and 14d are simultaneously formed in the insulating films 9 and 13. The electrode recesses 14a and 14b are formed in the first element region 1A of the insulating films 9 and 13, and the formation sites of the source electrode and the drain electrode of the compound semiconductor multilayer structure 5 are exposed at the bottom surfaces, respectively. The electrode recesses 14c and 14d are formed in the second element region 1B of the insulating films 9 and 13, and the conductive plugs 7A and 7B are exposed at the bottom surfaces, respectively.

Subsequently, as shown in FIG. 15, the source electrode 16a, the drain electrode 16b, the anode electrode 16c, and the cathode electrode 16d having the respective underlying films 15a, 15b, 15c, and 15d are formed simultaneously.
Specifically, for example, Ti is formed to a thickness of about 25 nm on the insulating film 13 by sputtering or the like so as to cover the inner wall surfaces of the electrode recesses 14a to 14d. Subsequently, for example, Al is deposited to a thickness of about 300 nm so as to embed the electrode recesses 14a to 14d through the deposited Ti by sputtering or the like. Then, Al and Ti are processed by lithography and dry etching. As a result, the source electrode 16a having the base film 15a and the drain electrode 16b having the base film 15b are formed in the first element region 1A. At the same time, an anode electrode 16c having a base film 15c and a cathode electrode 16d having a base film 15d are formed in the second element region 1B. The source electrode 16 a and the drain electrode 16 b are in ohmic contact with the compound semiconductor multilayer structure 5 on both sides of the gate electrode 12. The anode electrode 16c and the cathode electrode 16d are electrically connected to the conductive plugs 7A and 7B, and are electrically connected to the P-type diffusion region 3a and the N-type diffusion region 3b through the conductive plugs 7A and 7B.

  In this embodiment, the source electrode 16a and the drain electrode 16b are formed in the first element region 1A, and the anode electrode 16c and the cathode electrode 16d are formed in the same layer in the same layer and at the same height in the second element region 1B. It is formed. In this manner, each electrode (wiring) can be formed with good flatness with few steps as much as possible without causing an extra step, and a highly reliable semiconductor device with high processing accuracy is realized.

  Thereafter, various processes such as formation of an upper insulating film and formation of various wirings are performed. Thus, a semiconductor device is formed in which the first element region 1A is formed with an AlGaN / GaN.HEMT as the first element, and the second element region 1B is formed with a diode as the second element. .

  As described above, according to the present embodiment, the compound semiconductor multilayer structure 5 is shared by the compound semiconductor element AlGaN / GaN HEMT and the silicon element diode. By adopting this configuration, a highly reliable semiconductor device capable of reliably obtaining both the function of the HEMT and the function of the diode can be realized even though it is manufactured with a minimum number of processes by reducing new materials and new processes. To do.

(Second Embodiment)
In the present embodiment, a semiconductor device in which an AlGaN / GaN HEMT that is a compound semiconductor element as a first element and a bipolar transistor that is a silicon element as a second element is mounted together is disclosed.
16 to 29 are schematic cross-sectional views illustrating the method of manufacturing the semiconductor device according to the second embodiment in the order of steps.

  First, similarly to the first embodiment, the steps of FIGS. 1 to 3 are executed to form the element isolation structure 2 on the Si substrate 1.

Subsequently, as shown in FIG. 16, a P-type diffusion region 31 a is formed in the second element region 1 </ b> B of the Si substrate 1.
Specifically, a resist is applied on the Si substrate 1 and the resist is processed by lithography to form a resist mask 51 having an opening 51a that exposes the second element region 1B of the Si substrate 1.
Using the resist mask 51, a P-type impurity, for example, B ⁺ is ion-implanted into the exposed surface of the Si substrate 1 under conditions of an acceleration energy of about 300 keV and a dose of about 3.0 × 10 ¹³ / cm ² . As a result, a P-type diffusion region 31a is formed in the second element region 1B of the Si substrate 1. The resist mask 51 is removed by an ashing process or a wet process.

Subsequently, as shown in FIG. 17, an N-type diffusion region 31b is formed in the P-type diffusion region 31a.
Specifically, a resist is applied on the Si substrate 1, and the resist is processed by lithography to form a resist mask 52 having an opening 52a that exposes a part of the P-type diffusion region 31a.
Using the resist mask 52, an N-type impurity, for example, As ⁺ is ion-implanted into the surface exposed portion of the P-type diffusion region 31a under conditions of an acceleration energy of about 160 keV and a dose of about 4.5 × 10 ¹² / cm ² . Thereby, an N-type diffusion region 31b is formed in a part of the P-type diffusion region 31a. The resist mask 52 is removed by ashing or wet processing.

Subsequently, as shown in FIG. 18, a P-type diffusion region 31c is formed in the N-type diffusion region 31b.
Specifically, a resist is applied on the Si substrate 1, and the resist is processed by lithography to form a resist mask 53 having an opening 53a that exposes a part of the N-type diffusion region 31b.
Using the resist mask 53, a P-type impurity, for example, B ⁺ is ion-implanted into the surface exposed portion of the N-type diffusion region 31b under conditions of an acceleration energy of about 70 keV and a dose of about 3.0 × 10 ¹³ / cm ² . Thereby, the P-type diffusion region 31c is formed in a part of the N-type diffusion region 31b. The resist mask 53 is removed by an ashing process or a wet process.
The P-type diffusion region 31a, the N-type diffusion region 31b, and the P-type diffusion region 31c form an impurity diffusion region 31 that is an impurity diffusion portion.

Subsequently, as shown in FIG. 19, after the Si layer 32 is formed, an insulating layer 32 a is formed in the second element region 1 </ b> B of the Si layer 32.
Specifically, first, the Si layer 32 is grown on the entire surface of the Si substrate 1 to a thickness of about 500 nm by epitaxial growth.
A resist is applied on the Si layer 32, and the resist is processed by lithography to form a resist mask having an opening that exposes the second element region 1B of the Si layer 32. Using a resist mask, oxygen (O ⁺ ) is ion-implanted into the surface exposed portion of the Si layer 32 under conditions of an acceleration energy of about 20 keV and a dose of about 2 × 10 ¹⁸ / cm ² . Thereby, the portion of the second element region 1B of the Si layer 32 is altered, and the insulating layer 32a is formed. In FIG. 19 only, the interface between the Si layer 32 and the Si substrate 1 is represented by a broken line.

  Subsequently, as illustrated in FIG. 20, a compound semiconductor multilayer structure 33 is formed on the Si layer 32 including the insulating layer 32a. The compound semiconductor multilayer structure 33 includes a buffer layer 33a, an electron transit layer 33b, an electron supply layer 33c, and a cap layer 33d.

  In the completed AlGaN / GaN HEMT, during its operation, a two-dimensional carrier gas, here a two-dimensional electron gas (2DEG), is generated near the interface between the electron transit layer 33b and the electron supply layer 33c. The 2DEG is generated based on the difference in lattice constant between the compound semiconductor (here, GaN) of the electron transit layer 33b and the compound semiconductor (here, AlGaN) of the electron supply layer 33c.

Specifically, the following compound semiconductors are grown on the Si layer 32 including the insulating layer 32a by, for example, the MOVPE method. The MBE method or the like may be used instead of the MOVPE method.
On the Si substrate 1, i (tensionally undoped) AlGaN is about 2.6 μm thick, i-GaN is about 1 μm thick, and n-AlGaN (Al composition: 15% to 25%) is 20 nm. N-GaN is successively grown to a thickness of about 2 nm to a thickness of about. Thereby, the buffer layer 33a, the electron transit layer 33b, the electron supply layer 33c, and the cap layer 33d are formed. As the buffer layer, AlN may be used instead of AlGaN, or GaN may be grown at a low temperature.

  As growth conditions for AlN, GaN, AlGaN, and GaN, a mixed gas of trimethylaluminum gas, trimethylgallium gas, and ammonia gas is used as a source gas. Depending on the compound semiconductor layer to be grown, whether or not to supply trimethylaluminum gas, which is an Al source gas, and trimethylgallium gas, which is a Ga source gas, is appropriately set. The flow rate of ammonia gas, which is a common raw material, is about 100 ccm to 10 LM. The growth pressure is about 50 Torr to 300 Torr, and the growth temperature is about 1000 ° C. to 1200 ° C.

When growing GaN and AlGaN as n-type, for example, SiH ₄ gas containing Si as an n-type impurity is added to the source gas at a predetermined flow rate, and Si is doped into GaN and AlGaN. The doping concentration of Si is about 1 × 10 ¹⁸ / cm ^{3 to} about 1 × 10 ²⁰ / cm ³ , for example, about 5 × 10 ¹⁸ / cm ³ .

  Subsequently, as shown in FIG. 21, an insulating film 34 is deposited to a thickness of about 400 nm on the compound semiconductor multilayer structure 33 by a CVD method or the like.

Subsequently, as shown in FIG. 22, conductive plugs 35A, 35B, and 35C are formed in the second element region 1B.
Specifically, first, the insulating film 34 is processed by lithography and dry etching to form a hard mask that opens a portion where the conductive plug is to be formed in the insulating film 34.
The compound semiconductor multilayer structure 33 and the insulating layer 32a are dry-etched using a hard mask. Thus, the opening 35a exposing a part of the surface of the P-type diffusion region 31a, the opening 35b exposing a part of the surface of the N-type diffusion region 31b, and the P-type in the insulating layer 32a and the compound semiconductor multilayer structure 33. An opening 35c exposing a part of the surface of the diffusion region 31c is formed. The insulating film 34 used as the hard mask is removed by wet etching or the like.

Next, a base film 35d is formed on the compound semiconductor multilayer structure 33 so as to cover the inner wall surfaces of the openings 35a, 35b, and 35c. The base film 35d is formed by sequentially forming, for example, Ti and TiN with a thickness of about 10 nm and about 7 nm by sputtering or the like. A conductive material 35e is deposited so as to fill the openings 35a to 35c through the base film 35d. The conductive material 35e is deposited, for example, by CVD to a thickness that fills the openings 35a to 35c. The conductive material 35e and the base film 35d are polished by CMP using the cap layer 33d of the compound semiconductor multilayer structure 33 as an etching stopper.
As described above, the conductive portion is connected to the P-type diffusion region 31a, the N-type diffusion region 31b, and the P-type diffusion region 31c, and is a conductive portion formed by filling the openings 35a to 35c with the conductive material 35e through the base film 35d. Plugs 35A, 35B, and 35C are formed.

Subsequently, as shown in FIG. 23, an electrode recess 33A is formed in the first element region 1A.
More specifically, a portion where the gate electrode of the compound semiconductor multilayer structure 33 is to be formed in the first element region 1A is processed by lithography and dry etching. Dry etching using a chlorine-based gas and SF _x based gas, for example, the cap layer 33d halfway the depth of penetration by the electron supply layer 33c, is executed until total 15nm~20nm about depth. The etched portion of the electron supply layer 33c remains only about 2 nm to 7 nm in thickness. The resist used for lithography is removed by ashing or wet processing. Thus, the electrode recess 33A is formed in the first element region 1A.

Subsequently, as shown in FIG. 24, a 2DEG blocking structure 36 is formed in the second element region 1B.
A 2DEG blocking structure 36 that electrically blocks 2DEG generated in the compound semiconductor multilayer structure 33 is formed for each of the conductive plugs 35A, 35B, and 35C in the second element region 1B. Specifically, a resist is applied to the entire surface, and the resist is processed by lithography to form a resist mask that opens a portion where the 2DEG blocking structure is to be formed. An element (for example, Ar, B, etc.) that can destroy the crystal structure of the compound semiconductor multilayer structure 33 (GaN, AlGaN) so as to surround the conductive plugs 35A, 35B, 35C by using this resist mask, for example, Ar To a region deeper than the 2DEG generation site. Specifically, Ar is continuously applied under conditions of an acceleration energy of about 170 keV and a dose of about 5.0 × 10 ¹³ / cm ² , an acceleration energy of about 100 keV and a dose of about 1.0 × 10 ¹³ / cm ^2. Inject. By the implantation of Ar, the crystal structure of GaN and AlGaN at the implantation site is destroyed and 2DEG disappears. As described above, the 2DEG blocking structure 36 that is a carrier blocking portion that electrically blocks the conductive plugs 35A, 35B, and 35C from the 2DEG for each of the conductive plugs 35A, 35B, and 35C is formed.
The resist mask is removed by ashing or wet processing.

In the present embodiment, a configuration in which the compound semiconductor multilayer structure 33 is shared by the first element region 1A and the second element region 1B is adopted. In the first element region 1 </ b> A, a channel is formed using 2DEG generated in the compound semiconductor stacked structure 33. In the second element region 1B, the compound semiconductor multilayer structure 33 is substantially used as a so-called interlayer insulating film. In the latter case, the conductors in the compound semiconductor multilayer structure 33 in the second element region 1B, here, the conductive plugs 35A to 35C are cut off 2DEG generated in the compound semiconductor multilayer structure 33 for each conductor, and between the conductors. It is necessary to prevent short circuit. Therefore, in the present embodiment, the 2DEG blocking structure 36 is formed as described above. As a result, the conductive plugs 35A to 35C can be effectively obtained as the respective conductors, and the new material and the new process can be reduced by using the compound semiconductor multilayer structure 33 as the interlayer insulating film in the second element region 1B. To achieve the configuration.
Note that the 2DEG blocking structure 36 may be formed prior to the formation of the conductive plugs 35A to 35C.

Subsequently, as shown in FIG. 25, an insulating film 37 having an opening 37a is formed.
Specifically, for example, SiN is deposited to a thickness of about 200 nm on the compound semiconductor multilayer structure 33 by a CVD method or the like to form the insulating film 37. The insulating film 37 is processed by lithography and dry etching, and an opening 37a wider than the electrode recess 33A is formed at a position aligned with the electrode recess 33A of the insulating film 37. By dry etching, SiN in the electrode recess 33A is also removed, and the opening 37a communicates with the electrode recess 33A to form an electrode groove.

Subsequently, as shown in FIG. 26, a gate electrode 39 is formed in the first element region 1A via a gate insulating film.
Specifically, first, a gate insulating film 38 is formed on the insulating film 37 so as to cover the inner wall surface of the electrode groove. For example, Al ₂ O ₃ is deposited to a thickness of about 20 nm by an atomic layer deposition (ALD method). Thereby, the gate insulating film 38 is formed.
Al ₂ O ₃ may be deposited by, for example, a plasma CVD method or a sputtering method instead of the ALD method. Further, instead of depositing Al ₂ O ₃ , Al nitride or oxynitride may be used. In addition, an oxide, nitride, oxynitride of Si, Hf, Zr, Ti, Ta, and W, or an appropriate selection thereof may be deposited in multiple layers to form a gate insulating film. .

  Next, an electrode material, for example, Ti, TiN, TaN, etc., such as TaN having a thickness of about 50 nm and Al having a thickness of about 400 nm are deposited on the gate insulating film 38 by sputtering or the like. The electrode material and the gate insulating film 38 are processed by lithography and dry etching. The resist used for lithography is removed by ashing or wet processing. As described above, the gate electrode 39 is formed in which the electrode trench is filled with the electrode material through the gate insulating film 38 and protrudes upward from the surface of the insulating film 37.

Subsequently, as shown in FIG. 27, after the insulating film 41 is formed, electrode recesses 42a, 42b, 42c, 42d, and 42e are formed.
Specifically, first, for example, SiN is deposited on the insulating film 37 by a CVD method or the like to a thickness for embedding the gate electrode 39. Thereby, the insulating film 41 is formed.
Next, the insulating films 37 and 41 are processed by lithography and dry etching. Thereby, electrode recesses 42a, 42b, 42c, 42d, and 42e are simultaneously formed in the insulating films 37 and 41. The electrode recesses 42a and 42b are formed in the first element region 1A of the insulating films 37 and 41, and the formation regions of the source electrode and the drain electrode of the compound semiconductor multilayer structure 33 are exposed on the bottom surface, respectively. The electrode recesses 42c, 42d, and 42e are formed in the second element region 1B of the insulating films 37 and 41, and the conductive plugs 35A, 35B, and 35C are exposed on the bottom surfaces, respectively.

Subsequently, as shown in FIG. 28, the source electrode 44a, the drain electrode 44b, the collector electrode 44c, the base electrode 44d, and the emitter electrode 44e having the respective underlying films 43a, 43b, 43c, 43d, and 43e are simultaneously formed.
Specifically, for example, Ti is formed to a thickness of about 25 nm on the insulating film 41 by sputtering or the like so as to cover the inner wall surfaces of the electrode recesses 42a to 42e. Subsequently, for example, Al is deposited to a thickness of about 300 nm so as to embed the electrode recesses 42a to 42e through the deposited Ti by sputtering or the like. Then, Al and Ti are processed by lithography and dry etching. As a result, the source electrode 44a having the base film 43a and the drain electrode 44b having the base film 43b are formed in the first element region 1A. At the same time, a collector electrode 44c having a base film 43c, a base electrode 44d having a base film 43d, and an emitter electrode 44e having a base film 43e are formed in the second element region 1B. The source electrode 44 a and the drain electrode 44 b are in ohmic contact with the compound semiconductor multilayer structure 33 on both sides of the gate electrode 39. The collector electrode 44c, the base electrode 44d, and the emitter electrode 44e are electrically connected to the conductive plugs 35A, 35B, and 35C, and the P-type diffusion region 31a, the N-type diffusion region 31b, and P are connected through the conductive plugs 35A, 35B, and 35C. Conductive with the mold diffusion region 31c.

  In this embodiment, the source electrode 44a and the drain electrode 44b are formed in the first element region 1A, and the collector electrode 44c, the base electrode 44d, and the emitter electrode 44e are formed in the same flat surface in the same process in the second element region 1B. Formed. In this manner, each electrode (wiring) can be formed with good flatness with few steps as much as possible without causing an extra step, and a highly reliable semiconductor device with high processing accuracy is realized.

  Thereafter, various processes such as formation of an upper insulating film and formation of various wirings are performed. As described above, a semiconductor device is formed in which the first element region 1A is formed with an AlGaN / GaN HEMT as the first element, and the second element region 1B is formed with a bipolar transistor as the second element. The

  As described above, according to the present embodiment, the compound semiconductor multilayer structure 33 is shared by the compound semiconductor element AlGaN / GaN HEMT and the silicon element bipolar transistor. By adopting this configuration, a highly reliable semiconductor device capable of reliably obtaining both the function of the HEMT and the function of the bipolar transistor even though it is manufactured with a minimum number of processes by reducing new materials and new processes. Realize.

(Third embodiment)
In this embodiment, a semiconductor device in which an AlGaN / GaN HEMT that is a compound semiconductor element as a first element and a so-called vertical MIS transistor that is a silicon element as a second element is mounted together is disclosed.
29 to 41 are schematic cross-sectional views showing the method of manufacturing the semiconductor device according to the third embodiment in the order of steps.

  First, similarly to the first embodiment, the steps of FIGS. 1 to 3 are executed to form the element isolation structure 2 on the Si substrate 1.

Subsequently, as shown in FIG. 29, an N-type diffusion region 61 a is formed in the second element region 1 </ b> B of the Si substrate 1.
Specifically, a resist is applied on the Si substrate 1, and the resist is processed by lithography to form a resist mask 81 having an opening 81a that exposes the second element region 1B of the Si substrate 1.
Using the resist mask 81, an N-type impurity such as As ⁺ is ion-implanted into the surface exposed portion of the Si substrate 1 under the conditions of an acceleration energy of about 160 keV and a dose of about 4.5 × 10 ¹² / cm ² . As a result, an N-type diffusion region 61a is formed in the second element region 1B of the Si substrate 1. The resist mask 81 is removed by ashing or wet processing.

Subsequently, as shown in FIG. 30, a P-type diffusion region 61b is formed in the N-type diffusion region 61a.
Specifically, a resist is applied on the Si substrate 1, and the resist is processed by lithography to form a resist mask 82 having an opening 82a that exposes a part of the N-type diffusion region 61a.
Using the resist mask 82, a P-type impurity, for example, B ⁺ is ion-implanted into the surface exposed portion of the N-type diffusion region 61a under conditions of an acceleration energy of about 300 keV and a dose of about 3.0 × 10 ¹³ / cm ² . Thereby, a P-type diffusion region 61b is formed in a part of the N-type diffusion region 61a. The resist mask 82 is removed by an ashing process or a wet process.

Subsequently, as shown in FIG. 31, an N-type diffusion region 61c is formed in the P-type diffusion region 61b.
Specifically, a resist is applied on the Si substrate 1, and the resist is processed by lithography to form a resist mask 83 having an opening 83a that exposes a part of the P-type diffusion region 61b.
Using the resist mask 83, a type impurity such as As ⁺ is ion-implanted into the surface exposed portion of the P-type diffusion region 61b under conditions of an acceleration energy of about 70 keV and a dose of about 4.5 × 10 ¹² / cm ² . Thereby, an N-type diffusion region 61c is formed in a part of the P-type diffusion region 61b. The resist mask 83 is removed by ashing or wet processing.
The N-type diffusion region 61a, the P-type diffusion region 61b, and the N-type diffusion region 61c form an impurity diffusion region 61 that is an impurity diffusion portion.

Subsequently, as shown in FIG. 32, after forming the Si layer 62, an insulating layer 62 a is formed in the second element region 1 </ b> B of the Si layer 62.
Specifically, first, the Si layer 62 is grown on the entire surface of the Si substrate 1 to a thickness of about 500 nm by epitaxial growth.
A resist is applied onto the Si layer 62, and the resist is processed by lithography to form a resist mask having an opening that exposes the second element region 1B of the Si layer 62. Using a resist mask, oxygen (O ⁺ ) is ion-implanted into the surface exposed portion of the Si layer 62 under conditions of an acceleration energy of about 20 keV and a dose of about 2 × 10 ¹⁸ / cm ² . As a result, the portion of the second element region 1B of the Si layer 62 is altered and the insulating layer 62a is formed. In FIG. 32 only, the interface between the Si layer 62 and the Si substrate 1 is represented by a broken line.

  Subsequently, as shown in FIG. 33, a compound semiconductor multilayer structure 63 is formed on the Si layer 62 including the insulating layer 62a. The compound semiconductor multilayer structure 63 includes a buffer layer 63a, an electron transit layer 63b, an electron supply layer 63c, and a cap layer 63d.

  In the completed AlGaN / GaN HEMT, during its operation, a two-dimensional carrier gas, here a two-dimensional electron gas (2DEG), is generated near the interface between the electron transit layer 63b and the electron supply layer 63c. This 2DEG is generated based on the difference in lattice constant between the compound semiconductor (here, GaN) of the electron transit layer 63b and the compound semiconductor (here, AlGaN) of the electron supply layer 63c.

Specifically, the following compound semiconductors are grown on the Si layer 62 including the insulating layer 62a by, for example, the MOVPE method. The MBE method or the like may be used instead of the MOVPE method.
On the Si substrate 1, i (tensionally undoped) AlGaN is about 2.6 μm thick, i-GaN is about 1 μm thick, and n-AlGaN (Al composition: 15% to 25%) is 20 nm. N-GaN is successively grown to a thickness of about 2 nm to a thickness of about. Thereby, the buffer layer 63a, the electron transit layer 63b, the electron supply layer 63c, and the cap layer 63d are formed. As the buffer layer, AlN may be used instead of AlGaN, or GaN may be grown at a low temperature.

  As growth conditions for AlN, GaN, AlGaN, and GaN, a mixed gas of trimethylaluminum gas, trimethylgallium gas, and ammonia gas is used as a source gas. The presence / absence and flow rate of trimethylaluminum gas as an Al source and trimethylgallium gas as a Ga source are appropriately set according to the compound semiconductor layer to be grown. The flow rate of ammonia gas, which is a common raw material, is about 100 ccm to 10 LM. The growth pressure is about 50 Torr to 300 Torr, and the growth temperature is about 1000 ° C. to 1200 ° C.

When growing GaN and AlGaN as n-type, for example, SiH ₄ gas containing Si as an n-type impurity is added to the source gas at a predetermined flow rate, and Si is doped into GaN and AlGaN. The doping concentration of Si is about 1 × 10 ¹⁸ / cm ^{3 to} about 1 × 10 ²⁰ / cm ³ , for example, about 5 × 10 ¹⁸ / cm ³ .

Subsequently, as shown in FIG. 34, conductive plugs 65A and 65B are formed in the second element region 1B.
Specifically, first, an insulating film is formed on the compound semiconductor multilayer structure 63 by a CVD method or the like. The insulating film is processed by lithography and dry etching to form a hard mask that opens a portion where the conductive plug of the insulating film is to be formed.
The compound semiconductor multilayer structure 63 and the insulating layer 62a are dry-etched using a hard mask. Thus, an opening 65a exposing a part of the surface of the N-type diffusion region 61c and an opening 65b exposing a part of the surface of the N-type diffusion region 61a are formed in the insulating layer 62a and the compound semiconductor multilayer structure 63. The The insulating film used as the hard mask is removed by wet etching or the like.

Next, a base film 65c is formed on the compound semiconductor multilayer structure 63 so as to cover the inner wall surfaces of the openings 65a and 65b. The base film 65c is formed by sequentially forming, for example, Ti and TiN with a thickness of about 10 nm and about 7 nm by sputtering or the like. A conductive material 65d is deposited so as to fill the openings 65a and 65b through the base film 65c. The conductive material 65d is deposited, for example, by CVD to a thickness that fills the openings 65a and 65b. The conductive material 65d and the base film 65c are polished by CMP using the cap layer 63d of the compound semiconductor multilayer structure 63 as an etching stopper.
Thus, conductive plugs 65A and 65B, which are conductive portions connected to the N-type diffusion regions 61c and 61a and filling the openings 65a and 65b with the conductive material 65d through the base film 65c, are formed.

Subsequently, as shown in FIG. 35, a buried gate structure 66 is formed in the second element region 1B.
Specifically, first, an insulating film is formed on the compound semiconductor multilayer structure 63 by a CVD method or the like. The insulating film is processed by lithography and dry etching to form a hard mask that opens a portion where the insulating gate embedded gate structure is to be formed.
The compound semiconductor multilayer structure 63 and the insulating layer 62a are dry-etched using a hard mask. Thereby, an opening 66a etched to a predetermined depth of the P-type diffusion region 61b (depth from the surface of the P-type diffusion region 61b) is formed in the insulating layer 62a and the compound semiconductor multilayer structure 63. The insulating film used as the hard mask is removed by wet etching or the like.

Next, a gate insulating film 67 is formed on the compound semiconductor multilayer structure 63 so as to cover the inner wall surface of the opening 66a. The gate insulating film 67 is formed, for example, by depositing SiO ₂ to a thickness of about 14 nm by a CVD method or the like.
Next, a base film 66 b is formed on the compound semiconductor multilayer structure 63 so as to cover the inner wall surface of the opening 66 a through the gate insulating film 67. The base film 66b is formed by sequentially forming, for example, Ti and TiN with a thickness of about 10 nm and about 7 nm by sputtering or the like. A conductive material 66c is deposited so as to fill the opening 66a through the gate insulating film 67 and the base film 66b. The conductive material 66c is deposited by a CVD method or the like to a thickness in which, for example, polycrystalline silicon fills the opening 66a. The conductive material 66c, the base film 66b, and the gate insulating film 67 are polished by CMP using the cap layer 63d of the compound semiconductor multilayer structure 63 as an etching stopper.
As described above, the buried gate structure 66 connected to the P-type diffusion region 61b and filling the opening 66a with the conductive material 66c through the gate insulating film 67 and the base film 66b is formed.

  In the vertical MIS transistor formed in the second element region 1B, a channel is configured with a P-type diffusion region 61b between the N-type diffusion region 61c and the N-type diffusion region 61a. The conductive material 66c faces the P-type diffusion region 61b serving as a channel through the gate insulating film 67 on the side surface portion of the buried gate structure 66, and functions as an N-type MIS transistor.

Subsequently, as shown in FIG. 36, an electrode recess 63A is formed in the first element region 1A.
More specifically, a portion where the gate electrode of the compound semiconductor multilayer structure 63 is to be formed in the first element region 1A is processed by lithography and dry etching. Dry etching using a chlorine-based gas and SF _x based gas, for example through the cap layer 63d halfway the depth of the electron supply layer 63c, is executed until total 15nm~20nm about depth. The etched portion of the electron supply layer 63c remains with a thickness of about 2 nm to 7 nm. The resist used for lithography is removed by ashing or wet processing. Thus, the electrode recess 63A is formed in the first element region 1A.

Subsequently, as shown in FIG. 37, a 2DEG blocking structure 68 is formed in the second element region 1B.
For each of the conductive plugs 65A and 65B and the embedded gate structure 66 in the second element region 1B, a 2DEG blocking structure 68 that electrically blocks 2DEG generated in the compound semiconductor stacked structure 63 is formed. Specifically, a resist is applied to the entire surface, and the resist is processed by lithography to form a resist mask that opens a portion where the 2DEG blocking structure is to be formed. Using this resist mask, an element capable of destroying the crystal structure of the compound semiconductor multilayer structure 63 (GaN, AlGaN) is introduced so as to surround each of the conductive plugs 65A, 65B and the embedded gate structure 66. As the element, for example, Ar, B, or the like, here Ar, is used to introduce a region deeper than the 2DEG generation site of the compound semiconductor multilayer structure 63. Specifically, Ar is continuously applied under conditions of an acceleration energy of about 170 keV and a dose of about 5.0 × 10 ¹³ / cm ² , an acceleration energy of about 100 keV and a dose of about 1.0 × 10 ¹³ / cm ^2. Inject. By the implantation of Ar, the crystal structure of GaN and AlGaN at the implantation site is destroyed and 2DEG disappears. As described above, the 2DEG blocking structure 68 that is a carrier blocking portion that electrically blocks the conductive plugs 65A and 65B and the embedded gate structure 66 for each of the conductive plugs 65A and 65B and the embedded gate structure 66 is formed.
The resist mask is removed by ashing or wet processing.

In the present embodiment, a configuration in which the compound semiconductor multilayer structure 63 is shared by the first element region 1A and the second element region 1B is adopted. In the first element region 1 </ b> A, a channel is configured using 2DEG generated in the compound semiconductor stacked structure 63. In the second element region 1B, the compound semiconductor multilayer structure 63 is substantially used as a so-called interlayer insulating film. In the latter case, the conductor in the compound semiconductor multilayer structure 63 in the second element region 1B, here, the conductive plugs 65A and 65B, and the embedded gate structure 66 blocks 2DEG generated in the compound semiconductor multilayer structure 63 for each conductor. It is necessary to prevent a short circuit between the conductors. Therefore, in the present embodiment, the 2DEG blocking structure 68 is formed as described above. As a result, the conductive plugs 65A and 65B and the embedded gate structure 66 can be obtained effectively as the respective conductors, and the compound semiconductor multilayer structure 63 is used as an interlayer insulating film in the second element region 1B. And the structure which reduces a new process is implement | achieved.
The 2DEG blocking structure 68 may be formed prior to the formation of the conductive plugs 65A and 65B and the buried gate structure 66.

Subsequently, as shown in FIG. 38, an insulating film 69 having an opening 69a is formed.
Specifically, for example, SiN is deposited to a thickness of about 200 nm on the compound semiconductor multilayer structure 63 by a CVD method or the like to form an insulating film 69. The insulating film 69 is processed by lithography and dry etching, and an opening 69a wider than the electrode recess 63A is formed in a position aligned with the electrode recess 63A of the insulating film 69. By dry etching, SiN in the electrode recess 63A is also removed, and the opening 69a communicates with the electrode recess 63A to form an electrode groove.

Subsequently, as shown in FIG. 39, a gate electrode 72 is formed in the first element region 1 </ b> A via a gate insulating film 71.
Specifically, first, the gate insulating film 71 is formed on the insulating film 69 so as to cover the inner wall surface of the electrode groove. For example, Al ₂ O ₃ is deposited to a thickness of about 20 nm by an atomic layer deposition (ALD method). Thereby, the gate insulating film 71 is formed.
Al ₂ O ₃ may be deposited by, for example, a plasma CVD method or a sputtering method instead of the ALD method. Further, instead of depositing Al ₂ O ₃ , Al nitride or oxynitride may be used. In addition, an oxide, nitride, oxynitride of Si, Hf, Zr, Ti, Ta, and W, or an appropriate selection thereof may be deposited in multiple layers to form a gate insulating film. .

  Next, an electrode material, for example, Ti, TiN, TaN, etc., such as TaN having a thickness of about 50 nm and Al having a thickness of about 400 nm are deposited on the gate insulating film 71 by sputtering or the like. The electrode material and the gate insulating film 72 are processed by lithography and dry etching. The resist used for lithography is removed by ashing or wet processing. As described above, the gate electrode 72 is formed by filling the electrode trench with the electrode material via the gate insulating film 71 and projecting upward from the surface of the insulating film 69.

Subsequently, as shown in FIG. 40, after forming the insulating film 73, electrode recesses 74a, 74b, 74c, 74d, and 74e are formed.
More specifically, first, for example, SiN is deposited on the insulating film 69 to a thickness for embedding the gate electrode 72 by a CVD method or the like. Thereby, the insulating film 73 is formed.
Next, the insulating films 69 and 73 are processed by lithography and dry etching. Thus, electrode recesses 74a, 74b, 74c, 74d, and 74e are simultaneously formed in the insulating films 69 and 73. The electrode recesses 74a and 74b are formed in the first element region 1A of the insulating films 69 and 73, and the portions where the source electrode and the drain electrode of the compound semiconductor multilayer structure 63 are to be formed are exposed on the bottom surface. The electrode recesses 74c, 74d, and 74e are formed in the second element region 1B of the insulating films 69 and 73, and the conductive plugs 65A and 65B and the embedded gate structure 66 are exposed on the bottom surfaces.

Subsequently, as shown in FIG. 41, the source electrode 76a, the drain electrode 76b, the source electrode 76c, the drain electrode 76d, and the gate electrode 76e having the respective underlying films 75a, 75b, 75c, 75d, and 75e are formed simultaneously.
Specifically, for example, Ti is formed to a thickness of about 25 nm on the insulating film 73 by sputtering or the like so as to cover the inner wall surfaces of the electrode recesses 74a to 74e. Subsequently, for example, Al is deposited to a thickness of about 300 nm so as to embed the electrode recesses 74a to 74e through the deposited Ti by sputtering or the like. Then, Al and Ti are processed by lithography and dry etching. Thus, the source electrode 76a having the base film 75a and the drain electrode 76b having the base film 75b are formed in the first element region 1A. At the same time, a source electrode 76a having a base film 75c, a drain electrode 76d having a base film 75d, and a gate electrode 76e having a base film 75e are formed in the second element region 1B. The source electrode 76 a and the drain electrode 76 b are in ohmic contact with the compound semiconductor multilayer structure 63 on both sides of the gate electrode 72. The source electrode 76c, the drain electrode 76d, and the gate electrode 76e are electrically connected to the conductive plugs 65A and 65B and the buried gate structure 66. The source electrode 76c, the drain electrode 76d, and the gate electrode 76e are electrically connected to the N-type diffusion region 61c, the N-type diffusion region 61a, and the P-type diffusion region 61b through the conductive plugs 65A and 65B and the buried gate structure 66.

  In the present embodiment, the source electrode 76a and the drain electrode 76b are formed in the first element region 1A, and the source electrode 76c, the drain electrode 76d, and the gate electrode 76e are formed in the same flat surface in the same process in the second element region 1B. Formed. In this manner, each electrode (wiring) can be formed with good flatness with few steps as much as possible without causing an extra step, and a highly reliable semiconductor device with high processing accuracy is realized.

  Thereafter, various processes such as formation of an upper insulating film and formation of various wirings are performed. As described above, the first element region 1A is formed with the first element AlGaN / GaN.HEMT, and the second element region 1B is formed with the second element vertical N-type MIS transistor. A semiconductor device is formed.

As described above, according to the present embodiment, the compound semiconductor multilayer structure 63 is shared by the compound semiconductor element AlGaN / GaN HEMT and the silicon element MIS transistor. By adopting this configuration, a highly reliable semiconductor device capable of reliably obtaining both the function of the HEMT and the function of the MIS transistor even though it is manufactured with a minimum number of processes by reducing new materials and new processes. Realize.

  In the first to third embodiments, the MIS type AlGaN / GaN HEMT having a gate insulating film under the gate electrode is exemplified as the first element, but the first element is not limited thereto. A Schottky-type AlGaN / GaN.HEMT in which the gate electrode is not in contact and the gate electrode is in direct contact with the compound semiconductor stacked structure may be used. Further, the present invention is also applied to a case where, for example, a MIS transistor is formed instead of AlGaN / GaN HEMT.

  In the first to third embodiments, the transistor using 2DEG generated in the compound semiconductor stacked structure is exemplified as the first element. However, the first element is not limited to this. For example, the two-dimensional carrier gas generated in the compound semiconductor multilayer structure is not 2DEG but two-dimensional hole gas (2DHG), and various elements using the 2DHG are applicable as the first element.

(Fourth embodiment)
In this embodiment, a PFC (Power Factor Correction) circuit including at least one type of semiconductor device selected from the first to third embodiments is disclosed.
FIG. 42 is a connection diagram illustrating a PFC circuit according to the fourth embodiment.

The PFC circuit 100 includes a switching element (transistor) 101, a diode 102, a choke coil 103, capacitors 104 and 105, a diode bridge 106, and an AC power supply (AC) 107. AlGaN / GaN HEMT in one type of semiconductor device selected from the first to third embodiments is applied to the switch element 101. When the semiconductor device according to the first embodiment is applied as the switch element 101, the diode in the semiconductor device may be applied to the diode 102.
Note that the diode in the semiconductor device according to the first embodiment may be appropriately applied to the diode bridge 106.

  In the PFC circuit 100, the drain electrode of the switch element 101 is connected to the anode terminal of the diode 102 and one terminal of the choke coil 103. The source electrode of the switch element 101 is connected to one terminal of the capacitor 104 and one terminal of the capacitor 105. The other terminal of the capacitor 104 and the other terminal of the choke coil 103 are connected. The other terminal of the capacitor 105 and the cathode terminal of the diode 102 are connected. An AC 107 is connected between both terminals of the capacitor 104 via a diode bridge 106. A direct current power supply (DC) is connected between both terminals of the capacitor 105.

  In this embodiment, the functions of the first and second elements are realized with as simple an apparatus configuration as possible, and a highly reliable and high withstand voltage that can be manufactured with a minimum number of processes by reducing new materials and new processes. The semiconductor device is applied to the PFC circuit 100. Thereby, the highly reliable PFC circuit 100 is realized.

(Fifth embodiment)
In the present embodiment, a power supply device including at least one type of semiconductor device selected from the first to third embodiments is disclosed.
FIG. 43 is a connection diagram illustrating a schematic configuration of the power supply device according to the fifth embodiment.

The power supply device according to the present embodiment includes a high-voltage primary circuit 111 and a low-voltage secondary circuit 112, and a transformer 113 disposed between the primary circuit 111 and the secondary circuit 112. The
The primary side circuit 111 includes the PFC circuit 100 according to the fourth embodiment and an inverter circuit connected between both terminals of the capacitor 105 of the PFC circuit 100, for example, a full bridge inverter circuit 110. The full bridge inverter circuit 110 includes a plurality (four in this case) of switch elements 114a, 114b, 114c, and 114d.
The secondary side circuit 112 includes a plurality of (here, three) switch elements 115a, 115b, and 115c.

In the present embodiment, AlGaN / GaN in at least one type of semiconductor device selected from the first to third embodiments is used for the switch element 101 of the PFC circuit 100 and the switch elements 114a to 114d of the full bridge inverter circuit 110. -HEMT is applied.
The switch elements 115a to 115c of the secondary side circuit 112 are normal MIS • FETs using silicon. When the semiconductor device according to the third embodiment is applied as the switch element 101, the MIS transistor in the semiconductor device may be appropriately applied to the switch elements 115a to 115c.

  In this embodiment, the functions of the first and second elements are realized with as simple an apparatus configuration as possible, and a highly reliable and high withstand voltage that can be manufactured with a minimum number of processes by reducing new materials and new processes. The semiconductor device is applied to a power supply device. As a result, a highly reliable high-power power supply device is realized.

(Sixth embodiment)
In the present embodiment, a high-frequency amplifier including at least one type of semiconductor device selected from the first to third embodiments is disclosed.
FIG. 44 is a connection diagram illustrating a schematic configuration of the high-frequency amplifier according to the sixth embodiment.

The high-frequency amplifier according to this embodiment includes a digital predistortion circuit 121, mixers 122 a and 122 b, and a power amplifier 123.
The digital predistortion circuit 121 compensates for nonlinear distortion of the input signal. The mixer 122a mixes an input signal with compensated nonlinear distortion and an AC signal. The power amplifier 123 amplifies the input signal mixed with the AC signal, and AlGaN / GaN HEMT in at least one kind of semiconductor device selected from the first to third embodiments is applied. In FIG. 44, for example, by switching the switch, the output side signal is mixed with the AC signal by the mixer 122b and sent to the digital predistortion circuit 121.

  In this embodiment, the functions of the first and second elements are realized with as simple an apparatus configuration as possible, and a highly reliable and high withstand voltage that can be manufactured with a minimum number of processes by reducing new materials and new processes. This semiconductor device is applied to a high frequency amplifier. As a result, a high-reliability, high-voltage high-frequency amplifier is realized.

(Other embodiments)
In the first to sixth embodiments, semiconductor devices including AlGaN / GaN.HEMT as compound semiconductor elements are exemplified. As a compound semiconductor element, besides the AlGaN / GaN.HEMT, the following HEMT can be applied.

・ Other HEMT examples 1
In this example, a semiconductor device including InAlN / GaN.HEMT as a compound semiconductor element is disclosed.
InAlN and GaN are compound semiconductors that can have a lattice constant close to the composition. In this case, in the first to sixth embodiments described above, in the first element region 1A, the electron transit layer is formed of i-GaN, the electron supply layer is formed of n-InAlN, and the cap layer is formed of n-GaN. . Further, since piezo polarization hardly occurs in this case, 2DEG is mainly generated by spontaneous polarization of InAlN.

  According to this example, in a semiconductor device in which InAlN / GaN.HEMT and a predetermined silicon element are mounted together, the compound semiconductor laminated structure is shared between InAlN / GaN.HEMT and silicon element. By adopting this configuration, a highly reliable semiconductor device capable of reliably obtaining both the function of the HEMT and the function of the silicon element can be obtained by reducing the number of new materials and new processes and manufacturing the minimum number of processes. Realize.

・ Other HEMT examples 2
In this example, a semiconductor device including InAlGaN / GaN.HEMT as a compound semiconductor element is disclosed.
GaN and InAlGaN are compound semiconductors in which the latter can make the lattice constant smaller by the composition than the former. In this case, in the first to sixth embodiments described above, the first element region 1A is formed with an electron transit layer of i-GaN, an electron supply layer of n-InAlGaN, and a cap layer of n-GaN. .

  According to this example, in a semiconductor device in which an InAlGaN / GaN.HEMT and a predetermined silicon element are mixedly mounted, the compound semiconductor multilayer structure is shared by the InAlGaN / GaN.HEMT and the silicon element. By adopting this configuration, a highly reliable semiconductor device capable of reliably obtaining both the function of the HEMT and the function of the silicon element can be obtained by reducing the number of new materials and new processes and manufacturing the minimum number of processes. Realize.

  Hereinafter, various aspects of the semiconductor device, the manufacturing method thereof, the power supply device, and the high-frequency amplifier will be collectively described as appendices.

(Additional remark 1) Compound semiconductor laminated structure formed on the silicon substrate,
A first element and a second element formed in the compound semiconductor multilayer structure,
The second element is an element having an impurity diffusion portion formed in the silicon substrate and a conductive portion formed in the compound semiconductor stacked structure and electrically connected to the impurity diffusion portion. A featured semiconductor device.

(Supplementary Note 2) The first element includes a first electrode, and the second element includes a second electrode electrically connected to the conductive portion.
The semiconductor device according to appendix 1, wherein the first electrode and the second electrode are formed in the same layer and at the same height.

(Appendix 3) The compound semiconductor multilayer structure includes an electron transit layer having a two-dimensional carrier gas, and an electron supply layer that supplies electrons to the electron transit layer,
The semiconductor device according to appendix 1 or 2, wherein the first element is a HEMT element.

  (Additional remark 4) The said 2nd element is further formed in the said compound semiconductor laminated structure, and further has the carrier interruption | blocking part which interrupts | blocks the said two-dimensional carrier gas for every said electrically conductive part, The additional remark 3 characterized by the above-mentioned. A semiconductor device according to 1.

  (Supplementary Note 5) The semiconductor device according to any one of Supplementary Notes 1 to 4, wherein the second element includes an insulating layer between the impurity diffusion portion and the compound semiconductor multilayer structure.

  (Supplementary Note 6) In any one of Supplementary Notes 1 to 5, the predetermined conductive portion has a buried gate structure formed through a gate insulating film in the compound semiconductor stacked structure. Semiconductor device.

(Appendix 7) A step of forming an impurity diffusion portion in a silicon substrate;
Forming a compound semiconductor multilayer structure on the silicon substrate;
Forming a first element and a second element in the compound semiconductor multilayer structure,
The second element is an element having the impurity diffusion portion formed in the silicon substrate and a conductive portion formed in the compound semiconductor multilayer structure and electrically connected to the impurity diffusion portion. A method of manufacturing a semiconductor device.

  (Supplementary Note 8) The first electrode is connected to the first element, the second electrode is electrically connected to the second element, and the second electrode is electrically connected to the upper surface of the first electrode. 8. The method of manufacturing a semiconductor device according to appendix 7, wherein the semiconductor device is formed in the same process so that the upper surface of the electrode is on the same plane.

(Supplementary Note 9) The step of forming the compound semiconductor multilayer structure includes a step of forming an electron transit layer having a two-dimensional carrier gas,
Forming an electron supply layer for supplying electrons to the electron transit layer,
9. The method of manufacturing a semiconductor device according to appendix 7 or 8, wherein the first element is a HEMT element.

  (Supplementary note 10) The supplementary note 9 is characterized in that, in the second element, a carrier blocking part that electrically blocks the two-dimensional carrier gas is formed for each conductive part in the compound semiconductor multilayer structure. Semiconductor device manufacturing method.

  (Appendix 11) In the semiconductor device according to any one of Appendices 7 to 10, wherein in the second element, an insulating layer is formed between the impurity diffusion portion and the compound semiconductor multilayer structure. Production method.

  (Supplementary note 12) The semiconductor device according to any one of Supplementary notes 7 to 11, wherein the predetermined conductive portion is formed as a gate electrode through a gate insulating film in the compound semiconductor stacked structure. Method.

(Supplementary note 13) A power supply circuit comprising a transformer and a high-voltage circuit and a low-voltage circuit across the transformer,
The high-voltage circuit has a transistor,
The transistor is
A silicon region;
A compound semiconductor multilayer structure formed on the silicon region;
A first element and a second element formed in the compound semiconductor multilayer structure,
The second element is an element having an impurity diffusion portion formed in the silicon region and a conductive portion formed in the compound semiconductor stacked structure and electrically connected to the impurity diffusion portion. A featured power supply circuit.

(Supplementary Note 14) A high frequency amplifier that amplifies and outputs an input high frequency voltage,
Has a transistor,
The transistor is
A silicon region;
A compound semiconductor multilayer structure formed on the silicon region;
A first element and a second element formed in the compound semiconductor multilayer structure,
The second element is an element having an impurity diffusion portion formed in the silicon region and a conductive portion formed in the compound semiconductor stacked structure and electrically connected to the impurity diffusion portion. High-frequency amplifier characterized.

1 Si substrate 1a Element isolation trench 2 Element isolation structure 3, 31, 61 Impurity diffusion regions 3a, 31a, 31c, 61b P type diffusion regions 3b, 31b, 61a, 61c N type diffusion regions 4, 32, 62 Si layer 4a , 32a, 62a Insulating layers 5, 33, 63 Compound semiconductor laminated structure 5A, 14a, 14b, 14c, 14d, 33A, 42a, 42b, 42c, 42d, 42e, 63A, 74a, 74b, 74c, 74d, 74e For electrodes Recess 5a, 33a, 63a Buffer layer 5b, 33b, 63b Electron traveling layer 5c, 33c, 63c Electron supply layer 5d, 33d, 63d Cap layer 6, 9, 34, 37, 41, 69 Insulating films 7A, 7B, 35A, 35B, 35C, 65A, 65B Conductive plugs 7a, 7b, 9a, 21a, 22a, 23a, 35a, 35b, 35c, 3 7a, 51a, 52a, 53a, 65a, 65b, 66a, 81a, 82a, 83a, 69a Openings 7c, 15a, 15b, 15c, 15d, 35d, 43a, 43b, 43c, 43d, 43e, 65c, 66b, 75a, 75b, 75c, 75d, 75e Base films 7d, 35e, 65d, 66c Conductors 8, 36, 682 2DEG blocking structure 11, 38, 67, 71 Gate insulating films 12, 39, 72, 76e Gate electrodes 16a, 44a, 76a 76c Source electrode 16b, 44b, 76b, 76d Drain electrode 16c Anode electrode 16d Cathode electrode 21 Silicon oxide film 22 Silicon nitride film 23, 51, 52, 53, 81, 82, 83 Resist mask 44c Collector electrode 44d Base electrode 44e Emitter Electrode 66 buried gate structure 100 FC circuit 101,114a, 114b, 114c, 114d, 115a, 115b, 115c switch element 102 diode 103 choke coil 104 and 105 capacitor 106 diode bridge 107 AC
110 Full Bridge Inverter Circuit 111 Primary Side Circuit 112 Secondary Side Circuit 113 Transformer 121 Digital Predistortion Circuits 122a and 122b Mixer 123 Power Amplifier

Claims (8)

A compound semiconductor multilayer structure formed on a silicon substrate;
A first element and a second element formed in the compound semiconductor multilayer structure,
The second element is an element having an impurity diffusion portion formed in the silicon substrate and a conductive portion formed in the compound semiconductor stacked structure and electrically connected to the impurity diffusion portion. A featured semiconductor device. The first element includes a first electrode, and the second element includes a second electrode electrically connected to the conductive portion,
The semiconductor device according to claim 1, wherein the first electrode and the second electrode are formed in the same layer and at the same height. The compound semiconductor multilayer structure includes an electron transit layer having a two-dimensional carrier gas, and an electron supply layer that supplies electrons to the electron transit layer,
The semiconductor device according to claim 1, wherein the first element is a HEMT element.   The said 2nd element is further formed in the said compound semiconductor laminated structure, and further has a carrier interruption | blocking part which electrically interrupts | blocks the said two-dimensional carrier gas for every said electroconductive part. Semiconductor device. Forming an impurity diffusion portion in the silicon substrate;
Forming a compound semiconductor multilayer structure on the silicon substrate;
Forming a first element and a second element in the compound semiconductor multilayer structure,
The second element is an element having the impurity diffusion portion formed in the silicon substrate and a conductive portion formed in the compound semiconductor multilayer structure and electrically connected to the impurity diffusion portion. A method of manufacturing a semiconductor device.   A first electrode connected to the first element; a second electrode electrically connected to the conductive portion connected to the second element; an upper surface of the first electrode; an upper surface of the second electrode; 6. The method of manufacturing a semiconductor device according to claim 5, wherein the semiconductor device is formed in the same process so that the two are on the same plane. The step of forming the compound semiconductor multilayer structure includes the step of forming an electron transit layer having a two-dimensional carrier gas,
Forming an electron supply layer for supplying electrons to the electron transit layer,
The method for manufacturing a semiconductor device according to claim 5, wherein the first element is a HEMT element.   8. The semiconductor device according to claim 7, wherein in the second element, a carrier blocking portion that electrically blocks the two-dimensional carrier gas is formed for each of the conductive portions in the compound semiconductor stacked structure. Manufacturing method.

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