JP5049744B2 - 配線基板の製造方法およびその配線基板 - Google Patents
配線基板の製造方法およびその配線基板 Download PDFInfo
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- JP5049744B2 JP5049744B2 JP2007286865A JP2007286865A JP5049744B2 JP 5049744 B2 JP5049744 B2 JP 5049744B2 JP 2007286865 A JP2007286865 A JP 2007286865A JP 2007286865 A JP2007286865 A JP 2007286865A JP 5049744 B2 JP5049744 B2 JP 5049744B2
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- groove
- shaped
- wiring board
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- 229920012266 Poly(ether sulfone) PES Polymers 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000007664 blowing Methods 0.000 description 1
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Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4867—Applying pastes or inks, e.g. screen printing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/12—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using thick film techniques, e.g. printing techniques to apply the conductive material or similar techniques for applying conductive paste or ink patterns
- H05K3/1258—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using thick film techniques, e.g. printing techniques to apply the conductive material or similar techniques for applying conductive paste or ink patterns by using a substrate provided with a shape pattern, e.g. grooves, banks, resist pattern
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
- H01L2924/097—Glass-ceramics, e.g. devitrified glass
- H01L2924/09701—Low temperature co-fired ceramic [LTCC]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12044—OLED
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09009—Substrate related
- H05K2201/09036—Recesses or grooves in insulating substrate
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09218—Conductive traces
- H05K2201/09254—Branched layout
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/107—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by filling grooves in the support with conductive material
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Geometry (AREA)
- Thin Film Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
- Manufacturing Of Printed Wiring (AREA)
Description
2 ゲート電極
3 引き出し電極
4 ゲート絶縁膜
5 絶縁膜
6 感光性絶縁膜
7 有機半導体薄膜
9 ソース電極膜
10,13,73,74 複数の溝
11,14,75,76 バンク
12 ドレイン電極膜
Claims (2)
- 金属粒子を分散させた溶液を供給して配線を形成する配線基板の製造方法において、
基板上に、トランジジスタの細線幅のゲート長に近い寸法の間隙を持って配置され、細線用の溝であるソース電極側の溝型流路とドレイン電極側の溝型流路とを形成し、
前記ソース電極側の溝型流路の長手方向とは垂直方向に連通するように形成される複数の溝型流路を有する第1の櫛歯状の溝型流路を形成し、
該第1の櫛歯状の溝型流路は前記ソース電極側の溝型流路とは反対の一端で第1の共通溝型流路により互いに接続され、
前記ドレイン電極側の溝型流路の長手方向とは垂直方向に連通するように形成される複数の溝型流路を有する第2の櫛歯状の溝型流路を形成し、
該第2の櫛歯状の溝型流路は前記ドレイン電極側の溝型流路とは反対の一端で第2の共通溝型流路により互いに接続され、
複数の各流路へ金属粒子を分散させた溶液を供給し、
前記溶液の溶媒を乾燥させて、
前記流路内に残った前記金属粒子を焼成して、前記基板上に配線を形成することを特徴とする配線基板の製造方法。 - 請求項1において、
前記トランジジスタは、有機薄膜トランジスタであることを特徴とする配線基板の製造方法。
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007286865A JP5049744B2 (ja) | 2007-11-05 | 2007-11-05 | 配線基板の製造方法およびその配線基板 |
CN200810166779.9A CN101431146B (zh) | 2007-11-05 | 2008-10-27 | 布线基板的制造方法以及该布线基板 |
EP08019270A EP2056342B1 (en) | 2007-11-05 | 2008-11-04 | Wiring board |
US12/264,936 US8120070B2 (en) | 2007-11-05 | 2008-11-05 | Wiring board and method for manufacturing the same |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007286865A JP5049744B2 (ja) | 2007-11-05 | 2007-11-05 | 配線基板の製造方法およびその配線基板 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2009117498A JP2009117498A (ja) | 2009-05-28 |
JP5049744B2 true JP5049744B2 (ja) | 2012-10-17 |
Family
ID=40377568
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2007286865A Expired - Fee Related JP5049744B2 (ja) | 2007-11-05 | 2007-11-05 | 配線基板の製造方法およびその配線基板 |
Country Status (4)
Country | Link |
---|---|
US (1) | US8120070B2 (ja) |
EP (1) | EP2056342B1 (ja) |
JP (1) | JP5049744B2 (ja) |
CN (1) | CN101431146B (ja) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9510458B2 (en) * | 2013-03-13 | 2016-11-29 | Imagine Tf, Llc | High aspect ratio traces, circuits, and methods for manufacturing and using the same |
JP5924609B2 (ja) * | 2013-12-03 | 2016-05-25 | 国立大学法人山形大学 | 金属薄膜の製造方法及び導電構造の製造方法 |
CN105674777B (zh) * | 2016-01-25 | 2017-08-04 | 云南科威液态金属谷研发有限公司 | 一种基于液态金属的智能器件 |
CN111180523A (zh) * | 2019-12-31 | 2020-05-19 | 成都中电熊猫显示科技有限公司 | 薄膜晶体管、阵列基板以及液晶显示面板 |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02275672A (ja) * | 1989-03-30 | 1990-11-09 | Nippon Steel Corp | 薄膜トランジスター |
US5531020A (en) * | 1989-11-14 | 1996-07-02 | Poly Flex Circuits, Inc. | Method of making subsurface electronic circuits |
DE19941401C1 (de) * | 1999-08-31 | 2001-03-08 | Infineon Technologies Ag | Verfahren zur Herstellung einer DRAM-Zellenanordnung |
JP3324581B2 (ja) * | 1999-09-21 | 2002-09-17 | 日本電気株式会社 | 固体撮像装置及びその製造方法 |
GB0103715D0 (en) * | 2001-02-15 | 2001-04-04 | Koninkl Philips Electronics Nv | Semicondutor devices and their peripheral termination |
US7219978B2 (en) * | 2002-11-18 | 2007-05-22 | Osram Opto Semiconductors Gmbh | Ink jet bank substrates with channels |
JP2004260364A (ja) * | 2003-02-25 | 2004-09-16 | Renesas Technology Corp | 半導体装置及び高出力電力増幅装置並びにパソコンカード |
KR101100625B1 (ko) * | 2003-10-02 | 2012-01-03 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | 배선 기판 및 그 제조방법, 및 박막트랜지스터 및 그제조방법 |
WO2005048353A1 (en) * | 2003-11-14 | 2005-05-26 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing liquid crystal display device |
JP4330492B2 (ja) * | 2004-06-09 | 2009-09-16 | シャープ株式会社 | 配線基板及びその製造方法 |
JP4396414B2 (ja) * | 2004-06-24 | 2010-01-13 | セイコーエプソン株式会社 | 膜パターン形成方法および膜パターン形成装置 |
JP2007158003A (ja) * | 2005-12-05 | 2007-06-21 | Canon Inc | 電子デバイスおよび電子デバイスの製造方法 |
JP2007243081A (ja) * | 2006-03-13 | 2007-09-20 | Hitachi Ltd | 薄膜トランジスタ基板及び薄膜トランジスタ基板の生成方法 |
-
2007
- 2007-11-05 JP JP2007286865A patent/JP5049744B2/ja not_active Expired - Fee Related
-
2008
- 2008-10-27 CN CN200810166779.9A patent/CN101431146B/zh not_active Expired - Fee Related
- 2008-11-04 EP EP08019270A patent/EP2056342B1/en not_active Not-in-force
- 2008-11-05 US US12/264,936 patent/US8120070B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JP2009117498A (ja) | 2009-05-28 |
CN101431146A (zh) | 2009-05-13 |
US20090114958A1 (en) | 2009-05-07 |
EP2056342B1 (en) | 2013-01-09 |
EP2056342A3 (en) | 2011-04-06 |
US8120070B2 (en) | 2012-02-21 |
CN101431146B (zh) | 2011-12-07 |
EP2056342A2 (en) | 2009-05-06 |
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