JP5041984B2 - 整流回路、電源回路及び半導体装置 - Google Patents
整流回路、電源回路及び半導体装置 Download PDFInfo
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- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
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- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/13—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body combined with thin-film or thick-film passive components
Description
図1を用いて、本発明の整流回路及び電源回路の構成について説明する。図1(A)において、101は本発明の整流回路に相当する。整流回路101は2つの入力端子IN1、IN2と、2つの出力端子OUT1、OUT2に接続されている。アンテナが有する2つの端子は、入力端子IN1と入力端子IN2にそれぞれ接続される。また整流回路101は、第1の容量102と、第2の容量103と、ダイオード105と、トランジスタ106とを少なくとも有する。なお図1(A)では、トランジスタ106がnチャネル型である場合の整流回路101の構成を示している。また本発明の電源回路111は、整流回路101に加え、第3の容量104を有している。
図4を用いて、本発明の整流回路及び電源回路の構成について説明する。図4(A)において、201は本発明の整流回路に相当する。整流回路201は2つの入力端子IN1、IN2と、2つの出力端子OUT1、OUT2に接続されている。アンテナが有する2つの端子は、入力端子IN1と入力端子IN2にそれぞれ接続される。また整流回路201は、第1の容量202と、第2の容量203と、ダイオード205と、トランジスタ206とを少なくとも有する。なお図4(A)では、トランジスタ206がpチャネル型である場合の整流回路201の構成を示している。また本発明の電源回路211は、整流回路201に加え、第3の容量204を有している。
実施の形態1及び実施の形態2では、出力端子OUT1から正の直流電圧を得ることができる整流回路及び電源回路の構成について説明した。本実施の形態では、負の直流電圧を得ることができる、本発明の整流回路及び電源回路の構成について説明する。
102 第1の容量
103 第2の容量
104 第3の容量
105 ダイオード
106 トランジスタ
107 トランジスタ
108 ローパスフィルタ
109 ハイパスフィルタ
110 抵抗
111 電源回路
112 ハイパスフィルタ
140 半導体膜
141 導電膜
142 導電膜
143 半導体膜
144 導電膜
145 導電膜
146 導電膜
147 導電膜
148 半導体膜
149 導電膜
201 整流回路
202 第1の容量
203 第2の容量
204 第3の容量
205 ダイオード
206 トランジスタ
207 トランジスタ
208 ローパスフィルタ
209 ハイパスフィルタ
210 抵抗
211 電源回路
212 ハイパスフィルタ
2O4 マンガン酸リチウム(LiMn
2O5 場合(W
2O5 酸化バナジウム(V
301 整流回路
302 第1の容量
303 第2の容量
304 第3の容量
305 ダイオード
306 トランジスタ
309 電源回路
311 整流回路
312 第1の容量
313 第2の容量
314 第3の容量
315 ダイオード
316 トランジスタ
319 電源回路
700 基板
701 絶縁膜
702 剥離層
703 絶縁膜
704 半導体膜
705 半導体膜
706 半導体膜
708 ゲート絶縁膜
709 電極
710 低濃度不純物領域
711 マスク
712 高濃度不純物領域
713 ゲート絶縁膜
714 サイドウォール
715 高濃度不純物領域
716 TFT
717 TFT
718 TFT
719 容量
720 絶縁膜
721 絶縁膜
722 導電膜
723 導電膜
724 導電膜
725 導電膜
727 導電膜
730 絶縁膜
731 導電膜
732 導電膜
733 絶縁膜
734 素子形成層
735 シート材
736 シート材
800 ダイオード
801 入力端子
802 出力端子
803 コンデンサ
900 半導体装置
901 アンテナ
902 集積回路
903 電源回路
904 復調回路
905 変調回路
906 レギュレータ
907 制御回路
909 メモリ
1101 書籍
1102 包装材
1103 半導体装置
1104 携帯電話
1105 表示部
1307 半導体装置
1308 包装材
1309 弁当
1310 ラベル
1311 半導体装置
1312 商品
1601 集積回路
1602 アンテナ
1603 基板
1604 カバー材
1605 集積回路
1606 アンテナ
1607 カバー材
1608 基板
2300 半導体基板
2301 素子分離用絶縁膜
2302 素子形成領域
2303 素子形成領域
2304 pウェル
2305 絶縁膜
2307 導電膜
2308 導電膜
2309 ゲート電極
2310 ゲート電極
2311 マスク
2312 不純物領域
2313 チャネル形成領域
2314 マスク
2315 不純物領域
2316 チャネル形成領域
2317 絶縁膜
2318 導電膜
2324 層間膜
2325 配線
2326 導電膜
3000 半導体装置
3010 質問器
3020 アンテナユニット
3030 制御用端末
3100 アンテナ
3200 高周波回路
3300 電源回路
3400 リセット回路
3500 復調回路
3600 集積回路
3700 クロック生成回路
4000 変調回路
4100 第一の制御回路
4300 メモリ回路
4400 バッテリー
4410 第二の制御回路
7101 基板
7102 集電体薄膜
7103 負極活物質層
7104 固体電解質層
7105 正極活物質層
7106 集電体薄膜
Claims (24)
- 入力端子と2つの出力端子の間に、第1の容量と、第2の容量と、トランジスタと、ダイオードとを有し、
前記第1の容量と、前記第2の容量と、前記ダイオードとは、前記入力端子と前記2つの出力端子のうち一方の出力端子の間において順に直列に接続されており、
前記第2の容量は、前記トランジスタのソース領域及びドレイン領域の一方と、前記トランジスタのゲート電極の間に電気的に接続されており、
前記トランジスタのソース領域及びドレイン領域の他方と、前記2つの出力端子のうち他方の出力端子とが電気的に接続されていることを特徴とする整流回路。 - 入力端子と2つの出力端子の間に、第1の容量と、第2の容量と、トランジスタと、ダイオードと、抵抗とを有し、
前記第1の容量と、前記第2の容量と、前記ダイオードとは、前記入力端子と前記2つの出力端子のうち一方の出力端子の間において順に直列に接続されており、
前記第2の容量は、前記トランジスタのソース領域及びドレイン領域の一方と、前記トランジスタのゲート電極の間に電気的に接続されており、
前記トランジスタのソース領域及びドレイン領域の他方と、前記2つの出力端子のうち他方の出力端子とが電気的に接続され、
前記抵抗は、前記トランジスタのゲート電極と前記一方の出力端子との間に電気的に接続されていることを特徴とする整流回路。 - 請求項1または請求項2において、前記トランジスタはnチャネル型であり、該トランジスタのソース領域及びドレイン領域の一方が、前記ダイオードのカソードに電気的に接続されていることを特徴とする整流回路。
- 請求項1または請求項2において、前記トランジスタはpチャネル型であり、該トランジスタのソース領域及びドレイン領域の一方が、前記ダイオードのアノードに電気的に接続されていることを特徴とする整流回路。
- 請求項1乃至請求項4のいずれか1項において、前記ダイオードはnチャネル型のトランジスタであり、該トランジスタのソース領域及びドレイン領域の一方と、該トランジスタのゲート電極とが電気的に接続されていることを特徴とする整流回路。
- 請求項1乃至請求項4のいずれか1項において、前記ダイオードはpチャネル型のトランジスタであり、該トランジスタのソース領域及びドレイン領域の一方と、該トランジスタのゲート電極とが電気的に接続されていることを特徴とする整流回路。
- 入力端子と2つの出力端子の間に、第1の容量と、第2の容量と、第3の容量と、トランジスタと、ダイオードとを有し、
前記第1の容量と、前記第2の容量と、前記ダイオードとは、前記入力端子と前記2つの出力端子のうち一方の出力端子の間において順に直列に接続されており、
前記第2の容量は、前記トランジスタのソース領域及びドレイン領域の一方と、前記トランジスタのゲート電極の間に電気的に接続されており、
前記トランジスタのソース領域及びドレイン領域の他方と、前記2つの出力端子のうち他方の出力端子とが電気的に接続されており、
前記第3の容量は前記2つの出力端子の間に電気的に接続されていることを特徴とする電源回路。 - 入力端子と2つの出力端子の間に、第1の容量と、第2の容量と、第3の容量と、トランジスタと、ダイオードと、抵抗とを有し、
前記第1の容量と、前記第2の容量と、前記ダイオードとは、前記入力端子と前記2つの出力端子のうち一方の出力端子の間において順に直列に接続されており、
前記第2の容量は、前記トランジスタのソース領域及びドレイン領域の一方と、ゲート電極の間に電気的に接続されており、
前記トランジスタのソース領域及びドレイン領域の他方と、前記2つの出力端子のうち他方の出力端子とが電気的に接続されており、
前記第3の容量は前記2つの出力端子の間に電気的に接続されており、
前記抵抗は、前記トランジスタのゲート電極と前記一方の出力端子との間に電気的に接続されていることを特徴とする電源回路。 - 請求項7または請求項8において、前記トランジスタはnチャネル型であり、該トランジスタのソース領域及びドレイン領域の一方が、前記ダイオードのカソードに電気的に接続されていることを特徴とする電源回路。
- 請求項7または請求項8において、前記トランジスタはpチャネル型であり、該トランジスタのソース領域及びドレイン領域の一方が、前記ダイオードのアノードに電気的に接続されていることを特徴とする電源回路。
- 請求項7乃至請求項10のいずれか1項において、前記ダイオードはnチャネル型のトランジスタであり、
該トランジスタのソース領域及びドレイン領域の一方と、該トランジスタのゲート電極とが電気的に接続されていることを特徴とする電源回路。 - 請求項7乃至請求項10のいずれか1項において、前記ダイオードはpチャネル型のトランジスタであり、
該トランジスタのソース領域及びドレイン領域の一方と、該トランジスタのゲート電極とが電気的に接続されていることを特徴とする電源回路。 - アンテナから交流電圧が印加される整流回路を有し、
前記整流回路は、入力端子と2つの出力端子の間に、第1の容量と、第2の容量と、トランジスタと、ダイオードとを有し、
前記第1の容量と、前記第2の容量と、前記ダイオードとは、前記入力端子と前記2つの出力端子のうち一方の出力端子の間において順に直列に接続されており、
前記第2の容量は、前記トランジスタのソース領域及びドレイン領域の一方と、前記トランジスタのゲート電極の間に電気的に接続されており、
前記トランジスタのソース領域及びドレイン領域の他方と、前記2つの出力端子のうち他方の出力端子とが電気的に接続されていることを特徴とする半導体装置。 - アンテナから交流電圧が印加される整流回路を有し、
前記整流回路は、入力端子と2つの出力端子の間に、第1の容量と、第2の容量と、トランジスタと、ダイオードと、抵抗とを有し、
前記第1の容量と、前記第2の容量と、前記ダイオードとは、前記入力端子と前記2つの出力端子のうち一方の出力端子の間において順に直列に接続されており、
前記第2の容量は、前記トランジスタのソース領域及びドレイン領域の一方と、前記トランジスタのゲート電極の間に電気的に接続されており、
前記トランジスタのソース領域及びドレイン領域の他方と、前記2つの出力端子のうち他方の出力端子とが接続されており、
前記抵抗は、前記トランジスタのゲート電極と前記一方の出力端子との間に電気的に接続されていることを特徴とする半導体装置。 - アンテナと、アンテナから交流電圧が印加される整流回路とを有し、
前記整流回路は、入力端子と2つの出力端子の間に、第1の容量と、第2の容量と、トランジスタと、ダイオードとを有し、
前記第1の容量と、前記第2の容量と、前記ダイオードとは、前記入力端子と前記2つの出力端子のうち一方の出力端子の間において順に直列に接続されており、
前記第2の容量は、前記トランジスタのソース領域及びドレイン領域の一方と、前記トランジスタのゲート電極の間に電気的に接続されており、
前記トランジスタのソース領域及びドレイン領域の他方と、前記2つの出力端子のうち他方の出力端子とが接続されていることを特徴とする半導体装置。 - アンテナと、アンテナから交流電圧が印加される整流回路とを有し、
前記整流回路は、入力端子と2つの出力端子の間に、第1の容量と、第2の容量と、トランジスタと、ダイオードと、抵抗とを有し、
前記第1の容量と、前記第2の容量と、前記ダイオードとは、前記入力端子と前記2つの出力端子のうち一方の出力端子の間において順に直列に接続されており、
前記第2の容量は、前記トランジスタのソース領域及びドレイン領域の一方と、前記トランジスタのゲート電極の間に電気的に接続されており、
前記トランジスタのソース領域及びドレイン領域の他方と、前記2つの出力端子のうち他方の出力端子とが電気的に接続されており、
前記抵抗は、前記トランジスタのゲート電極と前記一方の出力端子との間に電気的に接続されていることを特徴とする半導体装置。 - アンテナから交流電圧が印加される電源回路を有し、
前記電源回路は、入力端子と2つの出力端子の間に、第1の容量と、第2の容量と、第3の容量と、トランジスタと、ダイオードとを有し、
前記第1の容量と、前記第2の容量と、前記ダイオードとは、前記入力端子と前記2つの出力端子のうち一方の出力端子の間において順に直列に接続されており、
前記第2の容量は、前記トランジスタのソース領域及びドレイン領域の一方と、前記トランジスタのゲート電極の間に電気的に接続されており、
前記トランジスタのソース領域及びドレイン領域の他方と、前記2つの出力端子のうち他方の出力端子とが電気的に接続されており、
前記第3の容量は前記2つの出力端子の間に電気的に接続されていることを特徴とする半導体装置。 - アンテナから交流電圧が印加される電源回路を有し、
前記電源回路は、入力端子と2つの出力端子の間に、第1の容量と、第2の容量と、第3の容量と、トランジスタと、ダイオードと、抵抗とを有し、
前記第1の容量と、前記第2の容量と、前記ダイオードとは、前記入力端子と前記2つの出力端子のうち一方の出力端子の間において順に直列に接続されており、
前記第2の容量は、前記トランジスタのソース領域及びドレイン領域の一方と、前記トランジスタのゲート電極の間に電気的に接続されており、
前記トランジスタのソース領域及びドレイン領域の他方と、前記2つの出力端子のうち他方の出力端子とが電気的に接続されており、
前記第3の容量は前記2つの出力端子の間に電気的に接続されており、
前記抵抗は、前記トランジスタのゲート電極と前記一方の出力端子との間に電気的に接続されていることを特徴とする半導体装置。 - アンテナと、アンテナから交流電圧が印加される電源回路とを有し、
前記電源回路は、入力端子と2つの出力端子の間に、第1の容量と、第2の容量と、第3の容量と、トランジスタと、ダイオードとを有し、
前記第1の容量と、前記第2の容量と、前記ダイオードとは、前記入力端子と前記2つの出力端子のうち一方の出力端子の間において順に直列に接続されており、
前記第2の容量は、前記トランジスタのソース領域及びドレイン領域の一方と、前記トランジスタのゲート電極の間に電気的に接続されており、
前記トランジスタのソース領域及びドレイン領域の他方と、前記2つの出力端子のうち他方の出力端子とが電気的に接続されており、
前記第3の容量は前記2つの出力端子の間に電気的に接続されていることを特徴とする半導体装置。 - アンテナと、アンテナから交流電圧が印加される電源回路とを有し、
前記電源回路は、入力端子と2つの出力端子の間に、第1の容量と、第2の容量と、第3の容量と、トランジスタと、ダイオードと、抵抗とを有し、
前記第1の容量と、前記第2の容量と、前記ダイオードとは、前記入力端子と前記2つの出力端子のうち一方の出力端子の間において順に直列に接続されており、
前記第2の容量は、前記トランジスタのソース領域及びドレイン領域の一方と、前記トランジスタのゲート電極の間に電気的に接続されており、
前記トランジスタのソース領域及びドレイン領域の他方と、前記2つの出力端子のうち他方の出力端子とが電気的に接続されており、
前記第3の容量は前記2つの出力端子の間に電気的に接続されており、
前記抵抗は、前記トランジスタのゲート電極と前記一方の出力端子との間に電気的に接続されていることを特徴とする半導体装置。 - 請求項13乃至請求項20のいずれか1項において、前記トランジスタはnチャネル型であり、該トランジスタのソース領域及びドレイン領域の一方が、前記ダイオードのカソードに電気的に接続されていることを特徴とする半導体装置。
- 請求項13乃至請求項20のいずれか1項において、前記トランジスタはpチャネル型であり、該トランジスタのソース領域及びドレイン領域の一方が、前記ダイオードのアノードに電気的に接続されていることを特徴とする半導体装置。
- 請求項13乃至請求項22のいずれか1項において、前記ダイオードはnチャネル型のトランジスタであり、該トランジスタのソース領域及びドレイン領域の一方と、該トランジスタのゲート電極とが電気的に接続されていることを特徴とする半導体装置。
- 請求項13乃至請求項22のいずれか1項において、前記ダイオードはpチャネル型のトランジスタであり、該トランジスタのソース領域及びドレイン領域の一方と、該トランジスタのゲート電極とが電気的に接続されていることを特徴とする半導体装置。
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CN101202472A (zh) | 2008-06-18 |
CN101202472B (zh) | 2012-07-04 |
US20080123383A1 (en) | 2008-05-29 |
US20110127338A1 (en) | 2011-06-02 |
US8050070B2 (en) | 2011-11-01 |
US7889528B2 (en) | 2011-02-15 |
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