JP5036146B2 - プログラマブル論理の特定用途向け集積回路等価物および関連の方法 - Google Patents
プログラマブル論理の特定用途向け集積回路等価物および関連の方法 Download PDFInfo
- Publication number
- JP5036146B2 JP5036146B2 JP2005193749A JP2005193749A JP5036146B2 JP 5036146 B2 JP5036146 B2 JP 5036146B2 JP 2005193749 A JP2005193749 A JP 2005193749A JP 2005193749 A JP2005193749 A JP 2005193749A JP 5036146 B2 JP5036146 B2 JP 5036146B2
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- Prior art keywords
- circuit
- logic
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- signal
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-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/1733—Controllable logic circuits
- H03K19/1737—Controllable logic circuits using multiplexers
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- Physics & Mathematics (AREA)
- Mathematical Physics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Logic Circuits (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US10/884,460 US7243329B2 (en) | 2004-07-02 | 2004-07-02 | Application-specific integrated circuit equivalents of programmable logic and associated methods |
| US10/884460 | 2004-07-02 |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2012087199A Division JP5475045B2 (ja) | 2004-07-02 | 2012-04-06 | プログラマブル論理の特定用途向け集積回路等価物および関連の方法 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2006020329A JP2006020329A (ja) | 2006-01-19 |
| JP2006020329A5 JP2006020329A5 (enExample) | 2008-08-14 |
| JP5036146B2 true JP5036146B2 (ja) | 2012-09-26 |
Family
ID=34993053
Family Applications (5)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2005193749A Expired - Fee Related JP5036146B2 (ja) | 2004-07-02 | 2005-07-01 | プログラマブル論理の特定用途向け集積回路等価物および関連の方法 |
| JP2012087199A Expired - Fee Related JP5475045B2 (ja) | 2004-07-02 | 2012-04-06 | プログラマブル論理の特定用途向け集積回路等価物および関連の方法 |
| JP2012153545A Expired - Fee Related JP5623471B2 (ja) | 2004-07-02 | 2012-07-09 | プログラマブル論理の特定用途向け集積回路等価物および関連の方法 |
| JP2014081749A Withdrawn JP2014131365A (ja) | 2004-07-02 | 2014-04-11 | プログラマブル論理の特定用途向け集積回路等価物および関連の方法 |
| JP2014208874A Expired - Fee Related JP5859089B2 (ja) | 2004-07-02 | 2014-10-10 | プログラマブル論理の特定用途向け集積回路等価物および関連の方法 |
Family Applications After (4)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2012087199A Expired - Fee Related JP5475045B2 (ja) | 2004-07-02 | 2012-04-06 | プログラマブル論理の特定用途向け集積回路等価物および関連の方法 |
| JP2012153545A Expired - Fee Related JP5623471B2 (ja) | 2004-07-02 | 2012-07-09 | プログラマブル論理の特定用途向け集積回路等価物および関連の方法 |
| JP2014081749A Withdrawn JP2014131365A (ja) | 2004-07-02 | 2014-04-11 | プログラマブル論理の特定用途向け集積回路等価物および関連の方法 |
| JP2014208874A Expired - Fee Related JP5859089B2 (ja) | 2004-07-02 | 2014-10-10 | プログラマブル論理の特定用途向け集積回路等価物および関連の方法 |
Country Status (4)
| Country | Link |
|---|---|
| US (5) | US7243329B2 (enExample) |
| EP (1) | EP1612940A3 (enExample) |
| JP (5) | JP5036146B2 (enExample) |
| CN (1) | CN1716781A (enExample) |
Families Citing this family (35)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7373631B1 (en) * | 2004-08-11 | 2008-05-13 | Altera Corporation | Methods of producing application-specific integrated circuit equivalents of programmable logic |
| US7392498B1 (en) * | 2004-11-19 | 2008-06-24 | Xilinx, Inc | Method and apparatus for implementing a pre-implemented circuit design for a programmable logic device |
| US7441223B1 (en) * | 2005-01-07 | 2008-10-21 | Altera Corporation | Method and apparatus for performing synthesis to improve density on field programmable gate arrays |
| US7620924B2 (en) * | 2005-03-14 | 2009-11-17 | Lsi Corporation | Base platforms with combined ASIC and FPGA features and process of using the same |
| US7275232B2 (en) * | 2005-04-01 | 2007-09-25 | Altera Corporation | Methods for producing equivalent field-programmable gate arrays and structured application specific integrated circuits |
| US7304497B2 (en) * | 2005-04-29 | 2007-12-04 | Altera Corporation | Methods and apparatus for programmably powering down structured application-specific integrated circuits |
| US7404169B2 (en) * | 2005-05-31 | 2008-07-22 | Altera Corporation | Clock signal networks for structured ASIC devices |
| US7386819B1 (en) * | 2005-07-28 | 2008-06-10 | Altera Corporation | Methods of verifying functional equivalence between FPGA and structured ASIC logic cells |
| US7373630B1 (en) | 2005-12-12 | 2008-05-13 | Altera Corporation | Methods for improved structured ASIC design |
| US8037444B1 (en) | 2006-07-20 | 2011-10-11 | Altera Corporation | Programmable control of mask-programmable integrated circuit devices |
| US7587686B1 (en) | 2006-08-01 | 2009-09-08 | Altera Corporation | Clock gating in a structured ASIC |
| US7536668B1 (en) | 2006-08-11 | 2009-05-19 | Xilinx, Inc. | Determining networks of a tile module of a programmable logic device |
| US7584448B1 (en) * | 2006-08-11 | 2009-09-01 | Xilinx, Inc. | Constructing a model of a programmable logic device |
| US7451424B1 (en) | 2006-08-11 | 2008-11-11 | Xilinx, Inc. | Determining programmable connections through a switchbox of a programmable logic device |
| US7451423B1 (en) | 2006-08-11 | 2008-11-11 | Xilinx, Inc. | Determining indices of configuration memory cell modules of a programmable logic device |
| US7472370B1 (en) | 2006-08-11 | 2008-12-30 | Xilinx, Inc. | Comparing graphical and netlist connections of a programmable logic device |
| US7451425B1 (en) | 2006-08-11 | 2008-11-11 | Xilinx, Inc. | Determining controlling pins for a tile module of a programmable logic device |
| US7451420B1 (en) | 2006-08-11 | 2008-11-11 | Xilinx, Inc. | Determining reachable pins of a network of a programmable logic device |
| US7478359B1 (en) * | 2006-10-02 | 2009-01-13 | Xilinx, Inc. | Formation of columnar application specific circuitry using a columnar programmable logic device |
| US7589555B1 (en) * | 2007-01-08 | 2009-09-15 | Altera Corporation | Variable sized soft memory macros in structured cell arrays, and related methods |
| JP2008192967A (ja) * | 2007-02-07 | 2008-08-21 | Elpida Memory Inc | 半導体装置及びその配線切り替えオプション |
| US7724031B2 (en) * | 2007-03-21 | 2010-05-25 | Altera Corporation | Staggered logic array block architecture |
| US7924052B1 (en) | 2008-01-30 | 2011-04-12 | Actel Corporation | Field programmable gate array architecture having Clos network-based input interconnect |
| US7586327B1 (en) | 2008-03-25 | 2009-09-08 | Altera Corporation | Distributed memory circuitry on structured application-specific integrated circuit devices |
| US7622952B1 (en) | 2008-05-28 | 2009-11-24 | Altera Corporation | Periphery clock signal distribution circuitry for structured ASIC devices |
| JP5453850B2 (ja) * | 2009-03-06 | 2014-03-26 | 富士通セミコンダクター株式会社 | 半導体集積回路 |
| US8105885B1 (en) * | 2010-08-06 | 2012-01-31 | Altera Corporation | Hardened programmable devices |
| JPWO2012032937A1 (ja) * | 2010-09-08 | 2014-01-20 | 日本電気株式会社 | 再構成可能回路 |
| WO2012047735A2 (en) * | 2010-09-29 | 2012-04-12 | The Regents Of The University Of California | In-place resynthesis and remapping techniques for soft error mitigation in fpga |
| US8533641B2 (en) | 2011-10-07 | 2013-09-10 | Baysand Inc. | Gate array architecture with multiple programmable regions |
| US8881082B2 (en) * | 2012-12-19 | 2014-11-04 | Infinera Corporation | FEC decoder dynamic power optimization |
| WO2015069275A1 (en) * | 2013-11-08 | 2015-05-14 | Empire Technology Development Llc | Control of router in cloud system |
| US9418231B2 (en) * | 2014-06-03 | 2016-08-16 | Empire Technology Development Llc | Perturbation of field programmable gate array code to prevent side channel attack |
| US10394991B2 (en) * | 2016-10-06 | 2019-08-27 | Altera Corporation | Methods and apparatus for dynamically configuring soft processors on an integrated circuit |
| US10353709B2 (en) * | 2017-09-13 | 2019-07-16 | Nextera Video, Inc. | Digital signal processing array using integrated processing elements |
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| JPH046913A (ja) * | 1990-04-24 | 1992-01-10 | Kawasaki Steel Corp | プログラマブル論理素子 |
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| JPH05252025A (ja) * | 1991-10-28 | 1993-09-28 | Texas Instr Inc <Ti> | 論理モジュールおよび集積回路 |
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-
2004
- 2004-07-02 US US10/884,460 patent/US7243329B2/en not_active Expired - Fee Related
-
2005
- 2005-05-25 CN CN 200510072989 patent/CN1716781A/zh active Pending
- 2005-06-24 EP EP05253922A patent/EP1612940A3/en not_active Withdrawn
- 2005-07-01 JP JP2005193749A patent/JP5036146B2/ja not_active Expired - Fee Related
-
2007
- 2007-05-07 US US11/801,082 patent/US7870513B2/en not_active Expired - Fee Related
-
2010
- 2010-12-14 US US12/967,851 patent/US8291355B2/en not_active Expired - Fee Related
-
2012
- 2012-04-06 JP JP2012087199A patent/JP5475045B2/ja not_active Expired - Fee Related
- 2012-07-09 JP JP2012153545A patent/JP5623471B2/ja not_active Expired - Fee Related
- 2012-09-13 US US13/614,819 patent/US8504963B2/en not_active Expired - Fee Related
-
2013
- 2013-07-31 US US13/955,200 patent/US8863061B2/en not_active Expired - Fee Related
-
2014
- 2014-04-11 JP JP2014081749A patent/JP2014131365A/ja not_active Withdrawn
- 2014-10-10 JP JP2014208874A patent/JP5859089B2/ja not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| US8863061B2 (en) | 2014-10-14 |
| US20110084727A1 (en) | 2011-04-14 |
| US8291355B2 (en) | 2012-10-16 |
| JP2012157054A (ja) | 2012-08-16 |
| JP2014131365A (ja) | 2014-07-10 |
| US8504963B2 (en) | 2013-08-06 |
| US7870513B2 (en) | 2011-01-11 |
| US7243329B2 (en) | 2007-07-10 |
| US20130002295A1 (en) | 2013-01-03 |
| JP2015008539A (ja) | 2015-01-15 |
| JP5475045B2 (ja) | 2014-04-16 |
| CN1716781A (zh) | 2006-01-04 |
| US20060001444A1 (en) | 2006-01-05 |
| EP1612940A2 (en) | 2006-01-04 |
| US20070210827A1 (en) | 2007-09-13 |
| JP5859089B2 (ja) | 2016-02-10 |
| US20130314122A1 (en) | 2013-11-28 |
| JP2006020329A (ja) | 2006-01-19 |
| EP1612940A3 (en) | 2007-08-22 |
| JP5623471B2 (ja) | 2014-11-12 |
| JP2012235499A (ja) | 2012-11-29 |
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| R250 | Receipt of annual fees |
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