JP5036146B2 - プログラマブル論理の特定用途向け集積回路等価物および関連の方法 - Google Patents

プログラマブル論理の特定用途向け集積回路等価物および関連の方法 Download PDF

Info

Publication number
JP5036146B2
JP5036146B2 JP2005193749A JP2005193749A JP5036146B2 JP 5036146 B2 JP5036146 B2 JP 5036146B2 JP 2005193749 A JP2005193749 A JP 2005193749A JP 2005193749 A JP2005193749 A JP 2005193749A JP 5036146 B2 JP5036146 B2 JP 5036146B2
Authority
JP
Japan
Prior art keywords
circuit
logic
hle
signal
input signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2005193749A
Other languages
English (en)
Japanese (ja)
Other versions
JP2006020329A5 (enrdf_load_stackoverflow
JP2006020329A (ja
Inventor
ケン チュア カー
チェウン サミー
コン プーン ヒー
ピン タン キム
リァン ゴアイ ウェイ
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Altera Corp
Original Assignee
Altera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Altera Corp filed Critical Altera Corp
Publication of JP2006020329A publication Critical patent/JP2006020329A/ja
Publication of JP2006020329A5 publication Critical patent/JP2006020329A5/ja
Application granted granted Critical
Publication of JP5036146B2 publication Critical patent/JP5036146B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/1733—Controllable logic circuits
    • H03K19/1737—Controllable logic circuits using multiplexers

Landscapes

  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Logic Circuits (AREA)
JP2005193749A 2004-07-02 2005-07-01 プログラマブル論理の特定用途向け集積回路等価物および関連の方法 Expired - Fee Related JP5036146B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/884460 2004-07-02
US10/884,460 US7243329B2 (en) 2004-07-02 2004-07-02 Application-specific integrated circuit equivalents of programmable logic and associated methods

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2012087199A Division JP5475045B2 (ja) 2004-07-02 2012-04-06 プログラマブル論理の特定用途向け集積回路等価物および関連の方法

Publications (3)

Publication Number Publication Date
JP2006020329A JP2006020329A (ja) 2006-01-19
JP2006020329A5 JP2006020329A5 (enrdf_load_stackoverflow) 2008-08-14
JP5036146B2 true JP5036146B2 (ja) 2012-09-26

Family

ID=34993053

Family Applications (5)

Application Number Title Priority Date Filing Date
JP2005193749A Expired - Fee Related JP5036146B2 (ja) 2004-07-02 2005-07-01 プログラマブル論理の特定用途向け集積回路等価物および関連の方法
JP2012087199A Expired - Fee Related JP5475045B2 (ja) 2004-07-02 2012-04-06 プログラマブル論理の特定用途向け集積回路等価物および関連の方法
JP2012153545A Expired - Fee Related JP5623471B2 (ja) 2004-07-02 2012-07-09 プログラマブル論理の特定用途向け集積回路等価物および関連の方法
JP2014081749A Withdrawn JP2014131365A (ja) 2004-07-02 2014-04-11 プログラマブル論理の特定用途向け集積回路等価物および関連の方法
JP2014208874A Expired - Fee Related JP5859089B2 (ja) 2004-07-02 2014-10-10 プログラマブル論理の特定用途向け集積回路等価物および関連の方法

Family Applications After (4)

Application Number Title Priority Date Filing Date
JP2012087199A Expired - Fee Related JP5475045B2 (ja) 2004-07-02 2012-04-06 プログラマブル論理の特定用途向け集積回路等価物および関連の方法
JP2012153545A Expired - Fee Related JP5623471B2 (ja) 2004-07-02 2012-07-09 プログラマブル論理の特定用途向け集積回路等価物および関連の方法
JP2014081749A Withdrawn JP2014131365A (ja) 2004-07-02 2014-04-11 プログラマブル論理の特定用途向け集積回路等価物および関連の方法
JP2014208874A Expired - Fee Related JP5859089B2 (ja) 2004-07-02 2014-10-10 プログラマブル論理の特定用途向け集積回路等価物および関連の方法

Country Status (4)

Country Link
US (5) US7243329B2 (enrdf_load_stackoverflow)
EP (1) EP1612940A3 (enrdf_load_stackoverflow)
JP (5) JP5036146B2 (enrdf_load_stackoverflow)
CN (1) CN1716781A (enrdf_load_stackoverflow)

Families Citing this family (35)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7373631B1 (en) * 2004-08-11 2008-05-13 Altera Corporation Methods of producing application-specific integrated circuit equivalents of programmable logic
US7392498B1 (en) * 2004-11-19 2008-06-24 Xilinx, Inc Method and apparatus for implementing a pre-implemented circuit design for a programmable logic device
US7441223B1 (en) * 2005-01-07 2008-10-21 Altera Corporation Method and apparatus for performing synthesis to improve density on field programmable gate arrays
US7620924B2 (en) * 2005-03-14 2009-11-17 Lsi Corporation Base platforms with combined ASIC and FPGA features and process of using the same
US7275232B2 (en) * 2005-04-01 2007-09-25 Altera Corporation Methods for producing equivalent field-programmable gate arrays and structured application specific integrated circuits
US7304497B2 (en) * 2005-04-29 2007-12-04 Altera Corporation Methods and apparatus for programmably powering down structured application-specific integrated circuits
US7404169B2 (en) 2005-05-31 2008-07-22 Altera Corporation Clock signal networks for structured ASIC devices
US7386819B1 (en) 2005-07-28 2008-06-10 Altera Corporation Methods of verifying functional equivalence between FPGA and structured ASIC logic cells
US7373630B1 (en) 2005-12-12 2008-05-13 Altera Corporation Methods for improved structured ASIC design
US8037444B1 (en) 2006-07-20 2011-10-11 Altera Corporation Programmable control of mask-programmable integrated circuit devices
US7587686B1 (en) 2006-08-01 2009-09-08 Altera Corporation Clock gating in a structured ASIC
US7451424B1 (en) 2006-08-11 2008-11-11 Xilinx, Inc. Determining programmable connections through a switchbox of a programmable logic device
US7536668B1 (en) 2006-08-11 2009-05-19 Xilinx, Inc. Determining networks of a tile module of a programmable logic device
US7451423B1 (en) 2006-08-11 2008-11-11 Xilinx, Inc. Determining indices of configuration memory cell modules of a programmable logic device
US7451420B1 (en) 2006-08-11 2008-11-11 Xilinx, Inc. Determining reachable pins of a network of a programmable logic device
US7451425B1 (en) 2006-08-11 2008-11-11 Xilinx, Inc. Determining controlling pins for a tile module of a programmable logic device
US7472370B1 (en) 2006-08-11 2008-12-30 Xilinx, Inc. Comparing graphical and netlist connections of a programmable logic device
US7584448B1 (en) * 2006-08-11 2009-09-01 Xilinx, Inc. Constructing a model of a programmable logic device
US7478359B1 (en) * 2006-10-02 2009-01-13 Xilinx, Inc. Formation of columnar application specific circuitry using a columnar programmable logic device
US7589555B1 (en) * 2007-01-08 2009-09-15 Altera Corporation Variable sized soft memory macros in structured cell arrays, and related methods
JP2008192967A (ja) * 2007-02-07 2008-08-21 Elpida Memory Inc 半導体装置及びその配線切り替えオプション
US7724031B2 (en) * 2007-03-21 2010-05-25 Altera Corporation Staggered logic array block architecture
US7924052B1 (en) 2008-01-30 2011-04-12 Actel Corporation Field programmable gate array architecture having Clos network-based input interconnect
US7586327B1 (en) 2008-03-25 2009-09-08 Altera Corporation Distributed memory circuitry on structured application-specific integrated circuit devices
US7622952B1 (en) 2008-05-28 2009-11-24 Altera Corporation Periphery clock signal distribution circuitry for structured ASIC devices
JP5453850B2 (ja) * 2009-03-06 2014-03-26 富士通セミコンダクター株式会社 半導体集積回路
US8105885B1 (en) 2010-08-06 2012-01-31 Altera Corporation Hardened programmable devices
WO2012032937A1 (ja) * 2010-09-08 2012-03-15 日本電気株式会社 再構成可能回路
WO2012047735A2 (en) * 2010-09-29 2012-04-12 The Regents Of The University Of California In-place resynthesis and remapping techniques for soft error mitigation in fpga
US8533641B2 (en) 2011-10-07 2013-09-10 Baysand Inc. Gate array architecture with multiple programmable regions
US8881082B2 (en) * 2012-12-19 2014-11-04 Infinera Corporation FEC decoder dynamic power optimization
WO2015069275A1 (en) * 2013-11-08 2015-05-14 Empire Technology Development Llc Control of router in cloud system
US9418231B2 (en) * 2014-06-03 2016-08-16 Empire Technology Development Llc Perturbation of field programmable gate array code to prevent side channel attack
US10394991B2 (en) 2016-10-06 2019-08-27 Altera Corporation Methods and apparatus for dynamically configuring soft processors on an integrated circuit
US10353709B2 (en) * 2017-09-13 2019-07-16 Nextera Video, Inc. Digital signal processing array using integrated processing elements

Family Cites Families (54)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4910417A (en) * 1986-09-19 1990-03-20 Actel Corporation Universal logic module comprising multiplexers
US5451887A (en) * 1986-09-19 1995-09-19 Actel Corporation Programmable logic module and architecture for field programmable gate array device
JPH03139863A (ja) * 1989-10-25 1991-06-14 Hitachi Ltd 半導体集積回路
JPH046913A (ja) * 1990-04-24 1992-01-10 Kawasaki Steel Corp プログラマブル論理素子
US5068547A (en) * 1990-09-05 1991-11-26 Lsi Logic Corporation Process monitor circuit
US5717928A (en) * 1990-11-07 1998-02-10 Matra Hachette Sa System and a method for obtaining a mask programmable device using a logic description and a field programmable device implementing the logic description
US5122685A (en) * 1991-03-06 1992-06-16 Quicklogic Corporation Programmable application specific integrated circuit and logic cell therefor
JPH05252025A (ja) * 1991-10-28 1993-09-28 Texas Instr Inc <Ti> 論理モジュールおよび集積回路
JPH06176102A (ja) * 1992-10-09 1994-06-24 Ricoh Co Ltd ゲートアレイ用ネットリスト発生装置
JP3139863B2 (ja) 1993-01-29 2001-03-05 ヤンマーディーゼル株式会社 舶用推進装置
US5550839A (en) * 1993-03-12 1996-08-27 Xilinx, Inc. Mask-programmed integrated circuits having timing and logic compatibility to user-configured logic arrays
JPH0785115A (ja) * 1993-09-10 1995-03-31 Toshiba Corp 論理回路の検査用データ収集装置及び検査用データ収集方法
KR960002333B1 (ko) * 1993-12-23 1996-02-16 재단법인한국전자통신연구소 논리 집적회로 모듈
TW396312B (en) * 1993-12-30 2000-07-01 At & T Corp Method and apparatus for converting field-programmable gate array implementations into mask-programmable logic cell implementations
US5502402A (en) * 1995-01-05 1996-03-26 Texas Instruments Incorporated FPGA architecture based on a single configurable logic module
US5671432A (en) * 1995-06-02 1997-09-23 International Business Machines Corporation Programmable array I/O-routing resource
JP3072888B2 (ja) * 1995-12-14 2000-08-07 川崎製鉄株式会社 フィールドプログラマブルゲートアレイ
US5841295A (en) * 1996-02-09 1998-11-24 Hewlett-Packard Company Hybrid programmable logic device
US5894565A (en) 1996-05-20 1999-04-13 Atmel Corporation Field programmable gate array with distributed RAM and increased cell utilization
US5825202A (en) * 1996-09-26 1998-10-20 Xilinx, Inc. Integrated circuit with field programmable and application specific logic areas
US5963050A (en) * 1997-02-26 1999-10-05 Xilinx, Inc. Configurable logic element with fast feedback paths
US5874834A (en) * 1997-03-04 1999-02-23 Xilinx, Inc. Field programmable gate array with distributed gate-array functionality
JPH10320451A (ja) * 1997-05-21 1998-12-04 Hitachi Telecom Technol Ltd ゲートアレイ用ネットデータ作成方法
US6097212A (en) * 1997-10-09 2000-08-01 Lattice Semiconductor Corporation Variable grain architecture for FPGA integrated circuits
JP3123977B2 (ja) 1998-06-04 2001-01-15 日本電気株式会社 プログラマブル機能ブロック
US6150838A (en) * 1999-02-25 2000-11-21 Xilinx, Inc. FPGA configurable logic block with multi-purpose logic/memory circuit
EP1533904A1 (en) * 1999-03-11 2005-05-25 Easic Corporation Integrated circuit technology
US6294926B1 (en) 1999-07-16 2001-09-25 Philips Electronics North America Corporation Very fine-grain field programmable gate array architecture and circuitry
US6331790B1 (en) * 2000-03-10 2001-12-18 Easic Corporation Customizable and programmable cell array
US6629294B2 (en) * 2000-03-10 2003-09-30 General Electric Company Tool and method for improving the quality of board design and modeling
US6490707B1 (en) * 2000-07-13 2002-12-03 Xilinx, Inc. Method for converting programmable logic devices into standard cell devices
US6515509B1 (en) * 2000-07-13 2003-02-04 Xilinx, Inc. Programmable logic device structures in standard cell devices
US6526563B1 (en) * 2000-07-13 2003-02-25 Xilinx, Inc. Method for improving area in reduced programmable logic devices
JP3862658B2 (ja) * 2001-05-16 2006-12-27 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ 再構成可能な論理デバイス
US6580289B2 (en) * 2001-06-08 2003-06-17 Viasic, Inc. Cell architecture to reduce customization in a semiconductor device
US6769107B1 (en) * 2001-12-03 2004-07-27 Lsi Logic Corporation Method and system for implementing incremental change to circuit design
US6911842B1 (en) * 2002-03-01 2005-06-28 Xilinx, Inc. Low jitter clock for a physical media access sublayer on a field programmable gate array
JP2003273727A (ja) * 2002-03-14 2003-09-26 Shinji Kimura 半導体集積回路装置
WO2003088095A1 (en) * 2002-04-17 2003-10-23 Fujitsu Limited Integrated circuit development method, program storage medium containing integrated circuit development method, system for concurrent development of asic and programmable logic device, development program, and development method
US6759869B1 (en) * 2002-06-05 2004-07-06 Xilinx, Inc. Large crossbar switch implemented in FPGA
US6873185B2 (en) * 2002-06-19 2005-03-29 Viasic, Inc. Logic array devices having complex macro-cell architecture and methods facilitating use of same
US7064579B2 (en) * 2002-07-08 2006-06-20 Viciciv Technology Alterable application specific integrated circuit (ASIC)
US7112994B2 (en) * 2002-07-08 2006-09-26 Viciciv Technology Three dimensional integrated circuits
US7679398B2 (en) * 2002-07-17 2010-03-16 Osann Jr Robert Reprogrammable instruction DSP
US7346876B2 (en) * 2002-09-04 2008-03-18 Darien K. Wallace ASIC having dense mask-programmable portion and related system development method
US6829756B1 (en) * 2002-09-23 2004-12-07 Xilinx, Inc. Programmable logic device with time-multiplexed interconnect
US6988258B2 (en) * 2002-12-09 2006-01-17 Altera Corporation Mask-programmable logic device with building block architecture
US6870395B2 (en) * 2003-03-18 2005-03-22 Lattice Semiconductor Corporation Programmable logic devices with integrated standard-cell logic blocks
JP2007524911A (ja) * 2003-06-23 2007-08-30 アルテラ コーポレイション マスクプログラム可能なロジックデバイスをプログラムする方法およびその方法によってプログラムされたデバイス
US7038490B1 (en) * 2003-09-12 2006-05-02 Lattice Semiconductor Corporation Delay-matched ASIC conversion of a programmable logic device
US7003746B2 (en) * 2003-10-14 2006-02-21 Hyduke Stanley M Method and apparatus for accelerating the verification of application specific integrated circuit designs
US7019557B2 (en) * 2003-12-24 2006-03-28 Viciciv Technology Look-up table based logic macro-cells
US7100142B2 (en) * 2004-04-07 2006-08-29 Synopsys, Inc. Method and apparatus for creating a mask-programmable architecture from standard cells
US7081772B1 (en) 2004-06-04 2006-07-25 Altera Corporation Optimizing logic in non-reprogrammable logic devices

Also Published As

Publication number Publication date
US8863061B2 (en) 2014-10-14
JP2012235499A (ja) 2012-11-29
JP2014131365A (ja) 2014-07-10
JP5475045B2 (ja) 2014-04-16
US7243329B2 (en) 2007-07-10
US8291355B2 (en) 2012-10-16
EP1612940A3 (en) 2007-08-22
US7870513B2 (en) 2011-01-11
US8504963B2 (en) 2013-08-06
US20070210827A1 (en) 2007-09-13
JP2006020329A (ja) 2006-01-19
US20130002295A1 (en) 2013-01-03
US20130314122A1 (en) 2013-11-28
JP5859089B2 (ja) 2016-02-10
JP2015008539A (ja) 2015-01-15
JP2012157054A (ja) 2012-08-16
US20110084727A1 (en) 2011-04-14
CN1716781A (zh) 2006-01-04
US20060001444A1 (en) 2006-01-05
EP1612940A2 (en) 2006-01-04
JP5623471B2 (ja) 2014-11-12

Similar Documents

Publication Publication Date Title
JP5859089B2 (ja) プログラマブル論理の特定用途向け集積回路等価物および関連の方法
US6271680B1 (en) Logic element for a programmable logic integrated circuit
US6184712B1 (en) FPGA configurable logic block with multi-purpose logic/memory circuit
US5828229A (en) Programmable logic array integrated circuits
US6288569B1 (en) Memory array with hard and soft decoders
US5587921A (en) Array of configurable logic blocks each including a look up table having inputs coupled to a first multiplexer and having outputs coupled to a second multiplexer
US6034540A (en) Programmable logic integrated circuit architecture incorporating a lonely register
US7733121B2 (en) Methods and apparatus for programmably powering down structured application-specific integrated circuits
US7573297B1 (en) Flexible macrocell interconnect
JPH04225621A (ja) 集積回路
JPH0653817A (ja) プログラマブル論理アレイ集積回路
GB2312067A (en) Programmable logic with lonely register
US7768819B2 (en) Variable sized soft memory macros in structured cell arrays, and related methods
US20080074142A1 (en) Routing for Microprocessor Busses
US7304499B1 (en) Distributed random access memory in a programmable logic device
JP2000232162A (ja) プログラマブルロジックｌｓｉ
US7406668B1 (en) Methods for producing mappings of logic suitable for FPGA and structured ASIC implementations
Chow et al. A high-speed FPGA using programmable mini-tiles
Grover F. Gail Gray

Legal Events

Date Code Title Description
A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20080701

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20080701

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A821

Effective date: 20110323

RD02 Notification of acceptance of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7422

Effective date: 20110323

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20110419

A601 Written request for extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A601

Effective date: 20110711

A602 Written permission of extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A602

Effective date: 20110714

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20110920

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20111208

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20120406

A911 Transfer of reconsideration by examiner before appeal (zenchi)

Free format text: JAPANESE INTERMEDIATE CODE: A911

Effective date: 20120416

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20120619

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20120703

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20150713

Year of fee payment: 3

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees