JP5034382B2 - TFT array inspection method and TFT array inspection apparatus - Google Patents

Description

  The present invention relates to a TFT array inspection process performed in a manufacturing process or the like of a liquid crystal substrate or the like, and more particularly to driving a TFT array when performing a TFT array inspection.

  In the manufacturing process of a semiconductor substrate on which a TFT array such as a liquid crystal substrate or an organic EL substrate is formed, a TFT array inspection process is included in the manufacturing process, and a defect inspection of the TFT array is performed in this TFT array inspection process.

  The TFT array is used as a switching element for selecting a pixel electrode of a liquid crystal display device, for example. In a substrate including a TFT array, for example, a plurality of gate lines functioning as scanning lines are arranged in parallel, and a plurality of source lines described as signal lines are arranged orthogonal to the gate lines. A TFT (Thin Film Transistor) is disposed in the vicinity of a portion where the lines intersect, and a pixel electrode is connected to the TFT.

  The liquid crystal display device is configured by sandwiching a liquid crystal layer between a substrate provided with the TFT array described above and a counter substrate, and a pixel capacitor is formed between the counter electrode and the pixel electrode provided in the counter substrate. In addition to the pixel capacitor, an additional capacitor (Cs) is connected to the pixel electrode. One of the additional capacitors (Cs) is connected to the pixel electrode, and the other is connected to the common line or the gate line. A TFT array configured to be connected to the common line is referred to as a Cs on Com type TFT array, and a TFT array configured to be connected to the gate line is referred to as a Cs on Gate type TFT array.

  In this TFT array, a scanning line (gate line) or a signal line (source line) is disconnected, a scanning line (gate line) and a signal line (source line) are short-circuited, or a pixel defect due to a characteristic defect of a TFT driving a pixel. In the defect inspection, for example, the counter electrode is grounded, a DC voltage of, for example, −15 V to +15 V is applied to all or part of the gate line at a predetermined interval, and an inspection signal is applied to all or part of the source line. By doing that. (For example, the prior art of patent document 1.)

  The TFT array inspection apparatus can detect a defect by inputting a driving signal for inspection to the TFT array and detecting the voltage state at that time. Further, the defect detection of the TFT array may be performed by observing the display state of the liquid crystal. When inspecting the TFT array by observing the display state of the liquid crystal, in addition to the inspection in the state of the liquid crystal display device in which the liquid crystal layer is sandwiched between the TFT array substrate and the counter electrode, the liquid crystal layer and the counter electrode are By attaching the provided inspection jig to the TFT array substrate, it is possible to inspect in the state of a semi-finished product that does not reach the liquid crystal display device.

  Various defects can occur in a TFT array during its manufacturing process. 10 to 13 are equivalent circuits of TFT arrays for explaining defect examples.

  FIG. 10 is a diagram for explaining a defect generated in each element portion constituting the TFT array. In each part indicated by a broken line in FIG. 10, a short-circuit defect (S-DSshort) is shown between the pixel 12oe and the source line 15e, and a short-circuit defect (G-DSshort) is shown between the pixel 12eo and the gate line 14e. A short-circuit defect (S-Gshort) is shown between the source line 15o and the gate line 14e, and a disconnection (D-open) is shown between the pixel 12ee and the TFT 11ee.

  In addition to the above-described defects in each pixel, there is a so-called adjacent defect that occurs between adjacent pixels. As this adjacent defect, a defect between adjacent pixels in the horizontal direction (referred to as horizontal PP), a defect between adjacent pixels in the vertical direction (referred to as vertical PP), a short circuit between adjacent source lines (referred to as SSshort), A short circuit (called GGshort) between adjacent gate lines is known.

  FIG. 11 is a view for explaining adjacent defects in the horizontal direction. The broken lines in FIG. 11 indicate a short-circuit defect (lateral PP) between pixels 12eo and 12ee adjacent in the horizontal direction and a short-circuit defect (SSshort) between source lines So and Se adjacent in the horizontal direction, respectively. Yes.

  FIG. 12 is a view for explaining adjacent defects in the vertical direction. A broken line in FIG. 12 indicates a short-circuit defect (vertical PP1) between pixels 12oo and 12eo adjacent in the vertical direction, a short-circuit defect (vertical PP2) between pixels 12oe and 12ee adjacent in the vertical direction, and the vertical direction. In FIG. 1, short-circuit defects (GGshort) between adjacent gate lines Go and Ge are shown.

  In a TFT array inspection apparatus using an electron beam, the pixel (ITO electrode) is irradiated with an electron beam, and secondary electrons emitted by this electron beam irradiation are detected and applied to the pixel (ITO electrode). The voltage waveform is changed to a secondary electron waveform and imaged by a signal, whereby the TFT array is electrically inspected.

  As a drive pattern for inspecting a defect generated in each pixel as shown in FIG. 10, for example, there is an inspection pattern as shown in FIG. 13A and 13B show gate signals, and FIGS. 13C and 13D show source signals. 13A and 13B and the source signal shown in FIGS. 13C and 13D, a positive voltage (here, 10v) and a negative voltage (here, −) are applied to all pixels of the TFT array. 10v) is applied alternately.

  FIGS. 15A and 15B show the voltage state of the pixel (ITO) generated when the same voltage (here, 10 v and −10 V) is applied to all the pixels.

  When a defect inspection is performed on the TFT array on the TFT substrate with a driving pattern that is uniformly driven as shown in FIG. 13, adjacent defects cannot be detected. Therefore, in the conventional defect inspection, in order to detect adjacent defects, an inspection pattern for laterally adjacent defects and an inspection pattern for longitudinally adjacent defects are used as independent inspection patterns. A laterally adjacent defect and a longitudinally adjacent defect are detected independently.

  FIG. 14 shows an inspection pattern for detecting an adjacent defect, and FIGS. 15C and 15D show the voltage state of a pixel (ITO) generated when driven by the inspection pattern shown in FIG. According to this inspection pattern, different potentials are applied to adjacent pixels.

  In addition to the above-described inspection pattern, various inspection patterns can be used as the inspection pattern for detecting adjacent defects. For example, when detecting a laterally adjacent defect, a positive voltage pixel (( The voltage is applied so that the voltage distribution formed by the ITO and negative voltage pixels (ITO) is a vertical stripe pattern. In this vertical stripe pattern, the pixels in the vertical direction of the TFT array have the same voltage, and the adjacent pixel rows in the horizontal direction have different voltages. Thereby, a laterally adjacent defect is detected.

When detecting vertical adjacent defects, a voltage is applied so that the voltage distribution formed by the positive voltage pixel (ITO) and the negative voltage pixel (ITO) on the TFT array becomes a horizontal stripe pattern. In this horizontal stripe pattern, the pixels in the horizontal direction of the TFT array have the same voltage, and the adjacent vertical pixel columns have different voltages. Thereby, the vertical adjacent defect is detected.
JP-A-5-307192

  In the above inspection pattern, a positive / negative symmetrical voltage is applied as a source voltage from the source line to the pixel (ITO). In the above example, + 10V and -10V are opposite in sign and voltages having the same absolute value are applied.

  The inventor of the present invention has found that when such an inspection pattern in which the applied voltage is positive and negative symmetrical is used, the sensitivity of defect detection may not be sufficiently obtained.

  In a TFT array inspection apparatus using an electron beam, a pixel (ITO electrode) is irradiated with an electron beam, and secondary electrons emitted by this electron beam irradiation are detected. The amount of secondary electrons emitted is There is a characteristic that the larger the potential of the pixel in the negative direction, the larger the potential.

  Therefore, for example, when a defect such as a short circuit or a resistance connection occurs between adjacent pixels, when a positive and negative symmetrical voltage is applied as a test pattern, the secondary electrons detected from the pixel are the average voltage of both pixels. Therefore, there is a problem that it is difficult to obtain sufficient detection signal intensity and high defect detection sensitivity.

  SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to solve the above-described problems and increase the defect detection sensitivity in TFT array inspection.

  The present invention relates to a TFT substrate inspection method for inspecting defects in a TFT array by applying a voltage to the TFT array of the TFT substrate and detecting secondary electrons obtained by electron beam irradiation. In FIG. 5, a positive voltage and a negative voltage are alternately applied to the pixel electrode of the TFT array, and the potential of the pixel electrode is offset to the negative side.

  The offset of the potential of the pixel electrode to the negative side is performed by making the absolute value of the negative voltage larger than the absolute value of the positive voltage in the positive voltage and the negative voltage applied alternately to the pixel electrode.

  By offsetting the potential of the pixel electrode to the negative side, the detection sensitivity of the potential of the pixel electrode can be improved by increasing the amount of secondary electrons emitted by irradiating the pixel voltage with an electron beam.

  For example, by capacitive coupling between a source line for supplying an inspection signal and the pixel electrode, the potential of the pixel electrode is drawn to the negative voltage side applied to the source line, and by drawing to the negative potential side, an electron beam is applied to the pixel electrode. The amount of secondary electrons emitted from the pixel electrode when irradiated with can be increased. By increasing the amount of secondary electrons emitted, the signal intensity of the defect signal is increased, the S / N ratio is improved, and the detection sensitivity of the potential of the pixel electrode can be improved.

  In addition, in the adjacent defect, the voltage applied to the adjacent pixel electrode is alternately set to a positive and negative voltage, and the pixel electrode having the adjacent defect is irradiated with an electron beam by offsetting the potential of the pixel electrode to the negative side. The amount of secondary electrons emitted from the pixel electrode is increased, thereby increasing the signal intensity of the defect signal, improving the S / N ratio, and improving the detection sensitivity of the potential of the pixel electrode.

  In addition, the secondary electron waveform detected when a positive / negative asymmetric voltage is applied to the TFT array changes compared to the secondary electron waveform detected when a positive / negative symmetrical voltage is applied to the TFT array. Since it becomes large, the sensitivity of the defect detection by a secondary electron waveform can be improved.

  The predetermined period can be a gate period, and the voltage applied to the pixel electrodes of all TFT arrays can be switched for each gate period.

  Further, the predetermined period may be a gate period, and the voltage applied to the pixel electrode of the adjacent TFT array can be alternately switched within the gate period.

  More specifically, a plurality of gate lines and source lines are arranged for each TFT array including a TFT having a gate connected to a gate line, a source connected to a source line, and a drain connected to a pixel electrode. Are divided into two gate line groups and two source line groups, and a positive voltage and a negative voltage are applied to each other between the two source line groups while shifting the time from each other. A positive voltage and a negative voltage are alternately applied to adjacent pixel electrodes of the TFT array by applying an on-pulse signal with a shift.

  Within one gate period, the voltage distribution voltage can be switched alternately by reversing the phase relationship between the drive voltage of the source line group and the on-pulse signal of the gate line group.

  In the voltage distribution in this voltage distribution, an on-pulse signal is applied to one gate line group while a positive voltage is applied to one source line group in the first period within one gate period, and then the other An on-pulse signal is applied to the other gate line group while a positive voltage is applied to the source line group, and an on-pulse signal is applied to the other gate line group while a positive voltage is applied to one source line group in the second period. And then applying an on-pulse signal to one gate line group while applying a positive voltage to the other source line group.

  Further, the present invention can be an aspect of an inspection apparatus for a TFT substrate. In this aspect of the inspection apparatus, a voltage is applied to the TFT array of the TFT substrate, and the voltage state by the voltage application is obtained by electron beam irradiation. A TFT substrate inspection device that detects defects in the TFT array by detecting by secondary electrons generated, an electron beam source that irradiates the TFT substrate with an electron beam, and a detector that detects secondary electrons emitted from the TFT substrate And an inspection signal generation unit that generates and applies an inspection signal to the TFT array of the TFT substrate, and a defect detection unit that detects a defect of the TFT array based on the detection signal of the detector. The inspection signal generation unit alternately applies a positive voltage and a negative voltage to the pixel electrodes of the TFT array within a predetermined period, and offsets the average potential of the pixel electrodes within the predetermined period to the negative side.

  According to the present invention, it is possible to increase the defect detection sensitivity in TFT array inspection.

  Further, according to the aspect of the present invention, the potential of the pixel electrode is drawn to the negative voltage side applied to the source line by capacitive coupling between the source line that supplies the inspection signal and the pixel electrode, By pulling in, the amount of secondary electrons emitted from the pixel electrode when the pixel electrode is irradiated with an electron beam can be increased. By increasing the amount of secondary electrons emitted, the signal intensity of the defect signal is increased. And the S / N ratio can be improved, and the detection sensitivity of the potential of the pixel electrode can be improved.

  Further, according to the aspect of the present invention, in the adjacent defect, the voltage applied to the adjacent pixel electrode is alternately changed to a positive / negative voltage, and the pixel electrode having the adjacent defect is offset by offsetting the potential of the pixel electrode to the negative side. Detecting the potential of the pixel electrode by increasing the amount of secondary electrons emitted from the pixel electrode when irradiated with an electron beam, thereby increasing the signal strength of the defect signal and improving the S / N ratio. Sensitivity can be improved.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a schematic view of a TFT array inspection apparatus of the present invention.

  The TFT array inspection apparatus 1 includes an inspection signal generation unit 4 that generates an inspection signal for array inspection on the TFT substrate 10, a prober 8 that applies the inspection signal generated by the inspection signal generation unit 4 to the TFT substrate 10, and a TFT substrate. A mechanism (2, 3, 5) for detecting the voltage application state of the TFT and a defect detector 6 for detecting a defect of the TFT array based on the detection signal.

  The prober 8 includes a prober frame provided with probe pins (not shown). The prober 8 contacts the electrode formed on the TFT substrate 10 by placing the probe pin on the TFT substrate 10 and applies an inspection signal to the TFT array.

  The mechanism for detecting the voltage application state of the TFT substrate can have various configurations. The configuration shown in FIG. 1 is a detection configuration using an electron beam. An electron beam source 2 that irradiates an electron beam on the TFT substrate 10 and a secondary electron that detects secondary electrons emitted from the TFT substrate 10 by the irradiated electron beam. The secondary electron detector 3 and the secondary electron detector 3 are provided with a signal processing unit 5 that performs signal processing on detection signals from the secondary electron detector 3 and detects a potential state on the TFT substrate 10.

  Since the TFT array irradiated with the electron beam emits secondary electrons corresponding to the voltage of the applied inspection signal, the potential state of the TFT array can be detected by detecting the secondary electrons.

  The defect detection unit 6 detects defects in the TFT array by comparing with the potential state in the normal state based on the potential state of the TFT array acquired by the signal processing unit 5.

  Here, a configuration example is shown in which a TFT array defect is detected using a mechanism (2, 3, 5) that detects the voltage application state of the TFT substrate. However, the TFT substrate constitutes a liquid crystal display device. If there is a display, a liquid crystal is driven by the inspection signal to display a display pattern based on the inspection signal, and this display state is imaged by the image pickup device and image processing is performed on the acquired image to perform defect inspection. The image may be observed visually. In the case where the TFT substrate is provided with only the TFT array, a liquid crystal display device is temporarily formed by providing a liquid crystal layer and a counter electrode on a jig for applying an inspection signal, and a defect is generated as described above. An inspection may be performed.

  The inspection signal generation unit 4 generates an inspection signal inspection pattern for driving the TFT array formed on the TFT substrate 10. This inspection pattern will be described later.

  The scanning control unit 9 controls the stage 7 and the electron source 2 in order to scan the inspection position of the TFT array on the TFT substrate 10. The stage 7 moves the TFT substrate 10 to be placed in the XY direction, and the electron source 2 scans the irradiation position of the electron beam by shaking the electron beam irradiating the TFT substrate 10 in the XY direction. The scanning position becomes the detection position.

  The above-described configuration of the TFT array inspection apparatus is an example, and is not limited to this configuration.

  Next, the inspection signals used for the inspection of the TFT substrate of the present invention will be described with reference to FIGS. 2 and 3 for the Cs on Com type TFT array, and FIGS. 4 and 5 for the case of the Cs on Gate type TFT array. Will be described.

  Here, the Cs on Com type TFT array has a configuration in which one connection end of the additional capacitor (Cs) connected to the pixel electrode is connected to a common line (Cs line). One connection end of the additional capacitor (Cs) connected to the pixel electrode is connected to the gate line (Gate line).

  First, the case of a Cs on Com type TFT array will be described.

  FIG. 2 schematically shows the configuration of a Cs on Com TFT array. On the TFT substrate, a TFT is provided in a TFT area 11A in the vicinity of a portion where the array gate line 14 and the source line 15 intersect. Further, a Cs line 16 for connecting an additional capacitor (Cs) is provided between adjacent gate lines 14.

  FIG. 3 shows an equivalent circuit of the Cs on Com type TFT array shown in FIG. In the equivalent circuit of FIG. 3, the gate line 14 and the source line 15 are illustrated as being driven by being divided into even-numbered and odd-numbered two line groups, respectively.

  A pixel 12oo is provided in the vicinity of a portion where the odd-numbered gate line 14o and the odd-numbered source line 15o intersect. One end of the pixel (Pixel) 12oo is connected to the TFT 11oo, and the other end is connected to the additional capacitor (Cs) 13oo. The other end of the additional capacitor (Cs) 13oo is connected to the Cs line 16. The drain D of the TFT 11oo is connected to the pixel 12oo, the gate G is connected to the odd-numbered gate line 14o, and the source S is connected to the odd-numbered source line 15o.

  Similarly, a pixel 12oe is provided in the vicinity of a portion where the odd-numbered gate line 14o and the even-numbered source line 15e intersect. One end of the pixel (Pixel) 12oe is connected to the TFT 11oe, and the other end is connected to the additional capacitor (Cs) 13oe. The other end of the additional capacitor (Cs) 13oe is connected to the Cs line 16. The drain D of the TFT 11oe is connected to the pixel 12oe, the gate G is connected to the odd-numbered gate line 14o, and the source S is connected to the even-numbered source line 15e.

  Further, a pixel 12eo is provided in the vicinity of a portion where the even-numbered gate line 14e and the odd-numbered source line 15o intersect. One end of the pixel (Pixel) 12eo is connected to the TFT 11eo, and the other end is connected to an additional capacitor (Cs) 13eo. The other end of the additional capacitor (Cs) 13eo is connected to the Cs line 16. The drain D of the TFT 11eo is connected to the pixel 12eo, the gate G is connected to the even-numbered gate line 14e, and the source S is connected to the odd-numbered source line 15o.

  Further, a pixel 12ee is provided in the vicinity of a portion where the even-numbered gate line 14e and the even-numbered source line 15e intersect. One end of the pixel 12ee is connected to the TFT 11ee, and the other end is connected to the additional capacitor (Cs) 13ee. The other end of the additional capacitor (Cs) 13ee is connected to the Cs line 16. The drain D of the TFT 11ee is connected to the pixel 12ee, the gate G is connected to the even-numbered gate line 14e, and the source S is connected to the even-numbered source line 15e.

  Accordingly, the voltage of the odd-numbered source line 15o is applied to the pixel (Pixel) 12oo according to the on-pulse signal of the odd-numbered gate line 14o, and the on-pulse of the odd-numbered gate line 14o is applied to the pixel (Pixel) 12oe. The voltage of the even-numbered source line 15e is applied according to the signal, and the voltage of the odd-numbered source line 15o is applied to the pixel (Pixel) 12eo according to the on-pulse signal of the even-numbered gate line 14e. Pixel) 12ee is applied with the voltage of the even-numbered source line 15e in accordance with the on-pulse signal of the even-numbered gate line 14e.

  Next, the case of a Cs on Gate type TFT array will be described.

  FIG. 4 schematically shows the configuration of a Cs on Gate type TFT array. On the TFT substrate, a TFT is provided in a TFT area 11A in the vicinity of a portion where the array gate line 14 and the source line 15 intersect.

  FIG. 5 shows an equivalent circuit of the Cs on Gate type TFT array shown in FIG. In the equivalent circuit of FIG. 5, the gate line 14 and the source line 15 are illustrated as being divided into two even-numbered and odd-numbered line groups.

  A pixel 12oo is provided in the vicinity of a portion where the odd-numbered gate line 14o and the odd-numbered source line 15o intersect. One end of the pixel (Pixel) 12oo is connected to the TFT 11oo, and the other end is connected to the additional capacitor (Cs) 13oo. The other end of the additional capacitor (Cs) 13oo is connected to the even-numbered gate line 14e. The drain D of the TFT 11oo is connected to the pixel 12oo, the gate G is connected to the odd-numbered gate line 14o, and the source S is connected to the odd-numbered source line 15o.

  Similarly, a pixel 12oe is provided in the vicinity of a portion where the odd-numbered gate line 14o and the even-numbered source line 15e intersect. One end of the pixel (Pixel) 12oe is connected to the TFT 11oe, and the other end is connected to the additional capacitor (Cs) 13oe. The other end of the additional capacitor (Cs) 13oe is connected to the even-numbered gate line 14e. The drain D of the TFT 11oe is connected to the pixel 12oe, the gate G is connected to the odd-numbered gate line 14o, and the source S is connected to the even-numbered source line 15e.

  Further, a pixel 12eo is provided in the vicinity of a portion where the even-numbered gate line 14e and the odd-numbered source line 15o intersect. One end of the pixel (Pixel) 12eo is connected to the TFT 11eo, and the other end is connected to the additional capacitor (Cs) 13eo. The other end of the additional capacitor (Cs) 13eo is connected to the odd-numbered gate line 14o. The drain D of the TFT 11eo is connected to the pixel 12eo, the gate G is connected to the even-numbered gate line 14e, and the source S is connected to the even-numbered source line 15e.

  Further, a pixel 12ee is provided in the vicinity of a portion where the even-numbered gate line 14e and the even-numbered source line 15e intersect. One end of the pixel 12ee is connected to the TFT 11ee, and the other end is connected to the additional capacitor (Cs) 13ee. The other end of the additional capacitor (Cs) 13ee is connected to the odd-numbered gate line 14o. The drain D of the TFT 11ee is connected to the pixel 12ee, the gate G is connected to the even-numbered gate line 14e, and the source S is connected to the even-numbered source line 15e.

  Accordingly, the voltage of the odd-numbered source line 15o is applied to the pixel (Pixel) 12oo according to the on-pulse signal of the odd-numbered gate line 14o, and the on-pulse of the odd-numbered gate line 14o is applied to the pixel (Pixel) 12oe. The voltage of the even-numbered source line 15e is applied according to the signal, and the voltage of the odd-numbered source line 15o is applied to the pixel (Pixel) 12eo according to the on-pulse signal of the even-numbered gate line 14e. Pixel) 12ee is applied with the voltage of the even-numbered source line 15e in accordance with the on-pulse signal of the even-numbered gate line 14e.

  Hereinafter, signal pattern examples of the inspection signal according to the present invention will be described using the inspection signal examples of FIGS. 6 and 7 and the applied voltage example of the pixel of FIG.

  6 and 7 show the signal pattern of the inspection signal within one gate period of the present invention, which can be commonly used for the Cs on Com type TFT array and the Cs on Gate type TFT array. Hereinafter, description will be given using an example of the Cs on Com type TFT array shown in FIG.

  In the signal pattern of the inspection signal shown in FIGS. 6 and 7, for example, gate lines 14 (14o (Go in FIGS. 6A and 7A), 14e (FIGS. 6B and 7B) are used. Ge)) on-pulse signals are output at equal time intervals within one gate period. At this time, the source lines 15 (15o (So in FIGS. 6 (c) and 7 (c)), 15e (FIG. 6 ( d) The voltage applied to Se) in FIG. 7D is passed through each TFT 11 (11oo, 11oe, 11eo, 11ee) to the pixel 12 (12oo, 12oe, 12eo, 12ee) at each intersection. Apply.

  At this time, depending on the combination of the voltage of the gate line 14 and the voltage of the source line 15 and the switching of the voltages, each pixel (Pixel) 12 (12oo, 12oe, 12eo, 12ee) has a different voltage for each adjacent pixel. Apply. At this time, in the signal pattern of the inspection signal of the present invention, the source lines 15o (So in FIGS. 6C and 7C) and 15e (Se in FIGS. 6D and 7D) are further provided. )), The positive voltage and the negative voltage are made asymmetric and offset to the negative potential side. Here, the positive voltage is + 8V and the negative voltage is −12V.

  Note that one gate period (period shown by 1 to 10 in FIGS. 6 and 7) can be set to an arbitrary time width, but can be set to 16 msec as an example.

  In the example of FIG. 6, for convenience of explanation, one gate period is indicated by 10 time intervals of 1 to 10, and this one gate period is indicated by a first period (indicated by 1 to 5) and a second period (6 to 6). In the first period, the pixel (Pixel) holds + voltage (+ 8V), and in the second period, the pixel (Pixel) holds −voltage (−12V).

  In the first period (the period indicated by 1 to 5 in FIG. 6), on-pulse signals are generated on the gate line Go and the gate line Ge (FIGS. 6A and 6B). At this time, a positive voltage (+8 V) is applied to the source line So in a period corresponding to the on-pulse signal of the gate line Go, and then a negative voltage (−12 V) is applied (FIG. 6C). Further, a positive voltage (+ 8V) is applied to the source line Se in a period corresponding to the on-pulse signal of the gate line Ge, and then a negative voltage (−12V) is applied (FIG. 6D).

  In the second period shown by 6 in FIG. 6, an on-pulse signal is generated on the gate line Go and the gate line Ge (FIGS. 6A and 6B). At this time, the source line So and the source line Se are kept in a state where a negative voltage (-12V) is applied (FIGS. 6C and 6D).

  Due to the on-pulse signal and the applied voltage, the pixels (pixels) 12oo, 12ee, 12oe, 12eo are held at a positive voltage (+ 8V) in the first period, and the pixels (pixels) 12oo, 12ee, 12e, in the second period. 12oe and 12eo are held at -voltage (-12V).

  FIG. 8A shows the voltage state of the pixel 12 in the first period, and all the pixels are held at + voltage (+ 8V). FIG. 8B shows the voltage state of the pixel (pixel) 12 in the second period, and all the pixels are held at −voltage (−12V).

  Next, FIG. 7 shows another signal pattern example of the inspection signal. Also in the example of FIG. 7, for convenience of explanation, one gate period is indicated by 10 time intervals of 1 to 10, and this one gate period is indicated by a first period (indicated by 1 to 5) and a second period (6 In the first period and the second period, a positive voltage (+8 V) and a negative voltage (−12 V) are alternately held in the pixel (Pixel).

  In the first period (the period indicated by 1 to 5 in FIG. 7), on-pulse signals are generated on the gate line Go and the gate line Ge (FIGS. 7A and 7B).

  First, an on-pulse signal is generated on the gate line Go (FIG. 7A), and then an on-pulse signal is generated on the gate line Ge (FIG. 7B). At this time, a negative voltage (−12 V) is applied to the source line So after a positive voltage (+8 V) is applied in a period corresponding to the on-pulse signal of the gate line Go (FIG. 7C). Further, a negative voltage (−12 V) is applied to the source line Se after a positive voltage (+8 V) is applied in a period corresponding to the on-pulse signal of the gate line Ge (FIG. 7D).

  Depending on the on-pulse signal of the gate line and the applied voltage of the source line, in the first period, the + voltage (+ 8V) is applied in the periods 1 to 5 and 6 to 10 in FIGS. ) And −voltage (−12V) are alternately held.

  FIG. 8C shows the voltage state of the pixel (pixel) 12 in the first period, and FIG. 8D shows the voltage state of the pixel (pixel) 12 in the second period. Among the pixels of the TFT array, adjacent pixels hold alternately a + voltage (+ 8V) and a −voltage (−12V), and the positive and negative are switched between the first period and the second period.

  Next, simulation results for detecting adjacent defects by applying a positive / negative asymmetric voltage inspection pattern of the present invention will be described. Here, a simulation is performed using an equivalent circuit of the TFT array shown in FIG. In the equivalent circuit of this TFT array, the capacitances Cs1 to Cs6 of each pixel are 0.3 pF, the resistances Rp1 and Rp2 of the gate lines between the pixels are 20 kΩ, and the capacitances Cp1 and Cp2 are 400 pF. Further, as a defect between pixels adjacent in the horizontal direction, the resistance between t1 of pixel 1 and t2 of pixel 2 is set to 100Ω.

  In the above-mentioned equivalent circuit of the TFT array, when positive and negative symmetrical voltages of +10 V and −10 V are applied as source voltages, the simulation result of the pixel voltage is 9.1419 V (when the source voltage +10 V is applied) for a normal pixel. -11.532 V (when source voltage −10 V is applied), on the other hand, for the pixel having the above-described adjacent defect, it is −5 both when +10 V source voltage is applied and when −10 V source voltage is applied. 275V.

  On the other hand, according to the present invention, when positive and negative asymmetric voltages of +8 V and −12 V are applied as source voltages, the simulation result of pixel voltage is 7.6228 V (when source voltage +8 V is applied) for normal pixels. −13.67V (when source voltage −12V is applied), on the other hand, for the pixel having the adjacent defect described above, it is −6 both when + 8V source voltage and −12V source voltage are applied. .99V.

  Therefore, according to the simulation result, when the conventional positive / negative symmetric voltage is applied, the pixel voltage is −5.275V, whereas when the positive / negative asymmetric voltage of the present invention is applied, the pixel voltage is The voltage of the defective pixel increases from −5.275 V to −6.99 V in the negative voltage direction. In defect inspection with an electron beam, this pixel voltage is detected by detecting secondary electrons obtained by electron beam irradiation, and the emission of secondary electrons increases as the target potential becomes negative. Therefore, it is expected that high detection sensitivity can be obtained.

  In the above description, the Cs on Com type TFT array is taken as an example, but the same applies to the case of the Cs on Gate type TFT array, and the description is omitted.

  The present invention can be applied not only to a TFT array inspection process in a liquid crystal manufacturing apparatus but also to a defect inspection of a TFT array provided in an organic EL or various semiconductor substrates.

It is the schematic of the TFT array test | inspection apparatus of this invention. It is a figure which shows typically the structure of a Cs on Com type | mold TFT array. It is an equivalent circuit diagram of a Cs on Com type TFT array. It is a figure which shows typically the structure of a Cs on Gate type TFT array. It is an equivalent circuit diagram of a Cs on Gate type TFT array. It is an example of a test signal of a signal pattern example of a test signal according to the present invention. It is an example of a test signal of a signal pattern example of a test signal according to the present invention. It is a figure which shows the voltage state of the pixel (pixel) of this invention. It is a figure which shows the equivalent circuit of the TFT array used for the simulation of this invention. It is a figure for demonstrating the defect of a TFT array. It is a figure for demonstrating a horizontal direction adjacent defect. It is a figure for demonstrating the adjacent defect of a vertical direction. It is an inspection pattern for detecting a defect. It is a test | inspection pattern for detecting a horizontal direction adjacent defect. It is a figure which shows the voltage state of the pixel (ITO) which generate | occur | produces when driving with a test | inspection pattern.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... TFT array inspection apparatus, 2 ... Electron source, 3 ... Secondary electron detector, 4 ... Inspection signal production | generation part, 5 ... Signal processing part, 6 ... Defect detection part, 7 ... Stage, 8 ... Probe, 9 ... Scanning Control part, 10 ... TFT substrate, 11 ... TFT, 11A ... TFT area, 12 ... Pixel electrode, 13 ... Addition capacitor, 14 ... Gate line, 15 ... Source line, 16 ... Cs line.

Claims (6)

A TFT array inspection method for inspecting defects in a TFT array by detecting secondary electrons obtained by applying a voltage to a TFT array of a TFT substrate and irradiating an electron beam to a pixel electrode ,
A method for inspecting a TFT array , wherein a positive voltage and a negative voltage are alternately applied to a pixel electrode of a TFT array within a predetermined period, and the potential of the pixel electrode is offset to the negative side. 2. The TFT array inspection method according to claim 1, wherein the potential of the pixel electrode is offset to the negative side by making the absolute value of the negative voltage larger than the absolute value of the positive voltage. 3. The TFT array inspection method according to claim 1, wherein the predetermined period is a gate period, and the voltage applied to the pixel electrodes of all TFT arrays is switched. 3. The TFT array inspection method according to claim 1, wherein the predetermined period is a gate period, and a voltage applied to a pixel electrode of an adjacent TFT array is alternately switched. For a TFT array comprising a TFT with a gate connected to the gate line, a source connected to the source line, and a drain connected to the pixel electrode,
Dividing a plurality of gate lines and source lines into two gate line groups and two source line groups every other line,
Between the two source line groups, applying a positive voltage and a negative voltage while shifting the time,
2. A positive voltage and a negative voltage are alternately applied to adjacent pixel electrodes of a TFT array by applying an on-pulse signal between the two gate line groups while shifting the time from each other. 5. The inspection method for the TFT array according to any one of items 1 to 4. A voltage is applied to the TFT array on the TFT substrate, and the voltage state due to the voltage application is detected by secondary electrons obtained by irradiating an electron beam to the pixel electrode, and a TFT array for inspecting defects in the TFT array An inspection device,
An electron beam source for irradiating the TFT substrate with an electron beam;
A detector for detecting secondary electrons emitted from the TFT substrate;
An inspection signal generator for generating and applying an inspection signal to the TFT array on the TFT substrate;
A defect detection unit that detects a defect of the TFT array based on a detection signal of the detector;
The inspection signal generator is
A TFT array inspection apparatus, wherein a positive voltage and a negative voltage are alternately applied to a pixel electrode of a TFT array within a predetermined period, and an average potential of the pixel electrode within the predetermined period is offset to the negative side.

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