KR20110066753A

KR20110066753A - Auto probe inspection method

Info

Publication number: KR20110066753A
Application number: KR1020090123522A
Authority: KR
Inventors: 박정욱
Original assignee: 엘지디스플레이 주식회사
Priority date: 2009-12-11
Filing date: 2009-12-11
Publication date: 2011-06-17

Abstract

The present invention relates to an auto probe inspection method of the present invention, wherein in performing an auto probe inspection on an electrophoretic panel, it is possible to detect a defective pixel having a leakage current between pixels, thereby improving the defect detection rate. It is about. In the method according to the preferred embodiment of the present invention, a plurality of pixels are defined by crossing a gate line and a data line, and a first test pad connected to an odd-numbered gate line and a second test line connected to an even-numbered gate line. Preparing an electrophoretic panel having a third test pad connected to the pad and the odd-numbered data line and a fourth test pad connected to the even-numbered data line; Inputting a first test signal to the first test pad and a third and fourth test signal to each of the third and fourth test pads; Inputting a second test signal to the second test pad and inputting a third and fourth test signal to each of the third and fourth test pads; And observing the defect by observing the electrophoretic panel in which the inspection pattern is implemented. The first and second test signals include a positive voltage section, a negative voltage section, and a reference voltage section, and the third and fourth test signals include a stabilization section and a data voltage section. Portions of the reference voltage sections of the first and second test signals overlap part of the data voltage sections of the third and fourth test signals.

Electrophoretic Panel, Auto Probe Inspection, Leakage Current

Description

AUTO PROBE INSPECTION METHOD}

The present invention relates to an auto probe inspection method of the present invention, wherein in performing an auto probe inspection on an electrophoretic panel, it is possible to detect a defective pixel having a leakage current between pixels, thereby improving the defect detection rate. It is about.

An electrophoretic display is an image display device using a phenomenon in which colloidal particles move to either polarity when a pair of electrodes to which voltage is applied is immersed in a colloidal solution.

Such an electrophoretic display device is manufactured by using a flexible substrate, so that flexibility is added to provide excellent portability, light weight, and thinness, and even when the power is turned off, data is not erased without power for a predetermined period of time. There is an advantage.

The electrophoretic display device includes an electrophoretic panel having an upper substrate on which a common electrode is formed, a lower substrate on which a plurality of pixels are defined, and an electrophoretic film formed between the two substrates, and scanning signals and image information on the electrophoretic panel. It comprises a drive unit for supplying and operating.

An electrophoretic display device having such a configuration includes a process of forming an upper substrate and a lower substrate, a process of forming an electrophoretic panel by forming an electrophoretic film between the upper substrate and the lower substrate, and inspecting the electrophoretic panel. It is made through a number of tests, including auto probe tests.

The auto probe inspection is performed by applying a predetermined signal to an electrophoretic panel which is an object to be inspected through an auto probe inspection device to determine whether the pixel is normally driven or defective. FIG. When described in detail with reference to as follows.

1 shows a circuit diagram of a conventional general electrophoretic panel.

A conventional electrophoretic panel includes a first substrate in which a plurality of pixels are defined by crossing a gate line GL and a data line DL, and a second substrate disposed to face the first substrate. An electrophoretic film is formed between the first substrate and the second substrate.

In each pixel, a thin film transistor TR is formed in an area where the gate line GL and the data line DL intersect, and a pixel electrode connected to the thin film transistor TR is formed in each pixel. In addition, a common electrode (not shown) is formed on the second substrate to drive an electrophoretic film by forming an electric field together with the pixel electrode.

Although not shown in detail in the drawings, the conventional general electrophoretic panel having the configuration as described above is formed with first and second test pads, third and fourth test pads for use in auto probe inspection. In this case, the first and second test pads and the third and fourth test pads are used only when performing an auto probe test, and after the manufacturing of the electrophoretic panel is completed, the gate lines are not connected to the first and second test pads. And the data line is connected to the gate driver without being connected to the third and fourth test pads.

The first test pad is connected to the entire odd-numbered gate line GL. As a result, the first test pad receives a first test signal from the auto-probe test apparatus at the time of the auto-probe test and connects to the odd-numbered gate line GL. The odd-numbered gate lines GL are driven simultaneously by supplying the second test pads to the entire even-numbered gate lines GL. Thus, the second test pads are separated from the auto-probe test apparatus at the time of the auto probe test. The even-numbered gate line GL is driven simultaneously by receiving the second test signal and supplying it to the even-numbered gate line GL.

The third test pad is connected to the entire odd-numbered data line DL. As a result, the third test pad receives a third test signal from the auto-probe test apparatus during the auto-probe test, and then the odd-numbered data line DL. ), And the fourth test pad is connected to the entire even-numbered data line DL, so that the fourth test pad receives the fourth test signal from the auto-probe test device during the auto-probe test and receives even-numbered data. Supply to the line DL.

2A and 2B show waveform diagrams of test signals applied to two adjacent pixels in an electrophoretic panel when performing an auto probe test on a conventional general electrophoretic panel having the above configuration. 2A illustrates an inspection signal applied to the first pixel 1 located at the upper left of the four pixels of FIG. 1, where the first waveform is the first inspection signal S1 and the second waveform is the third inspection signal S3. FIG. 2B illustrates an inspection signal applied to a second pixel located at the upper right side among the four pixels of FIG. 1, wherein the first waveform is the first inspection signal S1 and the second waveform is the fourth inspection signal S4. )to be.

Referring to FIG. 2A, the first test signal S1 includes a reference voltage section T1, a positive polarity section T2, a negative polarity section T3, and a reference voltage section T4, and includes a third test signal. S3 includes a reference voltage section T5, a stabilization section T6, a data voltage section T7, and a reference voltage section T8. At this time, a negative data voltage is generated in the data voltage section T7 in the third test signal S3.

More specifically, in the P1 and P7 sections of FIG. 2A, both the first test signal S1 and the third test signal S3 have the same level as the reference voltage, that is, the level of the common voltage applied to the common electrode. In the P2 section, since the first test signal S1 is positive and the third test signal S3 is positive, the first pixel 1 displays a black image, and in the P3 section, a third image is displayed. Since the inspection signal S3 is at the same level as the reference voltage, there is no change in the display image of the first pixel pixel 1, and in the P4 section, the third inspection signal S3 is negative, so that the first pixel pixel 1 does not change. Displays a white image, and in the P5 section, since the third test signal S3 generates a negative data voltage, the first pixel pixel 1 displays an image corresponding to the negative data voltage. In the P6 section, since the first test signal S1 is converted to negative polarity, The first pixel 1 does not change the displayed image.

Referring to FIG. 2B, as described above, the first test signal S1 repeats the reference voltage section T1, the positive polarity section T2, the negative polarity section T3, and the reference voltage section T4. In the fourth test signal S4, the reference voltage section T5, the stabilization section T6, the data voltage section T7, and the reference voltage section T8 are repeated. In this case, the data voltage of positive polarity is generated in the data voltage section T7 in the fourth test signal S4.

More specifically, in the periods P1 and P7 of FIG. 2B, the first test signal S1 and the fourth test signal S4 are both at the same level as the reference voltage, that is, the level of the common voltage applied to the common electrode. In the P2 section, since the first test signal S1 is positive and the fourth test signal S4 is positive, the second pixel 2 displays a black image, and in the P3 section, the fourth image is black. Since the inspection signal S4 is at the same level as the reference voltage, there is no change in the display image of the second pixel 2, and in the P4 section, the fourth inspection signal S4 is negative, so the second pixel 2 Displays a white image, and in the P5 section, since the fourth test signal S4 generates a positive data voltage, the second pixel (pixel 2) displays an image that matches the positive data voltage. Since the first test signal (S1) is switched to the negative polarity The second pixel pixel 2 does not change the display image.

First test signal S1 in the case where the first test signal S1 is applied to the first test pad and the third and fourth test signals S3 and S4 are applied to the third and fourth test pads, respectively. ) And the third and fourth test signals S3 and S4, the second test signal is applied to the second test pad and the third and fourth test signals S3 and 4 are respectively applied to the third and fourth pads. In the case of applying S4), since only the polarities of the data voltage sections of the third and fourth test signals are opposite to those of the case where the first test signal S1 is applied to the first test pad, the second test pad needs to be applied to the second test pad. In the case where the second test signal is applied and the third and fourth test signals are applied to the third and fourth pads, the detailed description of the second test signal and the third and fourth test signals will be omitted.

The first to fourth test signals as described above are applied to the first to fourth test pads of the electrophoretic panel to be supplied to the gate line GL and the data line DL to drive a predetermined pattern on the electrophoretic panel. The pattern is observed at, to check whether the pixel is normally driven.

However, in the conventional general electrophoretic panel as described above, leakage current between pixels in which charges charged in the pixel electrodes leak to adjacent data lines DL is applied to the source electrode of the thin film transistor TR of the adjacent pixels. current) problem may occur, such that the first test signal (or the second test signal) and the third test signal are simultaneously converted to the reference voltage level or the first test signal (or The third test signal is converted to the reference voltage level before the second test signal, and the first test signal (or the second test signal) and the fourth test signal are simultaneously referenced to each other as in the period P6 and P7 of FIG. 2B. Since the fourth test signal is switched to the level or to the reference voltage level before the first test signal (or the second test signal), the leakage current between the pixels is generated as shown in FIG. 3. Even when the leakage current flows, the thin film transistor TR of the pixel has a negative first test signal (or second test signal) having the lowest level as shown in the P6 section of FIGS. 2A and 2B. Since it cannot be driven, it has been a problem that a pixel to which leakage current flows from adjacent pixels cannot be detected at the time of auto probe inspection.

Accordingly, an object of the present invention is to solve the above problems, and an object of the present invention is to detect a defective pixel in which a leakage current between pixels occurs in performing an auto probe inspection on an electrophoretic panel. It is to provide an auto probe inspection method with improved detection rate.

According to an exemplary embodiment of the present invention, an auto probe inspection method includes a plurality of pixels defined by crossing gate lines and data lines, and an even number of first test pads connected to odd-numbered gate lines. Preparing an electrophoretic panel having a second test pad connected to the first gate line, a third test pad connected to the odd-numbered data line, and a fourth test pad connected to the even-numbered data line; Inputting a first test signal to the first test pad and a third and fourth test signal to each of the third and fourth test pads; Inputting a second test signal to the second test pad and inputting a third and fourth test signal to each of the third and fourth test pads; And observing the defect by observing the electrophoretic panel in which the inspection pattern is implemented. The first and second test signals include a positive voltage section, a negative voltage section, and a reference voltage section, and the third and fourth test signals include a stabilization section and a data voltage section. Portions of the reference voltage sections of the first and second test signals overlap part of the data voltage sections of the third and fourth test signals.

In addition, in the auto probe inspection method according to another exemplary embodiment of the present invention for achieving the above object, a plurality of pixels are defined by crossing gate lines and data lines, thin film transistors are formed in each pixel, and an odd number Preparing an electrophoretic panel having a first test pad connected to the first gate line, a second test pad connected to the even-numbered gate line, a third test pad connected to the odd-numbered data line and a fourth test pad connected to the even-numbered data line are prepared. step; Inputting a first test signal to the first test pad and a third and fourth test signal to each of the third and fourth test pads; Inputting a second test signal to the second test pad and inputting a third and fourth test signal to each of the third and fourth test pads; And observing the defect by observing the electrophoretic panel in which the inspection pattern is implemented. The first and second test signals include a positive voltage section, a negative voltage section, a leakage current test section, and a reference voltage section, and the third and fourth test signals include a stabilization section and a data voltage section. The leakage current test section has a level capable of driving a thin film transistor of a pixel in which leakage current from an adjacent pixel flows and overlaps a portion of the data voltage sections of the third and fourth test signals.

In the auto probe inspection method according to the preferred embodiment of the present invention as described above, when performing the auto probe inspection on the electrophoretic panel, a part of the reference voltage section of the first and second inspection signals is the third and fourth inspection signals. Since it overlaps with a part of the data voltage section, it is possible to detect the defective pixel in which the leakage current between the pixels is generated, thereby improving the defect detection rate.

In the auto probe inspection method according to another exemplary embodiment of the present invention, the leakage current inspection section next to the negative voltage section in the first and second inspection signals may drive the thin film transistor of the pixel in which the leakage current occurs. Since it is possible to detect the defective pixels in which the leakage current between the pixels is generated, the defective detection rate can be improved.

Hereinafter, an auto probe inspection apparatus and an auto probe inspection method according to a preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings.

In the auto probe test method according to an exemplary embodiment of the present invention, a plurality of pixels are defined by crossing gate lines GL_odd and GL_even and data lines DL_odd and DL_even, and are connected to odd-numbered gate lines GL_odd. A second test pad PAD2 connected to the test pad PAD1 and the even-numbered gate line GL_even, and a third test pad PAD3 connected to the odd-numbered data line DL_odd, and a third data pad DL_even connected to the even-numbered data line DL_even. Preparing an electrophoretic panel on which the test pad PAD4 is formed; Inputting a first test signal to the first test pad PAD1 and inputting third and fourth test signals S3 and S4 to each of the third and fourth test pads PAD3 and PAD4; Inputting a second test signal S2 to the second test pad PAD2 and inputting third and fourth test signals S3 and S4 to each of the third and fourth test pads PAD3 and PAD4; And observing the defect by observing the electrophoretic panel in which the inspection pattern is implemented. And the first and second test signals S1 and S2 include a positive voltage section, a negative voltage section, and a reference voltage section, and the third and fourth test signals S3 and S4 include And a stabilization period and a data voltage period, wherein a part of the reference voltage sections of the first and second test signals S1 and S2 overlap with a part of the data voltage sections of the third and fourth test signals S3 and S4. .

Before describing each step of the auto probe inspection method according to a preferred embodiment of the present invention comprising a plurality of steps as described above, with reference to Figures 4 and 5 the auto probe according to a preferred embodiment of the present invention Referring to the structure of the electrophoretic panel of the test object of the inspection apparatus as follows.

For reference, FIG. 4 is a circuit diagram of the electrophoretic panel, and FIG. 5 is a cross-sectional view of the electrophoretic panel of FIG. 4.

As shown in FIG. 4 and FIG. 5, the electrophoretic panel, which is the test object of the auto probe inspection apparatus according to the preferred embodiment of the present invention, includes a plurality of gate lines GL_odd and GL_even intersecting with data lines DL_odd and DL_even. Is composed of a first substrate 101 defined by a pixel and a second substrate 102 disposed to face the first substrate 101, and between the first substrate 101 and the second substrate 102. An electrophoretic film 103 is formed thereon.

The electrophoretic film 103 has an electron ink forming a capsule 103a in a polymer binder, and the electron ink distributed in the capsule 103a is formed of a white ink 103a1 and a black ink 103a2. The white ink 103a1 and the black ink 103a2 are charged with different polarities. That is, the white ink 103a1 is charged with positive charge and the black ink 103a2 is charged with negative charge, or the white ink 103a1 is charged with negative charge and the black ink 103a2 is charged. Is charged with a positive charge.

The first substrate 101 is formed such that a plurality of gate lines GL_odd and GL_even intersect with a plurality of data lines DL_odd and DL_even to define a plurality of pixels, and each pixel includes gate lines GL_odd and GL_even. The thin film transistors TR1 to TR4 are formed in an area where the data lines DL_odd and DL_even cross each other, and pixel electrodes 104 connected to the thin film transistors TR1 to TR4 are formed in each pixel. In addition, a common electrode 105 to which a reference voltage, that is, a common voltage is supplied, is formed on the second substrate 102, and the common voltage supplied to the common electrode 105 is a data voltage supplied to the pixel electrode 104. Drive the electrophoretic membrane.

The electrophoretic panel includes a gate driver for driving gate lines GL_odd and GL_even and a data driver for driving data lines DL_odd and DL_even, wherein the gate driver and the data driver are integrated circuits (ICs). The gate driver or the data driver manufactured by the integrated circuit method is mounted on the first substrate 101 after the auto probe inspection is performed during the electrophoretic panel manufacturing process.

In the electrophoretic panel having the configuration as described above, the first to fourth test pads PAD1 to PAD4 are formed for the purpose of use in the auto probe test. In this case, the first to fourth test pads PAD1 to PAD4 are used only when performing the auto probe test, and after the manufacturing of the electrophoretic panel is completed, the gate lines GL_odd and GL_even are connected to the gate driver so that the first and fourth test pads PAD1 to PAD4 are used. 2 The connection to the test pads PAD1 and PAD2 is disconnected and the data lines DL_odd and DL_even are connected to the data driver, thereby disconnecting the third and fourth test pads PAD3 and PAD4. That is, the first and second test pads PAD1 and PAD2 and the third and fourth test pads PAD3 and PAD4 are used only when performing an auto probe test in the manufacturing process of the electrophoretic panel. It is not used after the manufacture of is completed.

An auto probe inspection method according to a preferred embodiment of the present invention for inspecting an electrophoretic panel having the configuration as described above will be described in detail with reference to FIGS. 4 to 8.

First, as illustrated in FIG. 4, a plurality of pixels are defined by crossing gate lines GL1_odd and GL_even and data lines DL_odd and DL_even, and the plurality of pixels form a plurality of horizontal pixel columns. Prepare an electrophoretic panel, i.e. In this case, the first test pad PAD1 connected to the odd-numbered gate line GL_odd and the second test pad PAD2 connected to the even-numbered gate line GL_even and the odd-numbered number are formed on the first substrate 101 of the electrophoretic panel. The third test pad PAD3 connected to the data line DL_odd and the fourth test pad PAD4 connected to the even-numbered data line LD_even are formed.

Next, the first test signal is input to the first test pad PAD1 of the electrophoretic panel by using an auto probe device so that the entire odd-numbered gate line GL_odd is simultaneously driven, and the first test signal is input. The pixels corresponding to the odd-numbered gate lines GL_odd are driven by inputting the third and fourth test signals to the third and fourth test pads PAD3 and PAD4, respectively, in accordance with the timing.

In this case, the first test signal includes a positive voltage section, a negative voltage section, and a reference voltage section, and a part of the reference voltage section of the first test signal corresponds to a part of the data voltage section of the third and fourth test signals. Overlapping, in detail with reference to FIGS. 6A to 8B as follows.

6A and 6B show waveform diagrams of the first test signal and the third and fourth test signals. In detail, FIG. 6A illustrates an arbitrary odd number of pixels in a plurality of horizontal pixel columns formed on the first substrate 101. The first and third test signals S1 and S3 applied to the first first pixel pixel 1 are shown. The first waveform is the first test signal S1 and the second waveform is the third test signal S3. 6B illustrates first and fourth inspections applied to a second pixel 2 positioned to the right of the first pixel among pixels in a plurality of horizontal pixel columns formed on the first substrate 101. Signals S1 and S4 are shown, where the first waveform is the first test signal S1 and the second waveform is the fourth test signal S4.

Referring to FIG. 6A, the first test signal S1 includes a reference voltage section T1, a positive polarity section T2, a negative polarity section T3, and a reference voltage section T4, and includes a third test signal. S3 includes a reference voltage section T5, a stabilization section T6, a data voltage section T7, and a reference voltage section T8. In this case, in the third test signal S3, a negative data voltage is generated in the data voltage section T7.

Referring to FIG. 6A, in the P1 and P8 sections, both the first test signal S1 and the third test signal S3 are at the same level as the reference voltage, that is, the level of the common voltage Vcom applied to the common electrode. The first pixel pixel 1 is in the state before inspection by being generated as. In the P2 section, since the first inspection signal S1 is generated at the positive polarity level and the third inspection signal S3 is also generated at the positive polarity level, the first pixel pixel 1 displays a black image. . In the P3 section, since the third test signal S3 is generated at the same level as that of the reference voltage, there is no change in the display image of the first pixel pixel 1. In the P4 section, since the third test signal S3 is generated at the negative level, the first pixel pixel 1 displays a white image. In the P5 section, since the third test signal S3 is a negative data voltage, the first pixel pixel 1 displays a white image corresponding to the negative data voltage. In the P6 section, since the first test signal S1 is switched to the negative level, the first pixel pixel 1 has no change in the display image. In the P7 section, since the first inspection signal S1 is switched to the same level as the reference voltage level, and the third inspection signal S3 is the same negative data voltage as in the P5 and P6 sections, the pixel electrode 104 of the adjacent pixel. ) Is a leakage current that leaks through the data line DL_odd corresponding to the first pixel pixel 1, flows into the first pixel pixel 1, and is transferred to the thin film transistor TR1. In this case, the thin film transistor TR1 is operated so that the first pixel pixel 1 displays a darker image than the P5 and P6 sections.

Referring to FIG. 6B, as mentioned above, the first test signal S1 includes a reference voltage section T1, a positive polarity section T2, and a reference voltage section T4, and includes a fourth test signal S4. ) Includes a reference voltage section T5, a stabilization section T6, a data voltage section T7, and a reference voltage section T8. At this time, a positive data voltage is generated in the data voltage section T7 in the fourth test signal S4.

Referring to FIG. 6B, in the P1 and P8 sections, both the first test signal S1 and the fourth test signal S4 are at the same level as the reference voltage, that is, the level of the common voltage Vcom applied to the common electrode. By being generated as, the second pixel 2 is in a state before inspection. In the P2 section, since the first test signal S1 is generated at the positive polarity level and the fourth test signal S4 is also generated at the positive polarity level, the second pixel pixel 2 displays a black image. In the P3 section, since the fourth test signal S4 is generated at the same level as the reference voltage level, there is no change in the display image of the second pixel 2. In the P4 section, since the fourth test signal S4 is generated at the negative level, the second pixel pixel 2 displays a white image. In the P5 section, since the fourth test signal S4 is a positive data voltage, the second pixel pixel 2 displays a black image corresponding to the positive data voltage. In the P6 section, the first test signal S1 is negative. Since the level is switched to the level, the second pixel 2 does not change the display image. In the P7 section, since the first test signal S1 is switched to the same level as the reference voltage level, and the fourth test signal S4 is the same positive data voltage as in the P5 and P6 sections, the pixels of the adjacent pixels as shown in FIG. 7. The charge current charged in the electrode 104 leaks through the data line DL_even corresponding to the second pixel pixel 2, flows into the second pixel pixel 2, and is transmitted to the thin film transistor TR2. In this case, the thin film transistor TR2 is operated so that the second pixel pixel 2 displays a brighter image than the P5 and P6 sections.

Next, the second test signal is input to the second test pad PAD2 of the electrophoretic panel using an auto probe device to simultaneously drive the entire even-numbered gate line GL_even, and the input of the second test signal may occur. The pixels corresponding to the even-numbered gate lines GL_even are driven by inputting third and fourth test signals to the third and fourth test pads PAD3 and PAD4, respectively, in accordance with the timing.

In this case, the second test signal includes a positive voltage section, a negative voltage section, and a reference voltage section, and a part of the reference voltage section of the second test signal corresponds to a part of the data voltage section of the third and fourth test signals. Overlapping, it will be described in detail with reference to Figures 6a to 8 as follows.

8A and 8B illustrate waveform diagrams of the second test signal and the third and fourth test signals. In detail, FIG. 8A illustrates a first pixel among pixels in a plurality of horizontal pixel columns formed on the first substrate 101. The second and third test signals S2 and S3 applied to the third pixel pixel 3 positioned below the pixel 1 are shown. The first waveform is the second test signal S2 and the second waveform is 8B is a third inspection signal S3 and FIG. 8B illustrates a fourth pixel 4 positioned to the right of the third pixel 3 among pixels in a plurality of horizontal pixel columns formed on the first substrate 101. The second and fourth test signals S2 and S4 applied to the first waveform are the second test signal S2 and the second waveform is the fourth test signal S4.

Referring to FIG. 8A, as mentioned above, the second test signal S2 includes a reference voltage section T1, a positive polarity section T2, and a reference voltage section T4, and includes a third test signal S3. ) Includes a reference voltage section T5, a stabilization section T6, a data voltage section T7, and a reference voltage section T8. Here, the positive data voltage is generated in the data voltage section T7 in the third test signal S3. At this time, the data voltage section (T7 of FIG. 8A) of the third test signal S3 supplied to the third test pad PAD3 in synchronization with the second test signal S2 is synchronized with the first test signal S1. The polarity of the data voltage (T7 in FIG. 6A) of the third test signal S3 supplied to the third test pad PAD3 is inverted, but the present invention is not limited thereto. The data voltage section (T7 of FIG. 8A) of the third test signal S3 supplied to the third test pad PAD3 in synchronization with the second test signal S2 is synchronized with the first test signal S1. The polarity of the data voltage (T7 of FIG. 6A) of the third test signal S3 supplied to the third test pad PAD3 may be the same.

Referring to FIG. 8A, in the P1 and P8 sections, both the second test signal S2 and the third test signal S3 are at the same level as the reference voltage, that is, the level of the common voltage Vcom applied to the common electrode. The third pixel pixel 3 forms a state before inspection by being generated as. In the P2 section, since the second test signal S2 is generated at the positive polarity level (+) and the third test signal S3 is generated at the positive polarity level, the third pixel pixel 3 displays a black image. In the P3 section, since the third test signal S3 is generated at the same level as that of the reference voltage, there is no change in the display image of the third pixel 3. In the P4 section, since the third test signal S3 is generated at a negative level, the second pixel 2 displays a white image. In the P5 section, since the third test signal S3 is a positive data voltage, the third pixel pixel 3 displays a black image corresponding to the positive data voltage. In the P6 section, the second test signal S2 is negative. As the level is switched, the third pixel 3 does not change the display image. In the P7 section, since the second test signal S2 is switched to the same level as the reference voltage level, and the third test signal S3 is the same positive data voltage as in the P5 and P6 sections, the pixels of the adjacent pixels as shown in FIG. 7. When a charge current charged in the electrode 104 flows into the third pixel pixel 3 through the data line DL_odd corresponding to the third pixel pixel 3 and is transmitted to the thin film transistor TR3. The thin film transistor TR3 is operated to display a third image pixel 3 that is brighter than the P5 and P6 sections.

Referring to FIG. 8B, the second test signal S2 includes a reference voltage section T1, a positive polarity section T2, a negative polarity section T3, and a reference voltage section T4, and includes a fourth test signal. S4 includes a reference voltage section T5, a stabilization section T6, a data voltage section T7, and a reference voltage section T8. In the fourth test signal, a negative data voltage is generated in the data voltage section T7. At this time, the data voltage section (T7 of FIG. 8A) of the fourth test signal S4 supplied to the fourth test pad PAD4 in synchronization with the second test signal S2 is synchronized with the first test signal S1. The polarity of the data voltage (T7 in FIG. 6A) of the fourth test signal S4 supplied to the fourth test pad PAD4 is inverted, but the present invention is not limited thereto. The data voltage section (T7 of FIG. 8A) of the fourth test signal S4 supplied to the fourth test pad PAD4 in synchronization with the second test signal S2 is synchronized with the first test signal S1. The polarity of the data voltage (T7 of FIG. 6A) of the fourth test signal S4 supplied to the fourth test pad PAD4 may be the same.

Referring to FIG. 8B, in the P1 and P8 sections, both the second test signal S2 and the fourth test signal S4 are at the same level as the reference voltage, that is, the level of the common voltage Vcom applied to the common electrode. The fourth pixel (pixel 4) forms a state before inspection by being generated as. In the P2 section, since the second test signal S2 is generated at the positive polarity level and the fourth test signal S4 is also generated at the positive polarity level, the fourth pixel 4 displays a black image. In the P3 section, since the fourth test signal S4 is generated at the same level as the reference voltage level, there is no change in the display image of the fourth pixel 4. In the P4 section, since the fourth test signal S4 is generated at the negative level, the fourth pixel 4 displays a white image. In the P5 section, since the fourth test signal S4 is a negative data voltage, the fourth pixel 4 displays a white image corresponding to the negative data voltage. In the P6 section, since the second test signal is switched to the negative level, the fourth pixel 4 does not change the display image. In the P7 section, since the second test signal S2 is switched to the same level as the reference voltage level, and the fourth test signal S4 is the same negative data voltage as in the P5 and P6 sections, the pixel electrode of the adjacent pixel ( When the charge charged in the 104 flows into the fourth pixel (pixel 4) through the data line DL_even corresponding to the fourth pixel (pixel 4) and is transmitted to the thin film transistor TR4, the thin film is formed. The transistor TR4 is operated so that the fourth pixel 4 displays a darker image than in the P5 and P6 sections.

Next, the electrophoretic panel in which the test pattern is implemented is observed to detect pixels that are not normally driven due to disconnection or device failure, and to detect pixels that are not normally driven due to leakage current. As a method of observing the color pattern implemented on the electrophoretic panel, various methods such as a method of directly observing a worker through a microscope may be possible.

In the above description of the auto probe test method according to the preferred embodiment of the present invention, a part of the reference voltage section in the first and second test signals overlaps with a part of the data voltage sections of the third and fourth test signals. Although the present invention is not limited thereto, a part of the region overlapping with the data voltage intervals of the third and fourth test signals in the first and second test signals is determined by the pixel in which the leakage current flows from an adjacent pixel. An example in which the leakage current test interval is formed by having a level different from the reference voltage level within the range in which the thin film transistor can be driven may be possible.

1 is a circuit diagram of a conventional general electrophoretic panel.

2A and 2B are waveform diagrams of test signals applied to two adjacent pixels when performing an auto probe test on the electrophoretic panel of FIG. 1;

3 is a circuit diagram illustrating a case where a leakage current between pixels occurs in the general electrophoretic panel of FIG. 1.

4 is a circuit diagram of an electrophoretic panel that is a test object of the auto probe test method according to a preferred embodiment of the present invention.

5 is a cross-sectional view showing a cross section of the electrophoretic panel of FIG.

6A and 6B are waveform diagrams of test signals applied to first and second pixels adjacent to each other when performing an auto probe test with respect to the electrophoretic panel of FIG. 4, and FIG. Fig. 6B is a waveform diagram of the first test signal and the third test signal, and Fig. 6B is a waveform diagram of the first test signal and the fourth test signal applied to the second pixel.

FIG. 7 is a circuit diagram illustrating a case where a leakage current flows from a first pixel to a second pixel in the electrophoretic panel of FIG. 4. FIG.

8A and 8B are waveform diagrams of test signals applied to third and fourth pixels adjacent to each other when performing an auto probe test with respect to the electrophoretic panel of FIG. 4, and FIG. 8A is applied to the third pixel. Fig. 8B is a waveform diagram of the second test signal and the third test signal, and Fig. 8B is a waveform diagram of the second test signal and the fourth test signal applied to the fourth pixel.

** Description of the symbols for the main parts of the drawings **

101: first substrate 102: second substrate

103: electrophoretic membrane 103a: capsule

103a1: Black Ink 103a2: White Ink

104: pixel electrode 105: common electrode

GL_odd, GL_even: Gate Line DL_odd, DL_even: Data Line

TR1 to TR4: first thin film transistor to fourth thin film transistor

PAD1 to PAD4: 1st test pad-4th test pad

S1 to S4: 1st test signal-4th test signal

Claims

A plurality of pixels are defined by crossing the gate line and the data line, and a first test pad connected to an odd gate line and a second test pad connected to an even gate line and a third test pad connected to an odd data line and an even number line Preparing an electrophoretic panel having a fourth test pad connected to a data line;

Inputting a first test signal to the first test pad and a third and fourth test signal to each of the third and fourth test pads;

Inputting a second test signal to the second test pad and inputting a third and fourth test signal to each of the third and fourth test pads; And

Observing the defect by observing the electrophoretic panel in which the test pattern is implemented;

And,

The first and second test signals include a positive voltage section, a negative voltage section, and a reference voltage section, and the third and fourth test signals include a stabilization section and a data voltage section, and the first and second test signals. And a part of the reference voltage section of the signal overlaps a part of the data voltage sections of the third and fourth test signals.

The method of claim 1, wherein the data voltage section of the third test signal and the data voltage section of the fourth test signal have opposite polarities.

The method of claim 1, wherein the reference voltage section occurring after the negative voltage section in the first and second test signals includes a first section and a second section, and a data voltage in the third and fourth test signals. The intervals include the third to fifth intervals in sequence,

And the first section overlaps the fifth section.

4. The method of claim 3, wherein the positive voltage section of the first and second test signals overlaps the entire stabilization section of the third and fourth test signals and the third section of the data voltage section. .

4. The method of claim 3, wherein the negative voltage sections of the first and second test signals overlap with the fourth sections of the data voltage sections of the third and fourth test signals.

The gate line and the data line cross each other to define a plurality of pixels, and a thin film transistor is formed in each pixel, and the first test pad connected to the odd-numbered gate line and the second test pad and odd-numbered data line connected to the even-numbered gate line. Preparing an electrophoretic panel on which a third test pad connected to a fourth test pad connected to an even-numbered data line is formed;

And,

The first and second test signals include a positive voltage section, a negative voltage section, a leakage current test section, and a reference voltage section, and the third and fourth test signals include a stabilization section and a data voltage section. The leakage current test section has a level capable of driving a thin film transistor of a pixel into which leakage current from an adjacent pixel flows and overlaps a part of the data voltage sections of the third and fourth test signals. .

7. The method of claim 6, wherein the data voltage section of the third test signal and the data voltage section of the fourth test signal have opposite polarities.

The method of claim 6, wherein the data voltage section of the third and fourth check signals includes third to fifth sections in order.

And a leakage current test section of the first and second test signals and a fifth section of the third and fourth test signals overlap each other.

10. The method of claim 8, wherein the positive voltage section of the first and second test signals overlaps the entire stabilization period of the third and fourth test signals and the third section of the data voltage section. .

The method of claim 8, wherein the negative voltage section of the first and second test signals overlaps the fourth section of the data voltage sections of the third and fourth test signals.