JP4853705B2 - TFT array inspection method and TFT array inspection apparatus - Google Patents

Description

  The present invention relates to a TFT array inspection process performed in a manufacturing process of a liquid crystal substrate or the like, and more particularly to driving of a TFT array when performing a TFT array inspection.

  In the manufacturing process of a semiconductor substrate on which a TFT array such as a liquid crystal substrate or an organic EL substrate is formed, a TFT array inspection process is included in the manufacturing process, and a defect inspection of the TFT array is performed in this TFT array inspection process.

  The TFT array is used as a switching element for selecting a pixel electrode of a liquid crystal display device, for example. In a substrate including a TFT array, for example, a plurality of gate lines functioning as scanning lines are arranged in parallel, and a plurality of source lines described as signal lines are arranged orthogonal to the gate lines. A TFT (Thin Film Transistor) is disposed in the vicinity of a portion where the lines intersect, and a pixel electrode is connected to the TFT.

  The liquid crystal display device is configured by sandwiching a liquid crystal layer between a substrate provided with the TFT array described above and a counter substrate, and a pixel capacitor is formed between the counter electrode and the pixel electrode provided in the counter substrate. In addition to the pixel capacitor, an additional capacitor (Cs) is connected to the pixel electrode. One of the additional capacitors (Cs) is connected to the pixel electrode, and the other is connected to the common line or the gate line. A TFT array configured to be connected to the common line is referred to as a Cs on Com type TFT array, and a TFT array configured to be connected to the gate line is referred to as a Cs on Gate type TFT array.

  In this TFT array, a scanning line (gate line) or a signal line (source line) is disconnected, a scanning line (gate line) and a signal line (source line) are short-circuited, or a pixel defect due to a characteristic defect of a TFT driving a pixel. In the defect inspection, for example, the counter electrode is grounded, a DC voltage of, for example, −15 V to +15 V is applied to all or part of the gate line at a predetermined interval, and an inspection signal is applied to all or part of the source line. By doing that. (For example, the prior art of patent document 1.)

  The TFT array inspection apparatus can detect a defect by inputting a driving signal for inspection to the TFT array and detecting the voltage state at that time. Further, the defect detection of the TFT array may be performed by observing the display state of the liquid crystal. When inspecting the TFT array by observing the display state of the liquid crystal, in addition to the inspection in the state of the liquid crystal display device in which the liquid crystal layer is sandwiched between the TFT array substrate and the counter electrode, the liquid crystal layer and the counter electrode are By attaching the provided inspection jig to the TFT array substrate, it is possible to inspect in the state of a semi-finished product that does not reach the liquid crystal display device.

  FIG. 8 shows an example of a pattern of an inspection signal applied to the TFT array when the TFT array is inspected. In the conventional inspection signal pattern, the time ratio between the + voltage holding time for holding the positive voltage of the source line and the -voltage holding time for holding the negative voltage is set to 1: 1 within one gate period. Switching between the + voltage holding time and the −voltage holding time is performed by applying an on-pulse to the line gate. The ON pulse is applied at equal time intervals within one gate period so that the time ratio between the + voltage holding time and the −voltage holding time is 1: 1.

FIGS. 8A and 8B show ON pulses applied to the gate lines. Here, an example is shown in which the gate lines are divided into an even number and an odd number, and FIG. 8A shows an even line. FIG. 8B shows the state of application to odd lines. This one gate period (indicated by numbers 1 to 10 in the figure) is, for example, 16 msec (or 32 msec), and the time width of the + voltage holding time and the −voltage holding time is 8 msec (or 16 msec, respectively). ).
JP-A-5-307192

  It is known that some of the electrical defects included in the TFT array depend on the holding time of the voltage applied to the source line. A defect whose appearance depends on the holding time exhibits almost the same phenomenon as a normal pixel when the holding time is short, and the defect cannot be detected. In order to detect such a defect, it is necessary to lengthen the holding time. In order to increase the holding time, it is necessary to increase the time width of one gate period.

  However, the TFT array inspection process performed by the TFT array inspection apparatus is performed by an in-line process in a series of manufacturing processes, and each of these processes has a predetermined tact time, which affects the tact time of the apparatus. Such a long holding time cannot be set.

  Therefore, the conventional inspection signal pattern has a problem in that defects appearing depending on the holding time cannot be detected.

  SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to solve the above-described problems and detect defects that appear depending on holding time in TFT array inspection.

  The present invention relates to a TFT substrate inspection method and a TFT substrate inspection apparatus for inspecting defects of a TFT array by applying a voltage to the TFT array of the TFT substrate. The pixel electrode is connected to a positive potential within one gate period. By keeping the time ratio between the first period held in the second period and the second period in which the pixel electrode is held at a negative potential unequal, a predetermined voltage is held in the pixel electrode within a limited period of one gate period. The time taken is increased, thereby allowing inspection of defects that appear due to longer holding times.

  In the TFT substrate inspection method of the present invention, the time period of the on-pulse signal of the TFT gate applied to the gate line is made unequal within one gate period, so that the first period and the first period within one gate period are the same. The time ratio of period 2 is unequal.

  Within one gate period, it can be arbitrarily determined which of the first period and the second period is longer, and which of the first period and the second period is the first period. Can also be arbitrarily determined.

  When the TFT array is a Cs on Com type TFT array in which an additional capacitor (Cs) is connected to a common line, a plurality of gate lines provided in the TFT substrate are divided into two gate line groups by a predetermined gate line. A pulse signal for turning on the gate is applied to each of the gate line groups in synchronization with an unequal time period.

  For example, a plurality of gate lines provided in a TFT substrate are divided into two groups: a gate line group composed of even-numbered gate lines and a gate line group composed of odd-numbered gate lines. In each gate line group, the gates of the TFT array are divided. Pulse signals to be turned on are applied at unequal time periods, and are applied in synchronization between the two gate line groups.

  Further, when the TFT array is a Cs on Gate type TFT array in which the additional capacitor (Cs) is connected to the gate line, a plurality of gate lines provided in the TFT substrate are divided into two gate line groups by a predetermined gate line, A pulse signal for turning on the gate of the TFT is applied to each of the gate line groups asynchronously with the unequal time period.

  For example, a plurality of gate lines provided in a TFT substrate are divided into two groups: a gate line group composed of even-numbered gate lines and a gate line group composed of odd-numbered gate lines. In each gate line group, the gates of the TFT array are divided. Pulse signals to be turned on are applied with unequal time periods, and are applied asynchronously between the two gate line groups. Here, the non-period means that the on-pulse signal is not applied to the gate lines at the same time between the two gate line groups, and the application time is shifted.

  At this time, the application order of the pulse signal is, for example, by first applying the pulse signal to the even-numbered gate line to set the pixel electrode connected to the even-numbered gate line to the positive potential, and then to the odd-numbered gate line. A pulse signal is applied to the gate line so that the pixel electrode connected to the odd-numbered gate line has a positive potential. After the first period has elapsed, a pulse signal is applied to the odd-numbered gate lines to change the pixel electrodes connected to the odd-numbered gate lines to a negative potential, and then to the even-numbered gate lines. A pulse signal is applied to set the pixel electrode connected to the even-numbered gate line to a negative potential. Thereafter, when the second period elapses, one gate cycle is completed, and a pulse signal is applied in the same manner in the next one gate cycle.

  The TFT substrate inspection apparatus of the present invention is a TFT substrate inspection apparatus that inspects defects in the TFT array by applying a voltage to the TFT array of the TFT substrate and detecting a voltage state due to the voltage application. An electron beam source that irradiates the TFT substrate with an electron beam, a detector that detects secondary electrons emitted from the TFT substrate, an inspection signal generation unit that generates and applies an inspection signal to the TFT array of the TFT substrate, And a defect detection unit that detects defects in the TFT array based on a detection signal of the detector. Here, the inspection signal generation unit generates an on-pulse signal with an uneven time period within one gate period of the TFT array, applies it to the gate line, and performs on-control of the gate of the TFT.

  Within the gate period, by making the time ratio of the holding times with different voltage states non-uniform, one holding time becomes longer than in the case of an equal time ratio, and the detection of defects that develop with a long holding time can be detected. It becomes possible.

  According to the present invention, defects that appear depending on the holding time can be detected in the TFT array inspection.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a schematic view of a TFT array inspection apparatus of the present invention.

  The TFT array inspection apparatus 1 includes an inspection signal generation unit 4 that generates an inspection signal for array inspection on the TFT substrate 10, a prober 8 that applies the inspection signal generated by the inspection signal generation unit 4 to the TFT substrate 10, and a TFT substrate. A mechanism (2, 3, 5) for detecting the voltage application state of the TFT and a defect detector 6 for detecting a defect of the TFT array based on the detection signal.

  The prober 8 includes a prober frame provided with probe pins. The prober 8 is placed on the TFT substrate 10 to bring the probe pins into contact with electrodes formed on the TFT substrate 10 and applies an inspection signal to the TFT array.

  The mechanism for detecting the voltage application state of the TFT substrate can have various configurations. The configuration shown in FIG. 1 is a detection configuration using an electron beam. An electron beam source 2 that irradiates an electron beam on the TFT substrate 10 and a secondary electron that detects secondary electrons emitted from the TFT substrate 10 by the irradiated electron beam. The secondary electron detector 3 and the secondary electron detector 3 are provided with a signal processing unit 5 that performs signal processing on detection signals from the secondary electron detector 3 and detects a potential state on the TFT substrate 10.

  Since the TFT array irradiated with the electron beam emits secondary electrons corresponding to the voltage of the applied inspection signal, the potential state of the TFT array can be detected by detecting the secondary electrons.

  The defect detection unit 6 detects defects in the TFT array by comparing with the potential state in the normal state based on the potential state of the TFT array acquired by the signal processing unit 5.

  Here, a configuration example is shown in which a TFT array defect is detected using a mechanism (2, 3, 5) that detects the voltage application state of the TFT substrate. However, the TFT substrate constitutes a liquid crystal display device. If there is a display, a liquid crystal is driven by the inspection signal to display a display pattern based on the inspection signal, and this display state is imaged by the image pickup device and image processing is performed on the acquired image to perform defect inspection. The image may be observed visually. In the case where the TFT substrate is provided with only the TFT array, a liquid crystal display device is temporarily formed by providing a liquid crystal layer and a counter electrode on a jig for applying an inspection signal, and a defect is generated as described above. An inspection may be performed.

  The inspection signal generation unit 4 generates a signal pattern of an inspection signal that drives the TFT array formed on the TFT substrate 10. This signal pattern will be described later.

  The scanning control unit 9 controls the stage 7 and the electron source 2 in order to scan the inspection position of the TFT array on the TFT substrate 10. The stage 7 moves the TFT substrate 10 to be placed in the XY direction, and the electron source 2 scans the irradiation position of the electron beam by shaking the electron beam irradiating the TFT substrate 10 in the XY direction. The scanning position becomes the detection position.

  The above-described configuration of the TFT array inspection apparatus is an example, and is not limited to this configuration.

  Next, the inspection signal used for the inspection of the TFT substrate of the present invention will be described with reference to FIGS. 2 to 4 for the Cs on Com type TFT array, and FIGS. 5 to 7 for the case of the Cs on Gate type TFT array. Will be described.

  Here, the Cs on Com type TFT array has a configuration in which one connection end of the additional capacitor (Cs) connected to the pixel electrode is connected to a common line (Cs line). One connection end of the additional capacitor (Cs) connected to the pixel electrode is connected to the gate line (Gate line).

  First, the case of a Cs on Com type TFT array will be described.

  FIG. 2 schematically shows the configuration of a Cs on Com TFT array. On the TFT substrate, a TFT is provided in a TFT area 11A in the vicinity of a portion where the gate line 14 and the source line 15 intersect. Further, a Cs line 16 for connecting an additional capacitor (Cs) is provided between adjacent gate lines 14.

  FIG. 3 shows an equivalent circuit of the Cs on Com type TFT array shown in FIG. In the equivalent circuit of FIG. 3, the gate line 14 and the source line 15 are illustrated as being driven by being divided into even-numbered and odd-numbered two line groups, respectively.

  A pixel 12oo is provided in the vicinity of a portion where the odd-numbered gate line 14o and the odd-numbered source line 15o intersect. One end of the pixel (Pixel) 12oo is connected to the TFT 11oo, and the other end is connected to the additional capacitor (Cs) 13oo. The other end of the additional capacitor (Cs) 13oo is connected to the Cs line 16. The drain D of the TFT 11oo is connected to the pixel 12oo, the gate G is connected to the odd-numbered gate line 14o, and the source S is connected to the odd-numbered source line 15o.

  Similarly, a pixel 12oe is provided in the vicinity of a portion where the odd-numbered gate line 14o and the even-numbered source line 15e intersect. One end of the pixel (Pixel) 12oe is connected to the TFT 11oe, and the other end is connected to the additional capacitor (Cs) 13oe. The other end of the additional capacitor (Cs) 13oe is connected to the Cs line 16. The drain D of the TFT 11oe is connected to the pixel 12oe, the gate G is connected to the odd-numbered gate line 14o, and the source S is connected to the even-numbered source line 15e.

  Further, a pixel 12eo is provided in the vicinity of a portion where the even-numbered gate line 14e and the odd-numbered source line 15o intersect. One end of the pixel (Pixel) 12eo is connected to the TFT 11eo, and the other end is connected to an additional capacitor (Cs) 13eo. The other end of the additional capacitor (Cs) 13eo is connected to the Cs line 16. The drain D of the TFT 11eo is connected to the pixel 12eo, the gate G is connected to the even-numbered gate line 14e, and the source S is connected to the odd-numbered source line 15o.

  Further, a pixel 12ee is provided in the vicinity of a portion where the even-numbered gate line 14e and the even-numbered source line 15e intersect. One end of the pixel 12ee is connected to the TFT 11ee, and the other end is connected to the additional capacitor (Cs) 13ee. The other end of the additional capacitor (Cs) 13ee is connected to the Cs line 16. The drain D of the TFT 11ee is connected to the pixel 12ee, the gate G is connected to the even-numbered gate line 14e, and the source S is connected to the even-numbered source line 15e.

  Accordingly, the voltage of the odd-numbered source line 15o is applied to the pixel (Pixel) 12oo according to the on-pulse signal of the odd-numbered gate line 14o, and the on-pulse of the odd-numbered gate line 14o is applied to the pixel (Pixel) 12oe. The voltage of the even-numbered source line 15e is applied according to the signal, and the voltage of the odd-numbered source line 15o is applied to the pixel (Pixel) 12eo according to the on-pulse signal of the even-numbered gate line 14e. Pixel) 12ee is applied with the voltage of the even-numbered source line 15e in accordance with the on-pulse signal of the even-numbered gate line 14e.

  FIG. 4 shows a signal pattern of an inspection signal within one gate period by the Cs on Com type TFT array of the present invention. In this signal pattern, for example, pixels 12 (12oo, 12oe, 13eo, 12ee) are output by outputting on-pulse signals of the gate lines 14 (14o, 14e) at unequal time intervals within one gate period. The positive voltage holding time for holding the positive voltage is set to be long. Holding at a negative voltage-The voltage holding time is shortened because one gate period has a constant time width.

  The uneven time ratio of the holding time can be, for example, 3: 1. According to this time ratio, the holding time can be increased by 1.5 times compared to the conventional uniform time ratio. it can. For example, when the gate period is 16 msec, the conventional holding time of 8 msec can be set to 12 msec. In TFT array inspection, defects that depend on the retention time appear empirically at a retention time of about 10 msec or more. Therefore, a defect that depends on the retention time is detected by setting the retention time ratio to 3: 1. Can do. The time ratio of the holding time is an example, and other time ratios may be used.

  In FIG. 4, for convenience of explanation, one gate period is indicated by 10 time intervals of 1 to 10, and an example in which an on-pulse signal is output in a period indicated by 1 and a period indicated by 8 in this one gate period is shown. Therefore, the time ratio of the holding time is set to 3: 1. In FIG. 4, the voltage of the source line 15 (15o, 15e) is set to +10 V when the voltage of the gate line 14 is applied when setting the + voltage holding time, and the voltage of the gate line 14 when setting the -voltage holding time. At the time of voltage application, it is -10V. The Cs line 16 is set to 0V.

  In this inspection signal pattern, all the pixels on the TFT substrate are simultaneously set to the same voltage.

  Next, the case of a Cs on Gate type TFT array will be described.

  FIG. 5 schematically shows the configuration of a Cs on Gate type TFT array. On the TFT substrate, a TFT is provided in a TFT area 11A in the vicinity of a portion where the gate line 14 and the source line 15 intersect.

  FIG. 6 shows an equivalent circuit of the Cs on Gate type TFT array shown in FIG. In the equivalent circuit of FIG. 6, the gate line 14 and the source line 15 are illustrated as being divided into two even-numbered and odd-numbered line groups.

  A pixel 12oo is provided in the vicinity of a portion where the odd-numbered gate line 14o and the odd-numbered source line 15o intersect. One end of the pixel (Pixel) 12oo is connected to the TFT 11oo, and the other end is connected to the additional capacitor (Cs) 13oo. The other end of the additional capacitor (Cs) 13oo is connected to the even-numbered gate line 14e. The drain D of the TFT 11oo is connected to the pixel 12oo, the gate G is connected to the odd-numbered gate line 14o, and the source S is connected to the odd-numbered source line 15o.

  Similarly, a pixel 12oe is provided in the vicinity of a portion where the odd-numbered gate line 14o and the even-numbered source line 15e intersect. One end of the pixel (Pixel) 12oe is connected to the TFT 11oe, and the other end is connected to the additional capacitor (Cs) 13oe. The other end of the additional capacitor (Cs) 13oe is connected to the even-numbered gate line 14e. The drain D of the TFT 11oe is connected to the pixel 12oe, the gate G is connected to the odd-numbered gate line 14o, and the source S is connected to the even-numbered source line 15e.

  Further, a pixel 12eo is provided in the vicinity of a portion where the even-numbered gate line 14e and the odd-numbered source line 15o intersect. One end of the pixel (Pixel) 12eo is connected to the TFT 11eo, and the other end is connected to the additional capacitor (Cs) 13eo. The other end of the additional capacitor (Cs) 13eo is connected to the odd-numbered gate line 14o. The drain D of the TFT 11eo is connected to the pixel 12eo, the gate G is connected to the even-numbered gate line 14e, and the source S is connected to the even-numbered source line 15e.

  Further, a pixel 12ee is provided in the vicinity of a portion where the even-numbered gate line 14e and the even-numbered source line 15e intersect. One end of the pixel 12ee is connected to the TFT 11ee, and the other end is connected to the additional capacitor (Cs) 13ee. The other end of the additional capacitor (Cs) 13ee is connected to the odd-numbered gate line 14o. The drain D of the TFT 11ee is connected to the pixel 12ee, the gate G is connected to the even-numbered gate line 14e, and the source S is connected to the even-numbered source line 15e.

  Accordingly, the voltage of the odd-numbered source line 15o is applied to the pixel (Pixel) 12oo according to the on-pulse signal of the odd-numbered gate line 14o, and the on-pulse of the odd-numbered gate line 14o is applied to the pixel (Pixel) 12oe. The voltage of the even-numbered source line 15e is applied according to the signal, and the voltage of the odd-numbered source line 15o is applied to the pixel (Pixel) 12eo according to the on-pulse signal of the even-numbered gate line 14e. Pixel) 12ee is applied with the voltage of the even-numbered source line 15e in accordance with the on-pulse signal of the even-numbered gate line 14e.

  FIG. 7 shows a signal pattern of an inspection signal within one gate period by the Cs on Gate type TFT array of the present invention. In this signal pattern, for example, pixels 12 (12oo, 12oe, 13eo, 12ee) are output by outputting on-pulse signals of the gate lines 14 (14o, 14e) at unequal time intervals within one gate period. The positive voltage holding time for holding the positive voltage is set to be long. Holding at a negative voltage-The voltage holding time is shortened because one gate period has a constant time width.

  The unequal holding time ratio can be, for example, 3: 1 as in the case of the Cs on Com TFT array. According to this time ratio, the holding time can be reduced compared to the conventional time ratio. It can be made 1.5 times longer. When the gate period is 16 msec, the conventional holding time of 8 msec can be set to 12 msec. In TFT array inspection, defects that depend on the retention time appear empirically at a retention time of about 10 msec or more. Therefore, a defect that depends on the retention time is detected by setting the retention time ratio to 3: 1. Can do. The time ratio of the holding time is an example, and other time ratios may be used.

  In FIG. 7, for convenience of explanation, one gate period is indicated by 10 time intervals of 1 to 10, and an example in which an on-pulse signal is output in a period indicated by 1 and a period indicated by 8 in this one gate period is shown. Therefore, the time ratio of the holding time is set to 3: 1.

  For example, within a period indicated by 1, an on-pulse signal (+ 15V) is first applied to an odd-numbered gate line (Go), and then an on-pulse signal (+ 15V) is applied to an even-numbered gate line (Ge). By setting the voltage of the source line 14 (So, Se) during the period indicated by 1 to +10 V, the voltage of the pixel 12 is held for the + voltage holding time.

  Next, within a period indicated by 8, an on-pulse signal (+ 15V) is first applied to the even-numbered gate line (Ge), and then an on-pulse signal (+ 15V) is applied to the odd-numbered gate line (Go). By setting the voltage of the source line 14 (So, Se) in the period indicated by 8 to −10V, the voltage of the pixel 12 is held in the −voltage holding time.

  In this inspection signal pattern, all the pixels on the TFT substrate are simultaneously set to the same voltage.

  The present invention can be applied not only to a TFT array inspection process in a liquid crystal manufacturing apparatus but also to a defect inspection of a TFT array provided in an organic EL or various semiconductor substrates.

It is the schematic of the TFT array test | inspection apparatus of this invention. It is a figure which shows typically the structure of a Cs on Com type | mold TFT array. It is an equivalent circuit diagram of a Cs on Com type TFT array. It is a figure for demonstrating the signal pattern of the inspection signal in 1 gate period by the Cs on Com type | mold TFT array of this invention. It is a figure which shows typically the structure of a Cs on Gate type TFT array. It is an equivalent circuit diagram of a Cs on Gate type TFT array. It is a figure for demonstrating the signal pattern of the test | inspection signal within 1 gate period by the Cs on Gate type TFT array of this invention. It is an example of a pattern of an inspection signal applied to a TFT array when inspecting the TFT array.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... TFT array inspection apparatus, 2 ... Electron source, 3 ... Secondary electron detector, 4 ... Inspection signal production | generation part, 5 ... Signal processing part, 6 ... Defect detection part, 7 ... Stage, 8 ... Probe, 9 ... Scanning Control part, 10 ... TFT substrate, 11 ... TFT, 11A ... TFT area, 12 ... Pixel electrode, 13 ... Addition capacitor, 14 ... Gate line, 15 ... Source line, 16 ... Cs line.

Claims (5)

A TFT substrate inspection method for inspecting a TFT array for defects by applying a voltage to the TFT array of the TFT substrate,
Inspection of a TFT substrate characterized in that the time ratio between the first period for holding the pixel electrode at a positive potential and the second period for holding the pixel electrode at a negative potential is unequal within one gate period. Method.   Within the one gate period, the time period of the on-pulse signal of the TFT gate applied to the gate line is made unequal, thereby making the time ratio between the first period and the second period unequal. The method for inspecting a TFT substrate according to claim 1. The TFT array is a Cs on Com TFT array that connects an additional capacitor (Cs) to a common line.
A plurality of gate lines provided on the TFT substrate are divided into two gate line groups by a predetermined gate line, and a pulse signal for turning on the gate of the TFT is synchronized with each of the gate line groups at the unequal time period. The method for inspecting a TFT substrate according to claim 2, wherein the method is applied. The TFT array is a Cs on Gate TFT array that connects an additional capacitor (Cs) to a gate line,
A plurality of gate lines provided in the TFT substrate are divided into two gate line groups by a predetermined gate line, and a pulse signal for turning on the gate of the TFT is applied to each of the gate line groups with the unequal time period, and The TFT substrate inspection method according to claim 2, wherein the TFT substrate is applied asynchronously. A TFT substrate inspection apparatus that inspects defects in a TFT array by applying a voltage to the TFT array of the TFT substrate and detecting a voltage state due to the voltage application.
An electron beam source for irradiating the TFT substrate with an electron beam;
A detector for detecting secondary electrons emitted from the TFT substrate;
An inspection signal generator for generating and applying an inspection signal to the TFT array on the TFT substrate;
A defect detection unit that detects a defect of the TFT array based on a detection signal of the detector;
The inspection signal generation unit includes a first period in which the time period of the on-pulse signal of the gate of the TFT applied to the gate line is unequal within one gate period of the TFT array and the pixel electrode is held at a positive potential, An inspection apparatus for a TFT substrate, wherein the time ratio of the second period in which the electrode is held at a negative potential is made unequal .