JP5466393B2 - TFT array inspection method and TFT array inspection apparatus - Google Patents

Description

  The present invention relates to a TFT array inspection performed in a manufacturing process of a liquid crystal substrate or the like, and more particularly, to a TFT array drive when performing a TFT array inspection.

  In the manufacturing process of a semiconductor substrate on which a TFT array such as a liquid crystal substrate or an organic EL substrate is formed, a TFT array inspection process is included in the manufacturing process, and a defect inspection of the TFT array is performed in this TFT array inspection process.

  The TFT array is used as a switching element for selecting a pixel electrode of a liquid crystal display device, for example. In a substrate including a TFT array, for example, a plurality of gate lines functioning as scanning lines are disposed in parallel, and a plurality of source lines functioning as signal lines are disposed orthogonal to the gate lines. A TFT (Thin Film Transistor) is disposed in the vicinity of a portion where the lines intersect, and a pixel electrode is connected to the TFT.

  The liquid crystal display device is configured by sandwiching a liquid crystal layer between a substrate provided with the TFT array described above and a counter substrate, and a pixel capacitor is formed between the counter electrode and the pixel electrode provided in the counter substrate. In addition to the pixel capacitor, an additional capacitor (Cs) is connected to the pixel electrode. One of the additional capacitors (Cs) is connected to the pixel electrode, and the other is connected to the common line or the gate line. A TFT array configured to be connected to the common line is referred to as a Cs on Com type TFT array, and a TFT array configured to be connected to the gate line is referred to as a Cs on Gate type TFT array.

  In this TFT array, a scanning line (gate line) or a signal line (source line) is disconnected, a scanning line (gate line) and a signal line (source line) are short-circuited, or a pixel defect due to a characteristic defect of a TFT driving a pixel. In the defect inspection, for example, the counter electrode is grounded, a DC voltage of, for example, −15 V to +15 V is applied to all or part of the gate line at a predetermined interval, and an inspection signal is applied to all or part of the source line. By doing that. (For example, the prior art of patent document 1.)

  The TFT array inspection apparatus can detect a defect by inputting a driving signal for inspection to the TFT array and detecting the potential state at that time.

  Various defects can occur in a TFT array during its manufacturing process. As a defect of the pixel electrode, for example, a short-circuit defect (S-DSshort) is known between the pixel electrode and the source line, and a short-circuit defect (G-DSshort) is known between the pixel electrode and the gate line. Further, a disconnection defect (D-open) between the pixel electrode and the TFT is known.

  In addition to the above-described defects in each pixel electrode, there is a so-called adjacent defect that occurs between adjacent pixel electrodes. As this adjacent defect, a defect between pixel electrodes adjacent in the horizontal direction (referred to as horizontal PP), a defect between pixel electrodes adjacent in the vertical direction (referred to as vertical PP), and a short circuit between adjacent source lines (S-Sshort) Short circuit between adjacent gate lines (referred to as G-Gshort) is known.

  FIG. 6 is a view for explaining adjacent defects in the horizontal direction. The broken lines in FIG. 6 indicate a short-circuit defect (lateral PP) between the pixel electrodes 12eo and 12ee adjacent in the horizontal direction and a short-circuit defect (S-Sshort) between the source lines Slo and Sle adjacent in the horizontal direction. Each is shown. In FIG. 6, reference numeral 11 denotes a TFT, reference numeral 12 denotes a pixel electrode, reference numeral 13 denotes an additional capacitor, reference numeral 14 denotes a gate line, reference numeral 15 denotes a source line, and each reference numeral is given. Subscripts “o” and “e” indicate adjacent gate lines or source lines, “oo” indicates a point where the gate line Glo and the source line Slo intersect, and “oe” indicates the gate line Glo and the source line Sle. “Eo” indicates a point where the gate line Gle and the source line Slo intersect, and “ee” indicates a point where the gate line Gle and the source line Sle intersect.

  In a TFT array inspection apparatus using an electron beam, the pixel (ITO electrode) is irradiated with an electron beam, and secondary electrons emitted by this electron beam irradiation are detected and applied to the pixel (ITO electrode). The voltage waveform is changed to a secondary electron waveform and imaged by a signal, whereby the TFT array is electrically inspected.

  Among the adjacent defects in the horizontal direction shown in FIG. 6, as a drive pattern for inspecting an adjacent defect generated in a short-circuit defect (lateral PP) between adjacent pixel electrodes 12eo and 12ee across the source line, for example, FIG. There is an example. FIGS. 7A and 7B show examples of source signals (indicated by solid lines in the figure) applied to adjacent source lines in order to detect short-circuit defects between adjacent pixel electrodes across the source line. . FIG. 8 shows the potential distribution of the pixel electrode formed by this drive pattern.

  In the section SA of FIG. 7, the source signal So of FIG. 7A applies “+10 V” to the pixel electrodes 12oo and 12eo via the TFTs 11oo and 11oe in FIG. As the source signal Se, “−10 V” is applied to the pixel electrodes 12oe and 12ee via the TFTs 11oe and 11ee in FIG. The voltage is applied with the gate turned on by a gate signal G (+20 V in FIG. 7D). 7A and 7B, the signal indicated by the broken line indicates the voltage of each pixel electrode. The voltage detection of each pixel electrode is performed during a measurement period set within a period in which a negative voltage (-15 V in FIG. 7) is applied to the gate signal G and the gate is turned off.

  The inspection signal of the drive pattern in the section SB interchanged with the positive and negative of the section SA is alternately applied to adjacent pixel electrodes.

  When there is no adjacent defect, “+ voltage” (“+10 V” in the example of FIG. 7A) is applied to one of the pixel electrodes adjacent to each other across the source line, and the other A “−voltage” (“−10 V” in the example of FIG. 7B) is applied to the pixel electrode.

  When there is an adjacent defect, “+ voltage” (“+10 V” in the example of FIG. 7A) is applied to one pixel electrode, and “−voltage” (FIG. 7 ( In the example of b), “−10 V”) is applied, but since the adjacent pixel electrodes across the source line are short-circuited, the potential of both pixel electrodes is due to the difference in charge rate due to the IV characteristics of the TFT. As shown in FIG. 7C, the negative potentials Vas and Vbs are charged.

  The defect determination can be performed based on the potential distribution of the two pixel electrodes obtained by switching the drive patterns described above to obtain the potential distribution of the pixel electrodes by adding the voltages of the same pixel electrodes. FIG. 8A shows an example when there is no adjacent defect.

  In the driving pattern, the voltages applied to the pixel electrodes adjacent to each other across the source line have the opposite sign and the absolute value are equal, and the two patterns are adjacent to each other in the time series in order to reverse the relation in the time series. The potential distribution detected in (1) has a relationship of potentials having opposite signs and equal absolute values.

  In FIG. 8A, the potential distribution A ("+" distribution of the potential Vao corresponding to the source line Slo and "-" distribution of the potential Vae corresponding to the source line Sle) and the potential distribution B (to the source line Slo). When the “−” distribution of the corresponding potential Vbo and the “+” distribution of the potential Vbe corresponding to the source line Sle) are added, any pixel electrode becomes “zero potential”.

  On the other hand, FIG. 8B shows an example where there is an adjacent defect. When adjacent pixel electrodes are short-circuited across the source line, the short-circuited pixel electrode has the same potential, which is different from the potential of the pixel electrode without adjacent defects. Therefore, when the potential distribution A and the potential distribution B in FIG. 8B are added, the potential of the pixel electrode having the adjacent defect becomes a predetermined potential (potential Vas, potential Vbs) other than “zero potential”. Usually, the potential Vas and the potential Vbs are the same. When there is no adjacent defect, the added potential is “zero potential”, and therefore, by extracting a pixel electrode having a predetermined potential other than “zero potential”, the pixel electrode having the adjacent defect can be detected.

  The reason why the potential of the pixel electrode does not become “zero potential” when the adjacent pixel electrodes across the source line are short-circuited is due to the IV characteristics of the TFT. The formation of a potential when adjacent pixel electrodes are short-circuited will be described with reference to FIG.

  FIG. 9A schematically shows the IV characteristics of the TFT. In this IV characteristic, the horizontal axis indicates the voltage VG-S between the gate and the source of the TFT, and the vertical axis indicates the drain current Id. The drain current supplies a current to a capacitor formed by the pixel electrode, thereby setting the pixel electrode to a predetermined voltage. FIG. 9B schematically shows a potential change when adjacent pixel electrodes are applied with + 10V to one pixel electrode and −10V to the other pixel electrode from the state of 0V. .

  The pixel electrodes having adjacent defects are charged at the same time, but the charge rate of the capacitance of the pixel electrode depends on the magnitude of the drain current, and the pixel electrode having a large drain current is charged quickly. Therefore, the potential of the pixel electrode of the adjacent defect is biased from zero potential.

When the gate voltage is + 20V, VG-S of the pixel electrode to which + 10V is applied is 10V, and VG-S of the pixel electrode to which -10V is applied is 30V. Since the difference in VG-S causes the magnitude of the drain current, a pixel electrode having a large VG-S is charged to a predetermined potential earlier than a pixel electrode having a small VG-S. A broken line a in FIG. 9B indicates a change in potential of the pixel electrode having a large VG-S, and a broken line b in FIG. 9B indicates a change in potential of the pixel electrode having a small VG-S. Due to this difference in potential change, the potential of the adjacent pixel electrode is biased from “zero potential” to one potential pressure side (here, the − side potential side) as shown by a solid line c in FIG. 9B. When + 10V and -10V are applied simultaneously, the potential of the pixel electrode having an adjacent defect is about -2V to -3V.
JP-A-5-307192

  Since the potential of the pixel electrode of the adjacent defect across the source line is determined by the difference in charge rate between + charge and −charge, the potential difference between the potential of the normal pixel electrode and the potential of the pixel electrode of the adjacent defect is small. Therefore, it is difficult to detect the potential difference.

  Accordingly, the present invention has been made to solve the above-mentioned problems and to increase the detection sensitivity of adjacent defects of pixel electrodes sandwiching a source line in TFT array inspection, and the potential difference between pixel electrodes having adjacent defects and normal pixel electrodes. The purpose is to increase.

The present invention inspects defects in a TFT array based on the distribution of potentials of each pixel electrode obtained by applying a voltage to the TFT array on the TFT substrate and detecting secondary electrons obtained by electron beam irradiation. In the inspection of the TFT substrate, a short-circuit defect between pixel electrodes adjacent to each other with the source line interposed therebetween is detected, which can be an inspection method aspect and an inspection apparatus aspect.

  The aspect of the TFT substrate inspection method of the present invention uses a drive pattern in which different voltages are applied to adjacent pixel electrode rows across the source line of the TFT array, and the adjacent potential distribution of the pixel electrode obtained by this drive pattern A short-circuit defect between pixel electrodes to be detected is detected.

  The drive pattern used in the inspection method of the present invention is an inspection signal pattern in which a negative voltage is applied only to one of the adjacent pixel electrode columns. By applying this negative voltage, a pixel electrode having a short circuit defect in the other pixel electrode row of the adjacent pixel electrode rows is forcibly offset to the negative potential side. This increases the potential difference between the potential of the pixel electrode having an adjacent defect and the potential of a normal pixel electrode, and facilitates detection of a short-circuit defect between adjacent pixel electrodes across the source line.

The driving pattern used in the TFT substrate inspection method of the present invention is such that a positive voltage is applied to the other pixel electrode column and a first negative voltage is applied to one pixel electrode column with respect to the pixel electrode column adjacent along the source line And a second period in which a second negative voltage that is more negative than the first negative voltage is applied to only one pixel electrode column in time series, A pattern inspection signal is alternately applied to the pixel electrode columns adjacent to each other along the source line while changing the polarity . The potential distribution of each pixel electrode acquired in the second period is added for each pixel electrode, and in the potential distribution thus added, the potential of the adjacent pixel electrode having a short circuit defect is more negative than the potential of the normal pixel electrode. A short-circuit defect between adjacent pixel electrodes across the source line is detected by biasing to the side and comparing with the potential in the normal state .

The voltage applied to the pixel electrode array is the voltage of the source line of the TFT array. In the first period, the positive voltage is applied to the gate line of the TFT array to turn on the TFT and apply the voltage to the source line. In the second period, the TFT is turned off by applying a negative voltage to the gate line of the TFT array, and the second negative voltage is applied to the source line of the TFT array of one pixel electrode column.

  The TFT substrate inspection apparatus of the present invention applies a voltage to the TFT array of the TFT substrate, detects the voltage state due to the voltage application by secondary electrons obtained by electron beam irradiation, and inspects defects in the TFT array. A TFT substrate inspection device that generates and applies an inspection signal to a TFT array on an TFT substrate, an electron beam source that irradiates the TFT substrate with an electron beam, a detector that detects secondary electrons emitted from the TFT substrate. An inspection signal generation unit and a defect detection unit that detects a short-circuit defect between adjacent pixel electrodes based on a potential distribution of the pixel electrode obtained by a drive pattern based on a detection signal of the detector.

  The inspection signal generation unit generates an inspection signal of a drive pattern that applies different voltages to adjacent pixel electrode rows across the source line of the TFT array. In this driving pattern, a negative voltage is applied only to one pixel electrode column of an adjacent pixel electrode column, and a pixel electrode that is short-circuited defective in the other pixel electrode column of the adjacent pixel electrode column is negatively applied. By forcibly offset to the potential side, a short circuit defect between adjacent pixel electrodes across the source line is detected.

Driving patterns, to the pixel electrode column adjacent along the source line, a first period for applying the first negative voltage to one of the pixel electrode array by applying a positive voltage to the other of the pixel electrode array, wherein Two periods of a second period in which a second negative voltage that is more negative than the first negative voltage is applied to only one pixel electrode column are arranged in time series.

  The inspection signal generation unit alternately applies the inspection signal of the TFT drive pattern to the adjacent pixel electrode columns along the source line. The defect detection unit adds the potential of each pixel electrode acquired in the second period for each pixel electrode, and in the potential distribution of the added potential, the potential of the adjacent pixel electrode having a short-circuit defect is the normal pixel electrode potential. By biasing to the negative potential side, a short-circuit defect between adjacent pixel electrodes across the source line is detected.

The voltage applied to the pixel electrode array is the voltage of the source line of the TFT array, and the inspection signal generation unit turns on the TFT by applying a positive voltage to the gate line of the TFT array in the first period. A voltage is applied to the source line, and in the second period, the TFT is turned off by applying a negative voltage to the gate line of the TFT array, and a second negative voltage is applied to the source line of the TFT array of one pixel electrode column. Apply.

  According to the present invention, in the pixel electrode sandwiching the source line, the potential difference between the pixel electrode having the adjacent defect and the normal pixel electrode can be increased, and the detection sensitivity of the adjacent defect can be increased.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a schematic view of a TFT array inspection apparatus of the present invention. The TFT array inspection apparatus 1 includes an inspection signal generation unit 4 that generates an inspection signal for array inspection on the TFT substrate 10, a prober 8 that applies the inspection signal generated by the inspection signal generation unit 4 to the TFT substrate 10, and a TFT substrate. A mechanism (2, 3, 5) for detecting the voltage application state of the TFT and a defect detector 6 for detecting a defect of the TFT array based on the detection signal.

  The prober 8 includes a prober frame provided with probe pins (not shown). The prober 8 brings the probe pin into contact with the electrode formed on the TFT substrate 10 by placing it on the TFT substrate 10 or the like, and applies the inspection signal generated by the inspection signal generation unit 4 to the TFT array.

  The mechanism for detecting the voltage application state of the TFT substrate can have various configurations. The configuration shown in FIG. 1 is a detection configuration using an electron beam. An electron beam source 2 that irradiates an electron beam on the TFT substrate 10 and a secondary electron that detects secondary electrons emitted from the TFT substrate 10 by the irradiated electron beam. The secondary electron detector 3 and the secondary electron detector 3 are provided with a signal processing unit 5 that performs signal processing on detection signals from the secondary electron detector 3 and detects a potential state on the TFT substrate 10.

  Since the TFT array irradiated with the electron beam emits secondary electrons corresponding to the voltage of the applied inspection signal, the potential state of the TFT array can be detected by detecting the secondary electrons.

  The defect detection unit 6 detects defects in the TFT array by comparing with the potential state in the normal state based on the potential state of the TFT array acquired by the signal processing unit 5.

  The inspection signal generation unit 4 generates an inspection signal inspection pattern for driving the TFT array formed on the TFT substrate 10. This inspection pattern will be described later.

  The scanning control unit 9 controls the stage 7 and the electron beam source 2 in order to scan the inspection position of the TFT array on the TFT substrate 10. The stage 7 moves the TFT substrate 10 to be placed in the XY direction, and the electron beam source 2 scans the irradiation position of the electron beam by shaking the electron beam irradiating the TFT substrate 10 in the XY direction. The scanning position becomes the detection position. The above-described configuration of the TFT array inspection apparatus is an example, and is not limited to this configuration.

  Next, an inspection method for detecting a short-circuit defect between adjacent pixel electrodes by applying a voltage to the TFT array of the TFT substrate and detecting secondary electrons obtained by electron beam irradiation will be described with reference to FIGS. 4 will be described.

  The TFT array inspection of the present invention is performed based on the potential distribution of the pixel electrode obtained by using a driving pattern in which different voltages are applied to adjacent pixel electrode rows across the source line of the TFT array.

  The drive pattern has an inspection signal for applying a negative voltage only to one pixel electrode row of the adjacent pixel electrode rows, and the application of this negative voltage causes a short circuit defect in the other pixel electrode row. By forcibly offset the pixel electrode to be negative potential side, the potential of the pixel electrode having the adjacent defect is largely biased to the negative potential side, and the potential of the pixel electrode having the adjacent defect and the potential of the normal pixel electrode are The potential difference between the pixel electrode and the pixel electrode is made large so that the pixel electrode short-circuit defect can be easily detected.

  In the conventional driving pattern, a potential difference is formed between a potential of a pixel electrode having an adjacent defect and a potential of a normal pixel electrode based on a difference in charge rate to the pixel electrode to be short-circuited, and thus the potential difference is increased. However, by using the drive pattern according to the present invention, the pixel electrode having a short-circuit defect is forcibly offset to the negative potential side, so that the potential of the pixel electrode having an adjacent defect can be largely biased to the negative potential side. Therefore, it is possible to easily detect the short-circuit defect of the pixel electrode due to the potential difference of the pixel electrode.

  FIG. 2 is a signal diagram for explaining an example of a drive pattern by an inspection signal used for the TFT array inspection of the present invention.

  The source signal So in FIG. 2A applies “+10 V” to the pixel electrodes 12oo and 12eo via the TFTs 11oo and 11oe in FIG. 6, and the source signal Se in FIG. “−10 V” is applied to the pixel electrodes 12oe and 12ee through the TFTs 11oe and 11ee. The voltage application is performed in the first period T1 and the second period T2 in FIG. In the first period T1, a positive voltage is applied to the pixel electrode, and in the second period T2, a negative voltage is applied to the pixel electrode. The voltage application in the first period T1 is performed by turning on the gate by a gate signal. The voltage application in the second period T2 is such that the source voltage applied to one pixel electrode is a negative voltage (“−20 V”) lower than the source voltage applied to the other pixel electrode in a state where the gate is turned off. As a result, only one of the pixel electrodes is forcibly offset to the negative potential side, thereby increasing the potential difference between the adjacent defective pixel electrode and the normal pixel electrode to facilitate detection.

  The adjacent pixel electrodes are alternately applied in the section SA and the section SB by exchanging the relationship between So and Se in the inspection signal of the above drive pattern.

  Signals indicated by broken lines in FIGS. 2A and 2B indicate the voltage of each pixel electrode. The voltage detection of each pixel electrode is performed during a measurement period set within a period in which a negative voltage (-15 V in FIG. 7) is applied to the gate signal G and the gate is turned off.

When there is no adjacent defect, in the first period T1 during which the gate is turned on (FIG. 2D), a positive “+” is applied to the other pixel electrode among the adjacent pixel electrodes across the source line. Voltage "(" + 10V "in the examples of FIGS. 2A and 2B) is applied, and a negative" -voltage "(in the examples of FIGS. 2A and 2B) is applied to one pixel electrode. -10V ") is applied.

In the second period T2, with the gate turned off, the source voltage applied to one pixel electrode is set to a negative voltage lower than the source voltage applied to the other pixel electrode. In the second period T2, among the pixel electrodes adjacent to each other with the source line interposed therebetween, the pixel electrode to which a positive “+ voltage” is applied holds a positive potential because the gate is off. On the other hand, a negative second voltage lower than the gate voltage (“−20 V” in the examples of FIGS. 2A and 2B) is applied to one pixel electrode, and the drain voltage is applied to the pixel electrode by this second voltage. Current flows and becomes a low negative potential.

When there is an adjacent defect, in the first period T1, as in the conventional case, “+ voltage” (“+10 V” in the example of FIG. 2A) is applied to the other pixel electrode, Since “−electricity” (“−10 V” in the example of FIG. 2B) is applied to one pixel electrode and adjacent pixel electrodes across the source line are short-circuited, the potentials of both pixel electrodes Are charged to the negative potentials Vas and Vbs due to the difference in charge speed due to the IV characteristics of the TFT.

On the other hand, in the second period T2, the other pixel electrode is held at a positive potential, and one pixel electrode has a negative second voltage lower than the gate voltage (FIGS. 2A and 2B). In the example of FIG. 2, “−20 V”) is applied to obtain a low negative potential (negative potentials VAs and VBs in FIG. 2C).

  The defect determination can be performed based on the potential distribution of the two pixel electrodes obtained by switching the drive patterns described above to obtain the potential distribution of the pixel electrodes by adding the voltages of the same pixel electrodes. 3A and 3B are diagrams for explaining the potential distribution of the pixel electrode. FIG. 3A shows an example when there is no adjacent defect, and FIG. 3B shows an example when there is an adjacent defect. .

  In the driving pattern, the voltages applied to the pixel electrodes adjacent to each other across the source line have the opposite sign and the absolute value are equal, and the two patterns are adjacent to each other in the time series in order to reverse the relation in the time series. The potential distribution detected in (1) has a relationship of potentials having opposite signs and equal absolute values.

  When there is no adjacent defect, the potential distribution A ("+ 10V" distribution of the potential VAo corresponding to the source line Slo and "-20V" distribution of the potential VAe corresponding to the source line Sle in FIG. ) And the potential distribution B (the “−20 V” distribution of the potential VBo corresponding to the source line Slo and the “+10 V” distribution of the potential VBe corresponding to the source line Sle) are added to each pixel electrode. 5V ”.

  On the other hand, when there is an adjacent defect, the pixel electrodes adjacent to each other across the source line are short-circuited. Therefore, the potential of the shorted pixel electrode is the same, and is different from the potential of the pixel electrode without the adjacent defect. It becomes a potential. In the measurement period set in the second period T2, the potential VAs and the potential VBs are applied with the second voltage ("-20V" in the example of FIG. 2), so the adjacent defect in FIG. The potential of the pixel electrode is “-20V”.

  Therefore, when the potential distribution A and the potential distribution B in FIG. 3B are added, the potentials VAs and VBs of the pixel electrodes having adjacent defects become a predetermined potential “−20 V” other than “zero potential”. The potential of the pixel electrode without adjacent defects is “−5V”. Thus, the potential distribution of the pixel electrode can increase the potential difference between the potential of the pixel electrode having an adjacent defect and the potential of the pixel electrode having no adjacent defect.

  FIG. 4 is a flowchart for explaining the inspection procedure of the TFT array inspection of the present invention. In the section SA, an inspection signal of a drive pattern that forms the potential distribution A is applied (S1), the potential of each pixel electrode is measured within the measurement period (S2), and the drive for forming the potential distribution B is performed in the section SB. A pattern inspection signal is applied (S3), and the potential of each pixel electrode is measured within the measurement period (S4).

  Based on the potential distribution A obtained in S2 and the potential distribution B obtained in S4, the potential is added to each pixel electrode (S5), and defect determination is performed based on the potential of the pixel electrode obtained by the addition (S5). S6).

  FIG. 5 is a block diagram for explaining a configuration example of the defect detection unit 6. FIG. 5A shows a case where signal processing for defect detection is performed by digital processing, and FIG. 5B shows a case where signal processing for defect detection is performed by analog processing.

  The configuration of the defect detection unit 6 shown in FIG. 5A is an A / D conversion circuit 6A that converts a detection potential from an analog signal to a digital signal, and temporarily stores the potentials of the sections SA and SB for each pixel electrode. A storage circuit 6B, an average value calculation circuit 6C that calculates an average value of the potential of the section SA and the potential of the section SB stored in the storage circuit 6B, and the potential calculated by the average value calculation circuit 6C is compared with a threshold value; And a comparison circuit 6D for determining the presence or absence of a defect. In the potential distribution example shown in FIG. 3B, a voltage value is set between −5V and −20V as the threshold value.

  The configuration of the defect detection unit 6 shown in FIG. 5B includes an addition circuit 6a that adds the potentials of the sections SA and SB for each pixel electrode, and compares the potential calculated by the addition circuit 6a with a threshold value. And a comparison circuit 6b for determining presence or absence. In the potential distribution example shown in FIG. 3B, a voltage value is set between −5V and −20V as the threshold value. The adder circuit 6a can be configured using, for example, an integrating circuit using an operational amplifier.

  In the above description, a Cs on Com TFT array is taken as an example, but the same can be applied to a Cs on Gate TFT array.

  The present invention can be applied not only to a TFT array inspection process in a liquid crystal manufacturing apparatus but also to a defect inspection of a TFT array provided in an organic EL or various semiconductor substrates.

It is the schematic of the TFT array test | inspection apparatus of this invention. It is a signal diagram for demonstrating an example of the drive pattern by the test | inspection signal used for the TFT array test | inspection of this invention. It is a figure for demonstrating the electric potential distribution of the pixel electrode of this invention. It is a flowchart for demonstrating the test | inspection procedure of the TFT array test | inspection of this invention. It is a block diagram for demonstrating the structural example of the defect detection part of this invention. It is a figure for demonstrating the adjacent defect of a horizontal direction. It is a signal diagram for demonstrating an example of the drive pattern which test | inspects the adjacent defect which arises in a short circuit defect (lateral PP). It is a figure which shows the electric potential distribution of the pixel electrode formed with a drive pattern. It is a figure for demonstrating electric potential formation when the adjacent pixel electrode is short-circuited.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Array inspection apparatus, 2 ... Electron beam source, 3 ... Secondary electron detector, 4 ... Inspection signal generation part, 5 ... Signal processing part, 6 ... Defect detection part, 6A ... Conversion circuit, 6B ... Memory circuit, 6C ... average value calculation circuit, 6D ... comparison circuit, 6a ... addition circuit, 6b ... comparison circuit, 7 ... stage, 8 ... prober, 9 ... scanning control unit, 10 ... substrate, 12oe, 12ee, 12oo, 12eo ... pixel electrode.

Claims (2)

Inspection of TFT substrate that inspects TFT array for defects based on potential distribution of each pixel electrode obtained by applying voltage to TFT array of TFT substrate and detecting secondary electrons obtained by electron beam irradiation In the method
A drive pattern in which different voltages are applied to adjacent pixel electrode columns across the source line of the TFT array is used, and a short-circuit defect between the adjacent pixel electrodes is detected based on the potential distribution of the pixel electrode obtained by the drive pattern. Inspection method,
The driving pattern includes a first period in which a positive voltage is applied to the other pixel electrode column and a first negative voltage is applied to the one pixel electrode column, with respect to the adjacent pixel electrode columns along the source line; Two periods of a second period in which a second negative voltage that is more negative than the first negative voltage is applied to only one pixel electrode column in time series,
The voltage applied to the pixel electrode row is the voltage of the source line of the TFT array,
In the first period, applying a positive voltage to the gate line of the TFT array to turn on the TFT and applying a voltage to the source line;
An inspection signal for applying a negative second negative voltage lower than the gate voltage in the second period and causing a drain current to flow to one of the pixel electrodes by the second negative voltage to obtain a low negative potential; The inspection signal of the drive pattern is alternately applied to the pixel electrode columns adjacent to each other along the source line by changing the polarity, and the other pixel electrode column of the adjacent pixel electrode columns is applied by applying the second negative voltage. Forcibly offset the pixel electrode having a short-circuit defect to the second negative potential side,
Adding the potential distribution of each pixel electrode acquired in the second period for each pixel electrode;
In the distribution of the summed potential, biased to a negative potential than the potential of the normal pixel electrode potential of the adjacent pixel electrodes short defect, the pixel electrodes adjacent to each other across the source lines by comparing the potential in a normal state A method for inspecting a TFT substrate, characterized by detecting a short-circuit defect therebetween. Defects in the TFT array based on the potential distribution of each pixel electrode obtained by applying a voltage to the TFT array on the TFT substrate and detecting the secondary electrons obtained by electron beam irradiation as a result of the voltage application A TFT substrate inspection apparatus for inspecting
An electron beam source for irradiating the TFT substrate with an electron beam;
A detector for detecting secondary electrons emitted from the TFT substrate;
An inspection signal generator for generating and applying an inspection signal to the TFT array on the TFT substrate;
A defect detection unit that detects a short-circuit defect between the adjacent pixel electrodes according to a distribution of potentials of the pixel electrodes obtained by the drive pattern based on a detection signal of the detector;
The inspection signal generator is
Generating a test signal of the driving pattern for applying different voltages to the pixel electrodes adjacent columns across the source lines of the TFT array, the polarity with respect to the adjacent pixel electrode array test signals of the drive pattern along the source line Apply them alternately
The driving pattern includes a first period in which a positive voltage is applied to the other pixel electrode column and a first negative voltage is applied to the one pixel electrode column, with respect to the adjacent pixel electrode columns along the source line; Two periods of a second period in which a second negative voltage that is more negative than the first negative voltage is applied to only the one pixel electrode column in time series;
The voltage applied to the pixel electrode row is the voltage of the source line of the TFT array,
In the first period, applying a positive voltage to the gate line of the TFT array to turn on the TFT and applying a voltage to the source line;
In the second period, a negative second negative voltage lower than a gate voltage is applied, and a drain current is caused to flow to one pixel electrode by the second negative voltage to obtain a low negative potential. The second negative voltage is applied only to one pixel electrode column of the pixel electrode column to be operated, and the application of the second negative voltage causes the pixel electrode having a short circuit defect in the other pixel electrode column of the adjacent pixel electrode column to Forcibly offset to the negative potential side of 2,
The defect detection unit adds the potential distribution of each pixel electrode acquired in the second period for each pixel electrode, and in the added potential distribution , the potential of an adjacent pixel electrode having a short-circuit defect is a normal pixel. than the potential of the electrode was biased to the negative potential side, and detecting a short circuit defect between the pixel electrodes adjacent to each other across the source lines by comparing the potential in a normal state, the inspection device of the TFT substrate.