JP5018455B2 - Semiconductor device manufacturing apparatus and semiconductor device manufacturing method - Google Patents

Semiconductor device manufacturing apparatus and semiconductor device manufacturing method Download PDF

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JP5018455B2
JP5018455B2 JP2007329330A JP2007329330A JP5018455B2 JP 5018455 B2 JP5018455 B2 JP 5018455B2 JP 2007329330 A JP2007329330 A JP 2007329330A JP 2007329330 A JP2007329330 A JP 2007329330A JP 5018455 B2 JP5018455 B2 JP 5018455B2
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pressurizing
semiconductor element
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pressurization
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JP2009152410A (en
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俊也 赤松
延弘 今泉
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Fujitsu Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/75Apparatus for connecting with bump connectors or layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/35Mechanical effects
    • H01L2924/351Thermal stress
    • H01L2924/3511Warping

Abstract

<P>PROBLEM TO BE SOLVED: To materialize a device for manufacturing a semiconductor device, which can effectively suppress the generation of voids in a resin layer. <P>SOLUTION: In the device for manufacturing the semiconductor device, especially when filling of an underfill material resin composition layer 3 is implemented using a membranous film, the pressing tool head 6 of a flip chip bonder forming the semiconductor manufacturing device is divided into a plurality of regions. Since those regions can be pressed with the sequences such as pressure, pressing timing, made mutually independent, the occurrence of voids can be substantially suppressed. <P>COPYRIGHT: (C)2009,JPO&amp;INPIT

Description

本発明は、とくにフリップチップ実装したBGA(ボール・グリッド・アレイ)などの半導体装置を製造する製造装置、すなわち半導体素子に形成されたバンプなどの突起電極と配線基板上の接続電極とを接続するのに用いられるフリップチップボンダなどに代表される製造装置に関し、特にアンダーフィル層が半導体素子―配線基板間に充填された形で接続を行う際に好適な加圧ツールヘッド機構を有する、半導体装置の製造装置に関する。   The present invention particularly relates to a manufacturing apparatus for manufacturing a semiconductor device such as a flip-chip mounted BGA (ball grid array), that is, a bump electrode formed on a semiconductor element and a connection electrode on a wiring board. The present invention relates to a manufacturing apparatus typified by a flip chip bonder and the like, and in particular, a semiconductor device having a pressure tool head mechanism suitable for making a connection with an underfill layer filled between a semiconductor element and a wiring board. It relates to a manufacturing apparatus.

BGAなどの実装形式を有する半導体装置を製造するフリップチップ実装は、その高密度実装の可能性から、近年、CPUをはじめとする高密度実装半導体装置において重要な製造手段となっている。   Flip chip mounting for manufacturing a semiconductor device having a mounting format such as BGA has recently become an important manufacturing means in high-density mounting semiconductor devices such as CPUs because of the possibility of high-density mounting.

フリップチップ実装は、はんだバンプなどからなる突起電極が形成された半導体素子を半導体素子実装用配線基板上にフリップチップボンダなど製造装置で圧着接合する。その際に、半導体素子と配線基板の間隙にアンダーフィル樹脂層が充填された構造にして、接合後のバンプ電極間の接触の排除や絶縁性の確保、さらに被接合部品間の接合強度の強化などを図っている。   In flip chip mounting, a semiconductor element on which a protruding electrode made of a solder bump or the like is formed is pressure bonded to a semiconductor element mounting wiring board by a manufacturing apparatus such as a flip chip bonder. At that time, the gap between the semiconductor element and the wiring board is filled with an underfill resin layer, eliminating contact between bump electrodes after bonding, ensuring insulation, and strengthening bonding strength between parts to be bonded. Etc.

このアンダーフィル樹脂層(ここでのアンダーフィル樹脂とは、熱硬化性アアンダーフィル用主剤樹脂や同樹脂硬化剤、硬化促進剤、無機材料フィラーなどからなるアンダーフィル材樹脂組成物を言う)の充填形成法に関しては、従来から各種方法が行われている。例えば、突起電極と配線基板を接合後、両者の間隙に粘度の低いアンダーフィル樹脂を注入するように充填し、樹脂の熱硬化性を用いて樹脂を固化しアンダーフィル樹脂層を形成する方法、また、逆に、半導体素子と配線基板との接合前に、一方の表面に粘度の低いアンダーフィル樹脂を滴下・塗布し、その後両者を接合してから加熱固化しアンダーフィル樹脂層を形成する方法も用いられる。   The underfill resin layer (the underfill resin here refers to an underfill resin composition comprising a main resin for thermosetting underfill, the same resin curing agent, a curing accelerator, an inorganic material filler, etc.) Various methods have been conventionally used for the filling method. For example, after bonding the protruding electrode and the wiring board, filling the gap between the two so as to inject a low-viscosity underfill resin, solidifying the resin using the thermosetting property of the resin, and forming the underfill resin layer, Conversely, a method of forming an underfill resin layer by dripping and applying a low-viscosity underfill resin on one surface before bonding the semiconductor element and the wiring board, and then bonding the two together and then heating and solidifying. Is also used.

しかし、これらの液状樹脂の充填による方法は、特に接合される部品間のギャップがますます狭く、かつ接合点が大量となる高密度フリップチップ実装においては、液状樹脂の粘度や注入・塗布条件等の制御によって形成樹脂層中のボイド発生を抑制することが容易ではなく、信頼性の高いBGA実装素子の形成が困難となっている。特に間隙への注入による方法は、ギャップが小さいと毛細管現象(キャピラリーフロー)による充填がより困難になる。   However, these liquid resin filling methods, especially in high-density flip chip mounting where the gap between the parts to be joined is increasingly narrow and the number of joints is large, the viscosity of the liquid resin, injection and coating conditions, etc. It is not easy to suppress the generation of voids in the formed resin layer by controlling the above, and it is difficult to form a highly reliable BGA mounting element. In particular, in the method by injection into the gap, if the gap is small, filling by capillary action (capillary flow) becomes more difficult.

このアンダーフィル樹脂の充填工程をより短タクトタイム化・高信頼化する方法として、一方の素子、例えば半導体素子表面に粘度の低いアンダーフィル樹脂を滴下・塗布してから、この樹脂を一旦乾燥させて、例えばはんだバンプを含む固形のフィルム状アンダーフィル樹脂層を形成し、次に他者、すなわち配線基板との間の加熱・圧着による接合を行う方法や、別途、アンダーフィル樹脂の固形フィルム形状のものを用意し、これを半導体素子側あるいは配線基板側に貼り付けて、その後、両者の加熱・圧着による接合を行う方法、が提案されている(例えば、特許文献1)。   As a method for shortening the takt time and increasing the reliability of the filling process of the underfill resin, a low-viscosity underfill resin is dropped and applied to the surface of one element, for example, a semiconductor element, and then the resin is once dried. For example, a method of forming a solid film-like underfill resin layer including solder bumps and then joining to the other person, that is, a wiring board by heating and pressure bonding, or separately forming a solid film shape of the underfill resin A method has been proposed in which a device is prepared, attached to the semiconductor element side or the wiring substrate side, and then bonded by heating and pressure bonding (for example, Patent Document 1).

特に、別途形成したフィルム状のアンダーフィル樹脂膜をチップに貼り付ける前期後者の方法では、アンダーフィル樹脂がチップと基板間で未充填となることが確実に回避され、また樹脂層厚の制御や樹脂総量制御も比較的容易となり、接合後における樹脂のチップエッジからのはみ出し量なども制御できるといった長所を有している。
特許第3558576号公報
In particular, the latter method in which the film-like underfill resin film formed separately is attached to the chip in the first half of the previous period can reliably prevent the underfill resin from being unfilled between the chip and the substrate, and the control of the resin layer thickness Control of the total amount of resin is relatively easy, and the amount of protrusion of the resin from the chip edge after bonding can be controlled.
Japanese Patent No. 3558576

発明者は、前記の、半導体素子と配線基板とのフリップフロップ接続の前に一旦乾燥して固形化したアンダーフィル樹脂層を適用する方法に関し、ボイド発生の抑制し、より信頼性の高いBGA半導体装置形成を目的に検討を加えた。   The inventor relates to a method of applying the underfill resin layer once dried and solidified before the flip-flop connection between the semiconductor element and the wiring board, and to suppress the generation of voids and to provide a more reliable BGA semiconductor. We examined for the purpose of device formation.

先ず、一方の表面、すなわち半導体素子のバンプ電極が形成された面に液状アンダーフィル樹脂を滴下し、十分にバンプ搭載面全体にこの樹脂が行き渡るようにした後、これを一旦、溶剤を蒸発させるように乾燥させて突起電極を含有するアンダーフィル樹脂層を形成した。しかし、乾燥した後のアンダーフィル樹脂層において膜減り現象、つまり樹脂表面に、顕著に観察される凹凸発生現象を抑制することができなかった。当然、この状態でのアンダーフィル樹脂層を用いてフリップチップ接続を継続すれば、凹凸部に存在する空隙が樹脂内に巻き込まれ、アンダーフィル樹脂を溶融・加熱固化する工程で、樹脂層中に多くの、先の空隙に起因するボイドが内在することとなる。   First, liquid underfill resin is dropped on one surface, that is, the surface on which the bump electrode of the semiconductor element is formed, and the resin is sufficiently spread over the entire bump mounting surface, and then the solvent is once evaporated. The underfill resin layer containing the protruding electrode was formed by drying as described above. However, the phenomenon of film thickness reduction in the underfill resin layer after drying, that is, the phenomenon of unevenness observed remarkably on the resin surface could not be suppressed. Naturally, if the flip-chip connection is continued using the underfill resin layer in this state, voids existing in the concavo-convex portions are caught in the resin, and the underfill resin is melted and heated and solidified in the resin layer. Many voids resulting from the previous voids are inherent.

そこで、固形の(溶媒が蒸発した状態の)フィルム状の、アンダーフィル樹脂膜(アンダーフィル材樹脂組成物膜)を別に形成し、これを半導体素子の突起電極形成面に貼り付ける方法を試した。具体的には、先ず極力平滑なベース材の表面、例えば、所定厚のPETフィルム上、あるいはポリッシュ基板面(Si基板ポリッシュ面やガラス面など)の上に液状(低粘度)アンダーフィル樹脂材をコーティングあるいは平坦化塗布し、溶媒が除去される程度の十分な乾燥をする。こうしてベース材の面上に乾燥した所定膜厚のフィルム形状のアンダーフィル材樹脂組成物膜を形成する。次いで、このベース材の面上の膜形成面と半導体素子のバンプ搭載面とを互いに押し付けて密着させ、形成した乾燥アンダーフィル樹脂層膜を半導体素子上に残すようにベース材を取り除く。こうして、バンプ搭載面上に密着・形成されたアンダーフィル樹脂層の表面は、前の滴下・乾燥方式の層の表面に比し、凹凸が大幅に改善された状態で形成できることが解った。   Thus, a method of separately forming a solid (under the solvent evaporated) film-like underfill resin film (underfill material resin composition film) and affixing it to the bump electrode formation surface of the semiconductor element was tried. . Specifically, first, a liquid (low viscosity) underfill resin material is applied on the surface of the base material as smooth as possible, for example, on a PET film having a predetermined thickness or on a polished substrate surface (Si substrate polished surface, glass surface, etc.). Apply coating or planarization and dry enough to remove solvent. Thus, a dried underfill material resin composition film having a predetermined film thickness is formed on the surface of the base material. Next, the film forming surface on the surface of the base material and the bump mounting surface of the semiconductor element are pressed and adhered to each other, and the base material is removed so as to leave the formed dry underfill resin layer film on the semiconductor element. Thus, it was found that the surface of the underfill resin layer adhered and formed on the bump mounting surface can be formed in a state in which the unevenness is greatly improved as compared with the surface of the previous dripping / drying layer.

このように形成した、平坦な表面を持つフィルム状のアンダーフィル材樹脂組成物層を用いたフリップチップボンディングを実際に実施したが、しかしこの場合においても、樹脂層中にボイドが発生するという課題が生じた。   Flip chip bonding using a film-like underfill material resin composition layer having a flat surface formed in this way was actually carried out, but in this case as well, there is a problem that voids are generated in the resin layer. Occurred.

図6に、典型的な、従来のフリップチップ接続方法を採用した半導体素子と接続基板との接続工程の断面模式図を示す。図6(1)に示すような、チップなどの半導体素子101の電極上に、はんだバンプなどの突起電極102が形成された突起電極接続用半導体素子を用意し、これに図6(2)に示すような、上記したような方法で突起電極102にフィルム状のアンダーフィル材樹脂組成物膜を貼り付け、突起電極102を取り込んだ形の、アンダーフィル材樹脂組成物層103を形成する。   FIG. 6 is a schematic cross-sectional view of a connection process between a semiconductor element and a connection substrate using a typical conventional flip-chip connection method. As shown in FIG. 6 (1), a protruding electrode connecting semiconductor element having a protruding electrode 102 such as a solder bump formed on an electrode of a semiconductor element 101 such as a chip is prepared. As shown, a film-like underfill material resin composition film is attached to the protruding electrode 102 by the method described above, and the underfill material resin composition layer 103 having the shape in which the protruding electrode 102 is taken in is formed.

あるいは、このアンダーフィル材樹脂組成物層103を形成する上で、例えば、はんだバンプの融点以下の温度(例えば、50〜80℃)でこのアンダーフィル材樹脂組成物膜を一旦低粘度化して、突起電極102を含む半導体素子面に溶融付着させことで、突起電極101をより効果的に取り込んだ形でアンダーフィル材樹脂組成物層103を形成してもよい。   Alternatively, in forming the underfill material resin composition layer 103, for example, the viscosity of the underfill material resin composition film is once lowered at a temperature lower than the melting point of the solder bump (for example, 50 to 80 ° C.), The underfill material resin composition layer 103 may be formed in such a manner that the protruding electrodes 101 are more effectively taken in by being melted and adhered to the semiconductor element surface including the protruding electrodes 102.

そして、図6(3)に示すように、配線基板104上に、突起電極102の位置に対向するように形成された接続電極105と、突起電極102とを接続すべく、フリップチップボンダの加圧ツールヘッド(ボンダヘッド)106に、吸着などによって取り付けられたアンダーフィル材樹脂組成物層103が形成されたバンプ接続用半導体素子を、はんだボール溶融温度(例えば、230〜250℃)のもとで、アンダーフィル材樹脂組成物層103の溶融状態化させ、加圧ツールヘッド106で加圧107を行い、電極間の電気的接続を実現する。このように、接続加工時ではアンダーフィル材樹脂組成物層103は溶融状態に保たれていて、接続後は、はんだの融点以下で、かつ熱硬化性が成立する温度と所定時間(例えば170℃、熱処理時間2時間)で、恒温槽内などで硬化される。   Then, as shown in FIG. 6 (3), a flip chip bonder is added to connect the connecting electrode 105 formed on the wiring substrate 104 so as to face the position of the protruding electrode 102 and the protruding electrode 102. A bump connecting semiconductor element in which an underfill material resin composition layer 103 attached by suction or the like is formed on a pressure tool head (bonder head) 106 is subjected to a solder ball melting temperature (for example, 230 to 250 ° C.). Then, the underfill material resin composition layer 103 is melted, and pressure 107 is applied by the pressure tool head 106 to realize electrical connection between the electrodes. As described above, the underfill material resin composition layer 103 is kept in a molten state at the time of connection processing, and after the connection, the temperature is equal to or lower than the melting point of the solder and the thermosetting property is established (for example, 170 ° C.). , And heat treatment time is 2 hours).

図7の工程断面図およびその拡大図によって、上記の方法の課題を説明する。図7(1)に示すように、通常、フリップチップボンダの加圧ツールヘッド106は、半導体素子101の背面全面を、一定の強度で加圧107する機構となっていることから、接続電極105全域と突起電極102全域とが、通常ほぼ同時に接触・加圧するようになる。図7(2)の要部拡大図に示すように、アンダーフィル材樹脂組成物層103は、改善された方法で形成された樹脂層によってでも、微小な凹凸を有した表面を持ち、これと、微小な突起ではあるが接続電極105を有する配線基板104の面とが密着する。このような密着開始状態から加熱・圧着すると、アンダーフィル材樹脂組成物層103が軟化するまでに、半導体素子101のアンダーフィル材樹脂組成物層表面と配線基板104の面との間に噛みこまれた空隙が、アンダーフィル材樹脂組成物を固化後に、観察状況としては配線基板104表面側においてボイド108として残るといった現象が生じる。   The subject of said method is demonstrated with the process sectional drawing and its enlarged view of FIG. As shown in FIG. 7A, the pressing tool head 106 of the flip chip bonder normally has a mechanism for pressing 107 the entire back surface of the semiconductor element 101 with a constant strength. The entire area and the entire area of the protruding electrode 102 are normally contacted and pressed almost simultaneously. As shown in the enlarged view of the main part of FIG. 7 (2), the underfill material resin composition layer 103 has a surface with minute irregularities even with the resin layer formed by the improved method. The surface of the wiring substrate 104 having the connection electrode 105 is in close contact with the fine protrusion. When heated and pressure-bonded from such an adhesion start state, the underfill material resin composition layer 103 is bitten between the surface of the underfill material resin composition layer of the semiconductor element 101 and the surface of the wiring substrate 104 until the underfill material resin composition layer 103 is softened. After the underfill material resin composition is solidified, a phenomenon in which the voids remain as voids 108 on the surface side of the wiring board 104 occurs as an observation situation.

なお、半導体素子101の突起電極の足元側においては、通常、ボイド発生はほとんど観察されない。このことは、フィルム状のアンダーフィル材樹脂組成物を突起電極102側に貼り付け、そして溶融してアンダーフィル材樹脂組成物層102の形成工程では、突起電極102と半導体素子101とで生じる可能性のある空隙を巻き込んでいないものと考えられる。   In addition, on the foot side of the protruding electrode of the semiconductor element 101, usually no void is observed. This may occur between the projecting electrode 102 and the semiconductor element 101 in the process of forming the underfill material resin composition layer 102 by pasting and melting the film-like underfill material resin composition on the projecting electrode 102 side. It is considered that no vacant space is involved.

こうしたボイド108の発生は、BGAなどとして製造された半導体装置において、チップなどの半導体素子と配線基板間の密着面積の低下、これによって、例えば接合強度の低下を引き起こすことや、例えばこの半導体装置を回路ボードなどに実装するとき、はんだ溶融温度近傍での製造工程がなされた場合、隣接バンプ(突起電極)間でショート不良が発生することなどを生じやすい。   The generation of the void 108 causes a decrease in the contact area between a semiconductor element such as a chip and a wiring board in a semiconductor device manufactured as a BGA or the like, thereby causing, for example, a decrease in bonding strength. When mounting on a circuit board or the like, if a manufacturing process is performed in the vicinity of the solder melting temperature, short-circuit defects are likely to occur between adjacent bumps (projection electrodes).

そこで、本発明の課題は、半導体素子の突起電極と配線基板の接続電極とを、半導体素子・配線基板間をアンダーフィル材樹脂組成物層で充填して接続する際に、樹脂層中でのボイドの発生を効果的に抑制できる半導体装置の製造装置および半導体装置の製造方法を提供することにある。   Therefore, the problem of the present invention is that when the bump electrode of the semiconductor element and the connection electrode of the wiring board are connected by filling the gap between the semiconductor element and the wiring board with the underfill material resin composition layer, An object of the present invention is to provide a semiconductor device manufacturing apparatus and a semiconductor device manufacturing method capable of effectively suppressing the generation of voids.

本発明の半導体装置の製造装置は、
半導体素子を配線基板にフリップチップ実装する半導体装置の製造装置であって、
前記半導体素子における突起電極が形成されていない背面に接触して、前記半導体素子側から前記配線基板側に対して加圧する加圧手段を有し、
前記加圧手段が、前記背面の一部の第1の領域を加圧する第1の加圧部と、前記第1領域と異なる第2の領域を加圧するとともに前記第1の加圧部と独立に制御可能な第2の加圧部とを備えることを特徴とする。
The semiconductor device manufacturing apparatus of the present invention comprises:
A semiconductor device manufacturing apparatus for flip-chip mounting a semiconductor element on a wiring board,
A pressing means for pressing the semiconductor element from the semiconductor element side against the wiring board side in contact with the back surface of the semiconductor element on which no protruding electrode is formed;
The pressurizing unit pressurizes a first pressurizing unit that presses a part of the first region on the back surface, and pressurizes a second region different from the first region, and is independent of the first pressurizing unit. And a second pressurizing part that can be controlled.

また、
前記第2の領域が前記第1の領域の周囲を囲む領域であることを特徴とする。
Also,
The second region is a region surrounding the first region.

また、
前記第1の加圧部の加圧強度が前記第2の加圧部の加圧強度よりも大きいことを特徴とする。
Also,
The pressurizing strength of the first pressurizing unit is larger than the pressurizing strength of the second pressurizing unit.

また、
前記第1の加圧部の圧力開始時間が前記第2の圧力開始時間よりも早い時期に印加されることを特徴とする。
Also,
The pressure start time of the first pressurizing unit is applied at a time earlier than the second pressure start time.

本発明の半導体装置の製造方法は、
半導体装置の製造装置を用いて、半導体素子を配線基板にフリップチップ実装する半導体装置の製造方法であって、
前記半導体装置の製造装置は、
前記半導体素子における突起電極が形成されていない背面に接触して、前記半導体素子側から前記配線基板側に対して加圧する加圧手段を有し、前記加圧手段が、前記背面の一部の第1の領域を加圧する第1の加圧部と、前記第1領域と異なる第2の領域を加圧するとともに前記第1の加圧部と独立に制御可能な第2の加圧部とを備える
ことを特徴とする。
A method for manufacturing a semiconductor device of the present invention includes:
A method for manufacturing a semiconductor device in which a semiconductor element is flip-chip mounted on a wiring board using a semiconductor device manufacturing apparatus,
The semiconductor device manufacturing apparatus comprises:
The semiconductor device has a pressurizing unit that contacts the back surface of the semiconductor element on which the protruding electrode is not formed and pressurizes the semiconductor substrate side against the wiring substrate side, and the pressurizing unit is a part of the back surface A first pressurizing unit that pressurizes the first region; and a second pressurizing unit that pressurizes a second region different from the first region and can be controlled independently of the first pressurizing unit. It is characterized by providing.

半導体素子の突起電極と配線基板の接続電極とを、半導体素子・配線基板間をアンダーフィル材樹脂組成物層で充填してフリップチップ接合する場合、特にそのアンダーフィル材樹脂組成物層としてフィルム状の膜を用いて形成するような場合においても、フリップチップボンダの加圧ツールヘッドを、複数の加圧領域に分割し、またそれらの加圧が、圧力や加圧タイミングなどのシーケンスが互いに独立して実施可能とすることにより、接合加工されたBGAなどの半導体装置のアンダーフィル樹脂層中におけるボイドの発生を、従来方法に比べて大幅に現象させことが可能となる。   When the bump electrode of the semiconductor element and the connection electrode of the wiring board are filled with the underfill material resin composition layer between the semiconductor element and the wiring board and are subjected to flip chip bonding, particularly as the underfill material resin composition layer Even when the film is formed using the above-mentioned film, the pressure tool head of the flip chip bonder is divided into a plurality of pressure regions, and the sequences of pressure and pressure timing are independent from each other. Therefore, the generation of voids in the underfill resin layer of a semiconductor device such as a bonded BGA can be caused to be greatly caused as compared with the conventional method.

これは、今後の半導体チップの面積増大化にともなう、アンダーフィル材樹脂組成物層中に発生するボイド増大傾向に歯止めをかける意味においても、大きな効果が期待できる。   This can be expected to have a great effect also in the sense of preventing the increase in voids generated in the underfill material resin composition layer as the area of the semiconductor chip increases in the future.

以下に、本発明の実施の形態を、添付図を参照しつつ説明する。   Embodiments of the present invention will be described below with reference to the accompanying drawings.

(実施例)
図1は、本実施形態の製造装置の要部の断面模式図を示したものである。図1(1)は、例えば、フリップチップボンダの加圧ツールヘッド6を、加圧する方向に沿って手前側から見た断面図であって、この図の紙面に対して垂直の方向に圧力が印加される。図1(2)は、図1(1)における加圧ツールヘッド6のX−X‘断面図であり、図1(1)の矢印Zで示した方向に圧力が印加される。本図に示した様に、加圧ツールヘッド6の加圧領域は、半導体素子1の背面(突起電極2が形成されていない側のフラットな面)とほぼ同等のサイズを有する。またその背面の中央部とそれを囲む外周部とは、独立して加圧強度と加圧タイミング(各加圧部の加圧順序や開始時期など)をそれぞれ独立して調整可能のように、中央領域加圧部6−1と、外周領域加圧部6−2とに分離された2領域構造となっている。
(Example)
FIG. 1 is a schematic cross-sectional view of the main part of the manufacturing apparatus of this embodiment. FIG. 1A is a cross-sectional view of the pressurizing tool head 6 of a flip chip bonder, for example, as seen from the front side along the pressurizing direction, and pressure is applied in a direction perpendicular to the paper surface of this figure. Applied. FIG. 1B is a cross-sectional view of the pressing tool head 6 taken along line XX ′ in FIG. 1A, and pressure is applied in the direction indicated by the arrow Z in FIG. As shown in this figure, the pressurizing region of the pressurizing tool head 6 has substantially the same size as the back surface of the semiconductor element 1 (the flat surface on the side where the protruding electrodes 2 are not formed). In addition, the central part of the back surface and the outer peripheral part surrounding it can be independently adjusted for the pressure intensity and the pressure timing (pressure order and start time of each pressure part, etc.) It has a two-region structure separated into a central region pressurizing unit 6-1 and an outer peripheral region pressurizing unit 6-2.

図1(2)に示すように、半導体素子1は加圧ツールヘッド6に、図示されない吸着機構などによって取り付けられる。半導体素子1の一方の面には複数の突起電極2が形成され、更に、その上から、例えば、フィルム状の熱硬化性のアンダーフィル材樹脂組成物が前記突起電極2を覆うように付着され、その後、加熱により固化したアンダーフィル材樹脂組成物層3が形成されている。それに対して、図示されないステージ上に配線基板4を配し、この配線基板4には突起電極2に対向するように複数の配線電極5が形成されている。図示されない、例えば電熱ヒーターなどの加熱手段を同時に使用可能な状況下、これら半導体素子と配線基板の配置構成において加圧ツールヘッド6の加圧によってフリップチップ接合を実施する。   As shown in FIG. 1B, the semiconductor element 1 is attached to the pressure tool head 6 by a suction mechanism (not shown). A plurality of protruding electrodes 2 are formed on one surface of the semiconductor element 1, and further, for example, a film-like thermosetting underfill material resin composition is attached thereon so as to cover the protruding electrodes 2. Then, the underfill material resin composition layer 3 solidified by heating is formed. On the other hand, a wiring board 4 is arranged on a stage (not shown), and a plurality of wiring electrodes 5 are formed on the wiring board 4 so as to face the protruding electrodes 2. In a situation where heating means such as an electric heater (not shown) can be used at the same time, flip chip bonding is performed by pressurizing the pressurizing tool head 6 in the arrangement configuration of these semiconductor elements and the wiring board.

以下に、本発明の方法を検証するために行った具体的な実験実施例について述べる。
(1)突起電極つき半導体チップ作製;
15mm×15mmのSiの評価用TEG(Test Element Group)チップからなる半導体チップ上に、直径100μm、高さ90μm、材料Sn−3Ag−0.5Cuの突起電極を、250μmピッチで、合計3,364個形成した。
(2)配線基板;
35mm×35mmの樹脂ビルドアップ基板のほぼ中央に、チップサイズ15mm×15mm範囲内で、Au−Ni−Cu層の100μmφの接続電極を、上記突起電極と対向する位置に、同様に250μmピッチで形成した。
(3)フィルム状アンダーフィル材樹脂組成物作製;
次のものを混合しアンダーフィル材料とした。
Hereinafter, specific experimental examples conducted for verifying the method of the present invention will be described.
(1) Production of semiconductor chip with protruding electrodes;
On a semiconductor chip made of a TEG (Test Element Group) chip for evaluation of 15 mm × 15 mm Si, bump electrodes with a diameter of 100 μm, a height of 90 μm, and a material Sn-3Ag-0.5Cu are arranged in a total of 3,364 at a pitch of 250 μm. Individually formed.
(2) Wiring board;
A connection electrode of 100 μmφ of Au—Ni—Cu layer is formed in the center of a 35 mm × 35 mm resin build-up substrate within a chip size of 15 mm × 15 mm in the same position at a pitch of 250 μm at the position facing the protruding electrode. did.
(3) Production of film-like underfill material resin composition;
The following were mixed to make an underfill material.

・主剤:ビスフェノールF型エポキシ(EXA830LVP・大日本インキ);
100重量
・硬化剤:フェノール系硬化剤(EP601・旭電化工業); 50重量
・硬化促進剤:脂肪族ポリアミン(BUR439・旭電化工業); 10重量
・シリカフィラー:球状シリカ(So−E5・アドマテックス); 30重量
・溶剤;エタノール
はじめに主剤を秤量し、シリカフィラーを秤量して加え、ロールミルにより混合した後、硬化剤および硬化促進剤のエタノール混合液を加え、回転式混練脱泡機を用いて、1500rpmで2分間混合した。
・ Main agent: Bisphenol F type epoxy (EXA830LVP, Dainippon Ink);
100 wt.-Curing agent: phenolic curing agent (EP601, Asahi Denka Kogyo); 50 wt.-Curing accelerator: aliphatic polyamine (BUR439, Asahi Denka Kogyo); 10 wt.-Silica filler: spherical silica (So-E5 Ad. 30 weight ・ Solvent; ethanol First weigh the main agent, weigh out and add silica filler, mix by roll mill, add ethanol mixture of curing agent and curing accelerator, and use rotary kneading defoamer And mixed for 2 minutes at 1500 rpm.

その後、塗工機(コントロールコータ)により、厚さ50μmのPETフィルム上に塗工厚120μmとなるように塗布し、50℃の恒温槽中で乾燥させ、フィルム状アンダーフィル材樹脂組成物を作製した。乾燥後の膜厚は、約100μmとなった。
(4)フィルム状アンダーフィル材樹脂組成物の突起電極つき半導体チップ上への密着;
作製したフィルム状アンダーフィル材樹脂組成物が形成されているPETフィルムをアルミ板の上に置き、その上に先に作製した突起電極つき半導体チップのバンプ面を下にして静置し、その上にシリコーンラバーを被せたのち真空プレス機で加圧する。その結果、フィルム状アンダーフィル材樹脂組成物はチップ側に密着し、次いでPETフィルムを剥がすことによって、樹脂組成物層がチップ側に移転する。
(5)フリップチップ接合;
上記アンダーフィル樹脂組成物層形成の半導体チップと接続電極形成の配線基板のフリップチップ接合を行った。ボンダで熱圧着接合後、所定の温度で樹脂硬化を行って、完成サンプルを得た。これをSAT(Scanning Acoustic Tomograph、超音波映像装置)を用いて、サンプル中のボイド発生数を観測した。
Then, it is applied on a PET film having a thickness of 50 μm by a coating machine (control coater) so as to have a coating thickness of 120 μm, and dried in a constant temperature bath at 50 ° C. to produce a film-like underfill material resin composition. did. The film thickness after drying was about 100 μm.
(4) Adhering the film-like underfill material resin composition onto the semiconductor chip with protruding electrodes;
Place the prepared PET film on which the film-like underfill material resin composition is formed on an aluminum plate, and let it stand with the bump surface of the previously produced semiconductor chip with bump electrodes facing down. After applying silicone rubber, pressurize with a vacuum press. As a result, the film-like underfill material resin composition adheres to the chip side, and then the PET film is peeled off, whereby the resin composition layer is transferred to the chip side.
(5) Flip chip bonding;
Flip chip bonding was performed between the semiconductor chip formed with the underfill resin composition layer and the wiring substrate formed with a connection electrode. After thermocompression bonding with a bonder, the resin was cured at a predetermined temperature to obtain a finished sample. The number of voids in the sample was observed using SAT (Scanning Acoustic Tomography, ultrasonic imaging apparatus).

使用したフリップチップボンダは、図1に示したように、加圧ツールヘッド6の加圧領域が中央領域加圧部6−1と外周領域加圧部6−2との分割構造をしており、最外周が、チップと同サイズの15mm×15mm、中央領域加圧部6−1は5mm×5mmで、その外周5mm幅が外周領域加圧部6−2である。   In the used flip chip bonder, as shown in FIG. 1, the pressurizing region of the pressurizing tool head 6 has a divided structure of a central region pressurizing unit 6-1 and an outer peripheral region pressurizing unit 6-2. The outermost circumference is 15 mm × 15 mm, which is the same size as the chip, the central area pressurizing part 6-1 is 5 mm × 5 mm, and the outer circumference 5 mm width is the outer peripheral area pressurizing part 6-2.

別途、比較例として、従来のボンダヘッド(加圧ツールヘッド)と同様な、単一加圧領域の非分割加圧ツールヘッドを用意して、同様の接合試料を用いてフリップチップ接合を行った。   Separately, as a comparative example, a non-split pressure tool head in a single pressure region similar to a conventional bonder head (pressure tool head) was prepared, and flip chip bonding was performed using the same bonded sample.

なお、上記のボンディングにおいては、ヘッド温度は、いずれの方式のヘッド使用の場合でも最大250℃であり、また接合後のアンダーフィル材樹脂組成物層の硬化のために、150℃、2時間の熱処理を行っている。
(6)接合実施結果;
単一加圧領域を有する非分割型加圧ツールヘッドを用いた比較例サンプルでは、ヘッドにおける加圧力として10kgで行った。その結果、一個の接合サンプルあたり、およそ13〜16個のボイド発生が観測された。発生ボイドのサイズは、直径約200μm前後から10数μm程度であった。
In the above bonding, the head temperature is a maximum of 250 ° C. when using any type of head, and 150 ° C. for 2 hours for curing the underfill material resin composition layer after bonding. Heat treatment is performed.
(6) Joining result;
In a comparative example sample using a non-split type pressure tool head having a single pressure region, the applied pressure in the head was 10 kg. As a result, approximately 13 to 16 voids were observed per one bonded sample. The size of the generated void was about 200 μm to about several tens of μm in diameter.

一方、本発明の分割型ヘッド方式では、先ず、ヘッドを下げて半導体素子と配線基板とを全面で接触させ、最初の加圧として、中央領域加圧部に10kg、外周領域加圧部に7kgに設定した。すなわち、この場合は、最初の加熱として中央領域の加圧値を周辺領域の加圧値より高くなるような設定として同時加圧を行った。その後、この状態のまま引き続き、外周領域加圧部を10kgまで加圧して接合を行った。その結果、この本発明の方式では、最大3個のボイド発生が確認された。すなわち、大きく6分の1以上低減できることが解った。また、ボイドのサイズは10数μm程度で比較的小径のものであった。   On the other hand, in the divided head system of the present invention, first, the head is lowered to bring the semiconductor element and the wiring board into contact with each other, and as the first pressurization, 10 kg is applied to the central area pressurization section and 7 kg is applied to the outer peripheral area pressurization section. Set to. That is, in this case, the simultaneous pressurization was performed as a setting such that the pressurization value in the central region is higher than the pressurization value in the peripheral region as the first heating. Thereafter, in this state, the outer peripheral area pressurizing part was pressurized to 10 kg and joined. As a result, in the method of the present invention, generation of a maximum of three voids was confirmed. In other words, it was found that it can be greatly reduced by more than 1/6. The size of the void was about a few tens of μm and a relatively small diameter.

また、本実施形態の分割型ヘッド方式を用いて上記とは異なる加圧シーケンスを行った。その状況を図2の断面模式図によって示す。   Further, a pressurizing sequence different from the above was performed using the divided head system of the present embodiment. The situation is shown by the schematic sectional view of FIG.

すなわち、図2(1)のように、先ず、加圧ツールヘッド6を下げて半導体素子1と配線基板4とを近づけた後に、図2(2)に示すように、中央領域加圧部6−1のみに10kgの加圧A行った。次いで、この中央領域を圧接した状態で、図2(3)に示すように、外周領域加圧部6−2に7kg、そして、10kgと加圧Bを増加して圧着した。つまりこの場合は、中央領域を先ず高い圧力で加圧して圧着した状態とし、次いで外周部を最初はそれより低い圧力で加圧し、そして高い圧力で加圧Bを行う。この様な加圧シーケンスによって、本発明の分割型ヘッドでの接合を行った結果は、先と同様に、発生ボイドサイズが小型で、また発生数が最大2個程度と従来方法と比較して大幅に減少することが解った。   That is, as shown in FIG. 2 (1), first, after the pressing tool head 6 is lowered to bring the semiconductor element 1 and the wiring board 4 close to each other, as shown in FIG. A pressure A of 10 kg was applied only to -1. Next, in a state where the central region is in pressure contact, as shown in FIG. 2 (3), 7 kg and 10 kg and pressurization B are increased and pressure-bonded to the outer peripheral region pressurizing unit 6-2. That is, in this case, the central region is first pressurized and pressure-bonded, then the outer peripheral portion is first pressurized at a lower pressure, and pressurization B is performed at a higher pressure. As a result of joining with the split-type head of the present invention by such a pressurizing sequence, the generated void size is small and the number of generated is about 2 at the maximum as compared with the conventional method. It was found that it decreased significantly.

以上のように、従来の一体型ヘッド方式に比べ、本実施形態の分割型ヘッド方式のほうがボイドの発生を大幅に減少させることができる。その理由としては、次のように考えられる。即ち、突起電極2を内在するアンダーフィル材樹脂組成物層3の面(微小な凹凸面を有する)と若干突起している配線電極5が表面に設けられた配線基板とが接する時点で、この両者間に微小な空隙7が巻き込まれる可能性が高く、このまま一体型ヘッドで圧着し、固化するとこれがボイド化して残存する。しかし、図2(1)のように中央領域の加圧値を大きくする、あるいは図2(2)のように、中央領域が先に接するように加圧(加圧A)をすると、中央領域に内在する空隙7が外周領域に押し出される。その後、更に図2(3)のように中央領域を接したまま外周領域への加圧Bを行うと、周辺部に内在するものも含めて空隙7が接着領域の外部に排除されるものと考えられる。   As described above, the generation of voids can be significantly reduced in the divided head system of the present embodiment compared to the conventional integrated head system. The reason is considered as follows. That is, at the time when the surface of the underfill material resin composition layer 3 having the protruding electrode 2 (having a minute uneven surface) comes into contact with the wiring substrate 5 on which the slightly protruding wiring electrode 5 is provided. There is a high possibility that a minute gap 7 is caught between the two, and when this is pressed and solidified with an integrated head as it is, it becomes voided and remains. However, if the pressurization value in the central area is increased as shown in FIG. 2 (1), or the pressurization (pressurization A) is performed so that the central area comes into contact first as shown in FIG. The void 7 existing inside is pushed out into the outer peripheral region. Thereafter, when the pressure B is applied to the outer peripheral region while keeping the central region in contact as shown in FIG. 2 (3), the gap 7 including the one existing in the peripheral portion is excluded from the outside of the bonding region. Conceivable.

上記は一例であり、半導体素子と配線基板とが接触時に巻き込まれる空隙が外部領域に排除され易くなるようにボンディングを行うためには、図1で示したヘッドの分割方法に限らないし、また上記のような加圧シーケンスに限らないことは言うまでもない
例えば、半導体素子と配線基板とが最初に接触する場所が両者の中心部であるとするならば、例えば、図3の分割型加圧ツールヘッド6の分割例(平面図)を示すような例を適用することができる。図3(1)は、これまで説明したような、加圧ツールヘッド6が、中心部に四角形状をもつ中央領域加圧部6−1と、外周部が一体となった外周領域加圧部6−2からなる例を示した。また図3(2)に示すように、加圧ツールヘッド6が縦に分割され、中心部8−1と側部8−2(左右2領域を同時の一体加圧領域としてもよい)とからなるように、計3分割としてもよい。あるいは、図3(3)のように、中心部に四角形状をもつ中央領域加圧部9−1に対して、その外周領域は分割され、当該外周領域を角部領域9−2(四隅を同時の一体加圧領域としてもよい)と側辺部9−3(四側辺部を同時の一体加圧領域としてもよい)として、計9分割としてもよい。その他、多様な分割形状と、加圧シーケンスを適用できる。
The above is an example, and bonding is not limited to the head dividing method shown in FIG. 1 in order to perform bonding so that a gap that is involved when the semiconductor element and the wiring board are brought into contact with each other is easily excluded to the external region. Needless to say, the pressure sequence is not limited to the above. For example, if the first contact point between the semiconductor element and the wiring board is the center of both, for example, the divided pressure tool head of FIG. An example showing six division examples (plan view) can be applied. FIG. 3 (1) shows a pressurizing tool head 6 as described so far, a central area pressurizing part 6-1 having a square shape in the center and an outer peripheral area pressurizing part in which the outer peripheral part is integrated. An example consisting of 6-2 was shown. Further, as shown in FIG. 3 (2), the pressing tool head 6 is vertically divided, and from the center portion 8-1 and the side portion 8-2 (the left and right two regions may be used as a simultaneous integrated pressing region). Thus, a total of three divisions may be used. Alternatively, as shown in FIG. 3 (3), the outer peripheral region is divided with respect to the central region pressurizing unit 9-1 having a quadrangular shape at the center, and the outer peripheral region is divided into the corner region 9-2 (the four corners). It may be divided into a total of nine divisions as a simultaneous integral pressurizing region) and a side portion 9-3 (four side portions may be a simultaneous integral pressurization region). In addition, various division shapes and pressure sequences can be applied.

また、図3(1)のような分割型加圧ツールヘッド6において、その加圧シーケンス初期の接触段階で、中央領域加圧部6−1が周辺領域加圧部6−2より配線基板4側に凸(中央部が出っ張っている)状態になるようにして、ツールヘッド6全体を下降させる。このようにして、先に中央部が加圧され、次いで外周部を含めて加圧されることで、中央部の空隙が外周部へと除外させることも可能となる。   Further, in the divided pressurizing tool head 6 as shown in FIG. 3A, the central region pressurizing unit 6-1 is connected to the wiring substrate 4 by the peripheral region pressurizing unit 6-2 at the initial contact stage of the pressurizing sequence. The tool head 6 as a whole is lowered so as to protrude toward the side (the central portion protrudes). In this way, the central portion is first pressurized, and then the pressure including the outer peripheral portion is pressed, so that the central portion can be excluded from the outer peripheral portion.

更に、半導体素子と配線基板とが最初に接触する場所が両者の中心部では無く、例えば、外縁端部からの接触であるとする。その場合は、その最初の外縁端部から反対側の端部に、いわばローラーをかける様に加圧領域を拡大していく。そして最後に全体を接触・圧着させていくことができるように、加圧ヘッドの分割と、加圧シーケンスを行えばよい。   Furthermore, it is assumed that the place where the semiconductor element and the wiring board first contact each other is not the central portion of the both, but, for example, the contact from the outer edge end portion. In that case, the pressure area is expanded so that a roller is applied from the first outer edge end to the opposite end. Finally, the pressure head is divided and the pressure sequence is performed so that the whole can be brought into contact and pressure contact.

加圧ツールヘッドに関しては、上記の加圧領域分割例や加圧シーケンスに限らないことは言うまでもない。重要なことは、加圧ツールヘッドの加圧領域を、複数の加圧領域に分割し、互いに独立に加圧制御可能とする点にある。   Needless to say, the pressurizing tool head is not limited to the above-described pressurization region division example and pressurization sequence. What is important is that the pressurization area of the pressurization tool head is divided into a plurality of pressurization areas so that pressurization can be controlled independently of each other.

このような加圧ツールヘッドの複数の分割領域に対する互い独立な加圧制御機構を実現する方法に関して、その例を図4の断面模式図によって示す。図4(1)において、強い加圧の中央領域加圧部6−1と弱い加圧の外周領域加圧部6−2に分割した加圧ツールヘッド6をそれぞれ異なる圧力で加圧するとき、単独の制御モータ加圧機構10に、バネレート大のバネ11−1を中央領域加圧部6−1にセットし、バネレート小のバネ11−2を外周領域加圧部6−2にセットする。ここで、図4(2)に示すように、制御モータ加圧機構10で加圧することのより、中央領域加圧部6−1は強い加圧が、外周領域加圧部6−2には弱い加圧が生じることとなり、各加圧領域での加圧力を調整して空隙7を排除した接合を実施することができる。   An example of such a method for realizing independent pressure control mechanisms for a plurality of divided regions of the pressure tool head is shown in the schematic cross-sectional view of FIG. In FIG. 4 (1), when the pressurizing tool head 6 divided into the central area pressurizing section 6-1 for strong pressurization and the outer peripheral area pressurizing section 6-2 for weak pressurization is pressed with different pressures, respectively. In the control motor pressurizing mechanism 10, a spring 11-1 having a large spring rate is set in the central region pressurizing unit 6-1, and a spring 11-2 having a small spring rate is set in the peripheral region pressurizing unit 6-2. Here, as shown in FIG. 4 (2), the central region pressurizing unit 6-1 applies a strong pressurization to the outer peripheral region pressurizing unit 6-2 by applying pressure by the control motor pressurizing mechanism 10. A weak pressurization occurs, and it is possible to perform the joining in which the voids 7 are eliminated by adjusting the pressurizing force in each pressurizing region.

勿論、図5の加圧構造の断面模式図に示すように、各加圧領域に独立した個別の加圧機構を設けても良い。図5(1)の示すように、分割領域6−1、6−2、6−3それぞれに、例えば、油圧機構、あるいはピエゾ素子などを用いた、領域別個別加圧機構12−1,12−2、12−3を接続し、図5(2)に示すように、領域別加圧機構12−1(中央領域)を他のものより加圧力を強めたものとして、空隙7を排除するように制御することができる。   Of course, as shown in the schematic cross-sectional view of the pressurization structure in FIG. 5, an independent pressurization mechanism may be provided in each pressurization region. As shown in FIG. 5 (1), the individual pressurization mechanisms 12-1, 12 for each region using, for example, a hydraulic mechanism or a piezoelectric element in each of the divided regions 6-1, 6-2, 6-3. -2 and 12-3 are connected, and, as shown in FIG. 5 (2), the pressurizing mechanism 12-1 (central region) according to the region is assumed to have a stronger pressure than the others, and the gap 7 is eliminated. Can be controlled.

以上のように、特にフリップチップ接合である、半導体素子の突起電極と配線基板の接続電極とを半導体素子・配線基板間をアンダーフィル材樹脂組成物層で充填して接続するに際して、そのアンダーフィル材樹脂組成物層がフィルム状の膜を用いて実施する場合においても、半導体製造装置であるフリップチップボンダの加圧ツールヘッドを、複数の加圧領域に分割し、またそれらの加圧が、圧力や加圧タイミングなどのシーケンスが互いに独立して実施可能とすることで、接合加工されたBGAなどの半導体装置のアンダーフィル樹脂層中でのボイドの発生が、従来方法に比べ、大幅に現象させことが可能となった。   As described above, in particular, when the bump electrode of the semiconductor element and the connection electrode of the wiring board, which are flip chip bonding, are connected by filling the semiconductor element / wiring board with the underfill material resin composition layer, the underfill is performed. Even when the material resin composition layer is implemented using a film-like film, the pressurizing tool head of the flip chip bonder which is a semiconductor manufacturing apparatus is divided into a plurality of pressurizing regions, and those pressurizing are performed. By enabling sequences such as pressure and pressurization timing to be performed independently of each other, the occurrence of voids in the underfill resin layer of bonded semiconductor devices such as BGA is a significant phenomenon compared to conventional methods. It became possible to let me.

また、今後の半導体チップ面積の増大化・微細化に伴って、BGA素子などのアンダーフィル樹脂中のボイド発生数の増加傾向への対処やボイド抑制の必要性はますます強くなると考えられるが、本発明になるこの半導体製造装置の適用により、これら要求に効果的に対応することが期待できる。   In addition, as the area of semiconductor chips increases and miniaturizes in the future, the need to deal with the increasing trend of void generation in underfill resins such as BGA elements and the suppression of voids will become stronger. By applying this semiconductor manufacturing apparatus according to the present invention, it can be expected that these requirements will be effectively met.

以上の実施例を含む実施の形態に関し、以下の付記を開示する。   The following additional notes are disclosed regarding the embodiments including the above examples.

(付記1)
半導体素子を配線基板にフリップチップ実装する半導体装置の製造装置であって、
前記半導体素子における突起電極が形成されていない背面に接触して、前記半導体素子側から前記配線基板側に対して加圧する加圧手段を有し、
前記加圧手段が、前記背面の一部の第1の領域を加圧する第1の加圧部と、前記第1領域と異なる第2の領域を加圧するとともに前記第1の加圧部と独立に制御可能な第2の加圧部とを備える
ことを特徴とする半導体装置の製造装置。
(Appendix 1)
A semiconductor device manufacturing apparatus for flip-chip mounting a semiconductor element on a wiring board,
A pressing means for pressing the semiconductor element from the semiconductor element side against the wiring board side in contact with the back surface of the semiconductor element on which no protruding electrode is formed;
The pressurizing unit pressurizes a first pressurizing unit that presses a part of the first region on the back surface, and pressurizes a second region different from the first region, and is independent of the first pressurizing unit. And a controllable second pressurizing unit. A semiconductor device manufacturing apparatus, comprising:

(付記2)
前記第2の領域が前記第1の領域の周囲を囲む領域であることを特徴とする付記1記載の半導体装置の製造装置。
(Appendix 2)
2. The semiconductor device manufacturing apparatus according to claim 1, wherein the second region is a region surrounding the first region.

(付記3)
前記第1の加圧部の加圧強度が前記第2の加圧部の加圧強度よりも大きいことを特徴とする付記1記載の半導体装置の製造装置。
(Appendix 3)
The apparatus for manufacturing a semiconductor device according to appendix 1, wherein the pressure intensity of the first pressure part is greater than the pressure intensity of the second pressure part.

(付記4)
前記第1の加圧部の圧力開始時間が前記第2の圧力開始時間よりも早い時期に印加されることを特徴とする付記2または3記載の半導体装置の製造装置。
(Appendix 4)
4. The semiconductor device manufacturing apparatus according to appendix 2 or 3, wherein the pressure start time of the first pressurizing unit is applied at a time earlier than the second pressure start time.

(付記5)
前記第1の加圧部の加圧面が前記第2の加圧部の加圧面よりも前記配線基板の面に対して凸であることを特徴とする付記2ないし4のいずれかに記載の半導体装置の製造装置。
(Appendix 5)
The semiconductor according to any one of appendices 2 to 4, wherein the pressurizing surface of the first pressurizing unit is more convex than the pressurizing surface of the second pressurizing unit with respect to the surface of the wiring board. Equipment manufacturing equipment.

(付記6)
前記半導体素子と前記配線基板間に熱硬化性のフィルム状アンダーフィル材樹脂組成物を用いて形成することを特徴とする付記1ないし5のいずれかに記載の半導体装置の製造装置。
(Appendix 6)
6. The semiconductor device manufacturing apparatus according to any one of appendices 1 to 5, wherein a thermosetting film-like underfill material resin composition is formed between the semiconductor element and the wiring board.

(付記7)
半導体装置の製造装置を用いて、半導体素子を配線基板にフリップチップ実装する半導体装置の製造方法であって、
前記半導体装置の製造装置は、
前記半導体素子における突起電極が形成されていない背面に接触して、前記半導体素子側から前記配線基板側に対して加圧する加圧手段を有し、前記加圧手段が、前記背面の一部の第1の領域を加圧する第1の加圧部と、前記第1領域と異なる第2の領域を加圧するとともに前記第1の加圧部と独立に制御可能な第2の加圧部とを備える
ことを特徴とする半導体装置の製造方法。
(Appendix 7)
A method for manufacturing a semiconductor device in which a semiconductor element is flip-chip mounted on a wiring board using a semiconductor device manufacturing apparatus,
The semiconductor device manufacturing apparatus comprises:
The semiconductor device has a pressurizing unit that contacts the back surface of the semiconductor element on which the protruding electrode is not formed and pressurizes the semiconductor substrate side against the wiring substrate side, and the pressurizing unit is a part of the back surface A first pressurizing unit that pressurizes the first region; and a second pressurizing unit that pressurizes a second region different from the first region and can be controlled independently of the first pressurizing unit. A method for manufacturing a semiconductor device, comprising:

本実施の形態に係る半導体装置の製造装置の加圧ツールヘッドを説明する図The figure explaining the pressurization tool head of the manufacturing apparatus of the semiconductor device concerning this embodiment 本実施の形態に係る半導体装置の製造装置の加圧接続工程を説明する図The figure explaining the pressurization connection process of the manufacturing apparatus of the semiconductor device which concerns on this Embodiment 本実施の形態に係る半導体装置の製造装置の異なる加圧ツールヘッドを説明する図The figure explaining the pressurization tool head from which the manufacturing apparatus of the semiconductor device which concerns on this Embodiment differs 本実施の形態に係る半導体装置の製造装置の加圧ツールヘッドの加圧機構を説明する図(その1)The figure explaining the pressurization mechanism of the pressurization tool head of the manufacturing apparatus of the semiconductor device concerning this embodiment (the 1) 本実施の形態に係る半導体装置の製造装置の加圧ツールヘッドの加圧機構を説明する図(その2)The figure explaining the pressurization mechanism of the pressurization tool head of the manufacturing apparatus of the semiconductor device concerning this embodiment (the 2) 従来の半導体装置の製造装置の加圧接続工程を説明する図The figure explaining the pressurization connection process of the manufacturing apparatus of the conventional semiconductor device 従来の半導体装置の製造装置の加圧接続工程の課題を説明する図The figure explaining the subject of the pressure connection process of the manufacturing device of the conventional semiconductor device

符号の説明Explanation of symbols

1、101 半導体素子
2、102 突起電極
3、103 アンダーフィル材樹脂組成物層
4、104 配線基板
5、105 接続電極
6、8、9、106 加圧ツールヘッド
7、108 空隙(ボイド)
10 制御モータ加圧機構
11 バネ
12 領域別個別加圧機構
107 加圧
DESCRIPTION OF SYMBOLS 1,101 Semiconductor element 2,102 Projection electrode 3,103 Underfill material resin composition layer 4,104 Wiring board 5,105 Connection electrode 6,8,9,106 Pressurization tool head 7,108 Air gap (void)
DESCRIPTION OF SYMBOLS 10 Control motor pressurization mechanism 11 Spring 12 Individual pressurization mechanism classified by area 107 Pressurization

Claims (4)

半導体素子を配線基板にフリップチップ実装する半導体装置の製造装置であって、
前記半導体素子における突起電極が形成されていない背面に接触して、前記半導体素子側から前記配線基板側に対して加圧する加圧手段を有し、
前記加圧手段は、前記背面の所定の外縁端部に平行に3分割された前記背面の領域内の前記所定の外縁端部を含む第1の領域を加圧する第1の加圧部と、中央部の第2の領域を加圧する第2の加圧部と、前記第1と前記第2の領域を除く第3の領域を加圧する第3の加圧部を備え、前記第1乃至前記第3の加圧部により前記半導体素子の背面を前記所定の外縁端部から相対する外縁端部に向かって加圧する
ことを特徴とする半導体装置の製造装置。
A semiconductor device manufacturing apparatus for flip-chip mounting a semiconductor element on a wiring board,
A pressing means for pressing the semiconductor element from the semiconductor element side against the wiring board side in contact with the back surface of the semiconductor element on which no protruding electrode is formed;
The pressurizing means includes a first pressurizing unit that pressurizes a first region including the predetermined outer edge end portion in the region of the back surface that is divided into three in parallel with a predetermined outer edge end portion of the back surface; A second pressurizing unit that pressurizes the second region in the center, and a third pressurizing unit that pressurizes the third region excluding the first and second regions, An apparatus for manufacturing a semiconductor device, wherein the third pressurizing unit pressurizes the back surface of the semiconductor element from the predetermined outer edge end portion toward the opposite outer edge end portion.
前記加圧手段は、前記第1の加圧部から前記第2の加圧部を経て前記第3の加圧部の順番、または前記第3の加圧部から前記第2の加圧部を経て前記第1の加圧部の順番に加圧し、加圧する前記背面の領域を拡大していく
ことを特徴とする請求項1記載の半導体装置の製造装置。
The pressurizing unit is configured to change the order of the third pressurizing unit from the first pressurizing unit through the second pressurizing unit, or the second pressurizing unit from the third pressurizing unit. 2. The semiconductor device manufacturing apparatus according to claim 1, wherein pressurization is performed in the order of the first pressurization unit, and the region of the back surface to be pressurized is enlarged.
半導体素子を配線基板にフリップチップ実装する半導体装置の製造装置であって、
前記半導体素子における突起電極が形成されていない背面に接触して、前記半導体素子側から前記配線基板側に対して加圧する加圧手段を有し、
前記加圧手段は、前記背面の中央部の領域を加圧する中央加圧部と、前記背面の中央部から前記背面のそれぞれの外縁端部まで延出する4つの領域を加圧する辺部加圧部と、前記背面の4つの角部の領域を加圧する角部加圧部とを備え、前記中央加圧部と前記辺部加圧部と前記角部加圧部とにより前記半導体素子の背面を所定の外縁端部から相対する外縁端部に向かって加圧する
ことを特徴とする半導体装置の製造装置。
A semiconductor device manufacturing apparatus for flip-chip mounting a semiconductor element on a wiring board,
A pressing means for pressing the semiconductor element from the semiconductor element side against the wiring board side in contact with the back surface of the semiconductor element on which no protruding electrode is formed;
The pressurizing means includes a central pressurizing unit that pressurizes a central region of the back surface, and a side pressurizing that pressurizes four regions extending from the central portion of the back surface to the respective outer edge ends of the back surface. And a corner pressurizing unit that pressurizes four corner regions of the back surface, and the back surface of the semiconductor element is formed by the central pressurizing portion, the side pressurizing portion, and the corner pressurizing portion. The semiconductor device manufacturing apparatus is characterized in that pressure is applied from a predetermined outer edge end portion toward an opposite outer edge end portion.
半導体素子を配線基板にフリップチップ実装する半導体装置の製造方法であって、
前記半導体素子における突起電極が形成されていない背面に接触して、前記背面の所定の外縁端部に平行に3分割された前記背面の領域の前記外縁端部を含む第1の領域を、前記半導体素子側から前記配線基板側に対して加圧する第1の加圧手順と、
前記背面に接触して、前記3分割された領域の内の中央部の第2の領域を前記半導体素子側から前記配線基板側に対して加圧する第2の加圧手順と、
前記背面に接触して、前記3分割された領域の内の前記第1と前記第2の領域を除いた領域を前記半導体素子側から前記配線基板側に対して加圧する第3の加圧手順とを有し、
前記第1乃至前記第3の加圧手順による加圧の順番を、前記第1の加圧手順から前記第2の加圧手順を経て前記第3の加圧手順、または前記第3の加圧手順から前記第2の加圧手順を経て前記第1の加圧手順とし、前記背面の加圧領域を拡大していく
ことを特徴とする半導体装置の製造方法。
A method of manufacturing a semiconductor device in which a semiconductor element is flip-chip mounted on a wiring board,
A first region including the outer edge end portion of the region of the back surface, which is divided into three in parallel with a predetermined outer edge end portion of the back surface, in contact with the back surface of the semiconductor element on which no protruding electrode is formed; A first pressurizing procedure for pressurizing the wiring board side from the semiconductor element side;
A second pressurizing procedure that contacts the back surface and pressurizes the second region at the center of the three divided regions from the semiconductor element side to the wiring substrate side;
A third pressurizing procedure for pressing the region excluding the first and second regions in the three divided regions from the semiconductor element side to the wiring board side in contact with the back surface It has a door,
The order of pressurization by the first to third pressurization procedures is changed from the first pressurization procedure to the third pressurization procedure through the second pressurization procedure, or the third pressurization procedure. A method of manufacturing a semiconductor device, wherein the first pressurizing procedure is changed from the procedure to the first pressurizing procedure, and the pressurizing region on the back surface is expanded .
JP2007329330A 2007-12-20 2007-12-20 Semiconductor device manufacturing apparatus and semiconductor device manufacturing method Expired - Fee Related JP5018455B2 (en)

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