JP2010153670A - Flip-chip mounting method and semiconductor device - Google Patents

Flip-chip mounting method and semiconductor device Download PDF

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JP2010153670A
JP2010153670A JP2008331662A JP2008331662A JP2010153670A JP 2010153670 A JP2010153670 A JP 2010153670A JP 2008331662 A JP2008331662 A JP 2008331662A JP 2008331662 A JP2008331662 A JP 2008331662A JP 2010153670 A JP2010153670 A JP 2010153670A
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semiconductor chip
resin
wiring board
flip
chip
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Yoshihiro Tomura
善広 戸村
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Panasonic Corp
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Panasonic Corp
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Priority to JP2008331662A priority Critical patent/JP2010153670A/en
Priority to US13/056,462 priority patent/US8895359B2/en
Priority to PCT/JP2009/005890 priority patent/WO2010070806A1/en
Priority to CN2009801208771A priority patent/CN102047404B/en
Publication of JP2010153670A publication Critical patent/JP2010153670A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/75—Apparatus for connecting with bump connectors or layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/0781—Adhesive characteristics other than chemical being an ohmic electrical conductor
    • H01L2924/07811—Extrinsic, i.e. with electrical conductive fillers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Wire Bonding (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a flip-chip mounting method that can form unevenness, in a stable shape at a part of a fillet, even when using an anisotropic conductive adhesive, and prevents water from entering an electrical connection part between a wiring substrate and a semiconductor chip, even in the usage environment of high temperature and high humidity. <P>SOLUTION: A surface of a projecting underfill resin 6 at a periphery of the semiconductor chip 1 is coated with a second resin 16b to form an uneven layer 16, and molding using a mold resin is carried out thereupon to form a container. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

本発明は、半導体装置のフリップチップ実装方法に関する。   The present invention relates to a flip chip mounting method for a semiconductor device.

近年、電子機器の小型化、薄型化の要求により、裸（ベア）の半導体チップを配線基板上に直接に実装（ベアチップ実装）した半導体装置が要求されている。特に、半導体チップの回路面を配線基板上に向き合わさるようにひっくり返して実装（フリップチップ実装）された半導体装置が要求されている。   In recent years, a semiconductor device in which a bare semiconductor chip is directly mounted on a wiring board (bare chip mounting) is required due to a demand for downsizing and thinning of electronic devices. In particular, there is a demand for a semiconductor device that is mounted by flipping so that the circuit surface of the semiconductor chip faces the wiring board (flip chip mounting).

従来、フリップチップタイプの半導体装置は、図１９に示すように配線基板５０に金属バンプ電極などの内部接続端子を備えた半導体チップ５１をフリップチップ接続により搭載することにより構成されている。５２は異方導電性接着剤である。   Conventionally, a flip chip type semiconductor device is configured by mounting a semiconductor chip 51 having internal connection terminals such as metal bump electrodes on a wiring board 50 by flip chip connection as shown in FIG. 52 is an anisotropic conductive adhesive.

この半導体装置では、外力が半導体チップ５１に作用した場合に、異方性導電接着剤５２が破損して、配線基板５０と半導体チップ５１との電気接続の不良が発生する。
そこで特許文献１には、図２０に示すように半導体チップ５１の外周からはみ出す異方性導電接着剤５２のフィレット部分に凹凸５３を形成することによって、異方性導電接着剤５２の機械的強度を向上させて配線基板５０と半導体チップ５１との電気接続の不良の発生を低減している。
特開２０００−２７７５６６号公報 In this semiconductor device, when an external force acts on the semiconductor chip 51, the anisotropic conductive adhesive 52 is damaged, and a poor electrical connection between the wiring substrate 50 and the semiconductor chip 51 occurs.
Therefore, in Patent Document 1, as shown in FIG. 20, the mechanical strength of the anisotropic conductive adhesive 52 is formed by forming irregularities 53 on the fillet portion of the anisotropic conductive adhesive 52 that protrudes from the outer periphery of the semiconductor chip 51. The occurrence of poor electrical connection between the wiring board 50 and the semiconductor chip 51 is reduced.
JP 2000-277666 A

特許文献１のフリップチップ実装方法は、異方性導電接着剤５２を加熱するプロセスをコントロールして前記凹凸５３を異方性導電接着剤５２のフィレット部分に形成しているため、凹凸形状が緩やかで、形状にばらつきがある。さらに、高温多湿の使用環境下では、配線基板５０と半導体チップ５１との電気接続個所に水分が侵入し易い信頼性の低いものである。   In the flip-chip mounting method of Patent Document 1, since the unevenness 53 is formed in the fillet portion of the anisotropic conductive adhesive 52 by controlling the process of heating the anisotropic conductive adhesive 52, the uneven shape is gentle. And there are variations in shape. Furthermore, in a high-temperature and high-humidity environment, moisture is liable to enter the electrical connection portion between the wiring board 50 and the semiconductor chip 51 and has low reliability.

本発明は安定した形状の凹凸を前記フィレットの部分に形成することができ、しかも機械的強度について従来よりも高信頼性の半導体装置を得ることができるフリップチップ実装方法を提供することを目的とする。   SUMMARY OF THE INVENTION An object of the present invention is to provide a flip chip mounting method capable of forming irregularities having a stable shape in the fillet portion and obtaining a semiconductor device having higher mechanical strength than conventional ones. To do.

また、本発明は安定した形状の凹凸を前記フィレットの部分に形成することができ、しかも機械的強度ならびに電気接続について従来よりも高信頼性の半導体装置を得ることができるフリップチップ実装方法を提供することを目的とする。   In addition, the present invention provides a flip chip mounting method capable of forming irregularities with a stable shape in the fillet portion and obtaining a semiconductor device with higher mechanical strength and electrical connection than before. The purpose is to do.

本発明のフリップチップ実装方法は、熱硬化性のアンダーフィル樹脂を半導体チップと配線基板の間に介在させて半導体チップを配線基板にフリップチップ実装するとともに、前記配線基板の上に前記半導体チップを覆う容器を接合するに際し、前記配線基板と前記半導体チップの間に熱硬化性のアンダーフィル樹脂を挟んで位置決め配設された前記半導体チップを圧着ツールで加圧加熱して前記半導体チップの周囲にはみ出したアンダーフィル樹脂の表面に、凹凸形成用の第２の樹脂を塗布して凹凸層を形成し、前記半導体チップを覆う前記容器の内面とアンダーフィル樹脂表面の前記凹凸層とを接合することを特徴とする。   In the flip chip mounting method of the present invention, a thermosetting underfill resin is interposed between a semiconductor chip and a wiring board to flip chip mount the semiconductor chip on the wiring board, and the semiconductor chip is placed on the wiring board. When bonding a covering container, the semiconductor chip positioned and disposed with a thermosetting underfill resin interposed between the wiring board and the semiconductor chip is pressurized and heated with a crimping tool around the semiconductor chip. A second resin for forming irregularities is applied to the surface of the protruding underfill resin to form an irregular layer, and the inner surface of the container covering the semiconductor chip and the irregular layer on the surface of the underfill resin are joined. It is characterized by.

好ましくは、前記第２の樹脂を、前記アンダーフィル樹脂の表面にメッシュ状、ひも状、パンチング形状の何れかに塗布する。また、前記第２の樹脂として導電性樹脂を使用する。   Preferably, the second resin is applied to the surface of the underfill resin in any one of a mesh shape, a string shape, and a punching shape. In addition, a conductive resin is used as the second resin.

また、本発明のフリップチップ実装方法は、熱硬化性のアンダーフィル樹脂を半導体チップと配線基板の間に介在させて半導体チップを配線基板にフリップチップ実装するとともに、前記配線基板の上に前記半導体チップを覆う容器を接合するに際し、前記配線基板と前記半導体チップの間に熱硬化性のアンダーフィル樹脂を挟んで位置決め配設された前記半導体チップを圧着ツールで加圧加熱して前記半導体チップの周囲にはみ出したアンダーフィル樹脂の表面に、表面に凹凸をした金属フィルムシートまたは樹脂フィルムシートを覆い被せて凹凸層を形成し、前記半導体チップを覆う前記容器の内面とアンダーフィル樹脂表面の前記凹凸層とを接合することを特徴とする。   Further, the flip chip mounting method of the present invention flip-chip mounts the semiconductor chip on the wiring board by interposing a thermosetting underfill resin between the semiconductor chip and the wiring board, and the semiconductor on the wiring board. When bonding a container covering the chip, the semiconductor chip positioned and disposed with a thermosetting underfill resin interposed between the wiring substrate and the semiconductor chip is pressurized and heated with a crimping tool. The surface of the underfill resin that protrudes to the periphery is covered with a metal film sheet or resin film sheet having an uneven surface to form an uneven layer, and the inner surface of the container covering the semiconductor chip and the unevenness of the surface of the underfill resin It is characterized by joining the layers.

本発明の半導体装置は、熱硬化性のアンダーフィル樹脂を半導体チップと配線基板の間に介在させて半導体チップを配線基板にフリップチップ実装するとともに、前記配線基板の上に前記半導体チップを覆う容器を接合した半導体装置であって、前記半導体チップの周囲にはみ出したアンダーフィル樹脂の表面と前記容器の間に、凹凸形成用の第２の樹脂を塗布して形成された凹凸層を有していることを特徴とする。   A semiconductor device according to the present invention is a container in which a thermosetting underfill resin is interposed between a semiconductor chip and a wiring board so that the semiconductor chip is flip-chip mounted on the wiring board and the semiconductor chip is covered on the wiring board. A semiconductor device having an uneven layer formed by applying a second resin for forming unevenness between the surface of the underfill resin that protrudes around the semiconductor chip and the container. It is characterized by being.

好ましくは、前記第２の樹脂が導電性樹脂で前記配線基板の電極に接続されていることを特徴とする。
また、本発明の半導体装置は、熱硬化性のアンダーフィル樹脂を半導体チップと配線基板の間に介在させて半導体チップを配線基板にフリップチップ実装するとともに、前記配線基板の上に前記半導体チップを覆う容器を接合した半導体装置であって、前記半導体チップの周囲にはみ出したアンダーフィル樹脂の表面と前記容器の間に、表面に凹凸をした金属フィルムシートまたは樹脂フィルムシートを覆い被せて形成された凹凸層を有していることを特徴とする。 Preferably, the second resin is a conductive resin and is connected to the electrode of the wiring board.
Further, the semiconductor device of the present invention flip-chip mounts the semiconductor chip on the wiring board by interposing a thermosetting underfill resin between the semiconductor chip and the wiring board, and the semiconductor chip is placed on the wiring board. A semiconductor device in which a covering container is joined, and is formed by covering a metal film sheet or a resin film sheet having an uneven surface between the surface of the underfill resin that protrudes around the semiconductor chip and the container. It has a concavo-convex layer.

好ましくは、前記金属フィルムシートまたは樹脂フィルムシートが導電性で前記配線基板の電極に接続されていることを特徴とする。   Preferably, the metal film sheet or the resin film sheet is conductive and connected to the electrode of the wiring board.

この構成によると、半導体チップの周囲にはみ出したアンダーフィル樹脂の表面に、凹凸形成用の第２の樹脂を塗布して凹凸層を形成し、前記半導体チップを覆う前記容器の内面とアンダーフィル樹脂表面の前記凹凸層とを接合するので、安定した形状の凹凸を前記フィレットの部分に形成することができ、しかも機械的強度の半導体装置を得ることができる。また、前記第２の樹脂が導電性樹脂で前記配線基板の電極に接続することによって、機械的だけでなく電気的にも信頼性の高い半導体装置を提供できる。   According to this configuration, the surface of the underfill resin that protrudes around the semiconductor chip is coated with the second resin for forming the unevenness to form the uneven layer, and the inner surface of the container covering the semiconductor chip and the underfill resin Since the uneven layer on the surface is bonded, it is possible to form uneven portions having a stable shape in the fillet portion, and to obtain a semiconductor device having mechanical strength. In addition, when the second resin is a conductive resin and is connected to the electrode of the wiring board, a semiconductor device having high reliability not only mechanically but also electrically can be provided.

以下、本発明の実施の形態を図１〜図１８に基づいて説明する。
図１〜図１４はフリップチップ実装の工程を示し、図１５が完成した半導体装置である。 Hereinafter, embodiments of the present invention will be described with reference to FIGS.
1 to 14 show a flip chip mounting process, and FIG. 15 shows the completed semiconductor device.

先ず、図１（ａ）（ｂ）に示す前工程を説明する。
図１（ａ）に示すように半導体チップ１の電極パッド２の上には、バンプ３が設けられている。半導体チップ１の厚みは０．１５〜０．２ｍｍを使用した。バンプ３は主に金、銅、パラジウム、ニッケル、錫、アルミニウム、半田等の少なくとも１種類から形成されている。このバンプ３は公知のワイヤーボンディング法によりスタッドバンプや引きちぎりバンプが形成されてもよいし、バンプ３を形成するためのワイヤーには微量元素を添加、含有してもよい。この場合のバンプ高さは約５０μｍ、台座径は５５μｍとした。バンプ３は公知のめっき法、印刷法により形成されてもよい。 First, the pre-process shown in FIGS. 1 (a) and 1 (b) will be described.
As shown in FIG. 1A, bumps 3 are provided on the electrode pads 2 of the semiconductor chip 1. The thickness of the semiconductor chip 1 was 0.15 to 0.2 mm. The bump 3 is mainly formed from at least one of gold, copper, palladium, nickel, tin, aluminum, solder and the like. The bump 3 may be formed with a stud bump or a tear bump by a known wire bonding method, and a trace element may be added to and contained in the wire for forming the bump 3. In this case, the bump height was about 50 μm and the base diameter was 55 μm. The bump 3 may be formed by a known plating method or printing method.

厚みが０．２〜０．４ｍｍの配線基板４は、ガラスエポキシ基板（アラミド基板、シリコン基板、シリコンインターポーザでもよい）で、上面には銅（ニッケル＋Ａｕメッキしてもよい）の端子電極５が形成されている。配線基板４と端子電極５の上には、半導体チップ１よりも必要に応じて若干大きな寸法にてカットされたアンダーフィル樹脂としての絶縁性樹脂６が貼り付けられている。ここでは、１８０℃で硬化するエポキシ樹脂を絶縁性樹脂６として用いた。   The wiring substrate 4 having a thickness of 0.2 to 0.4 mm is a glass epoxy substrate (which may be an aramid substrate, a silicon substrate, or a silicon interposer), and a terminal electrode 5 made of copper (may be nickel + Au plated) is provided on the upper surface. Is formed. On the wiring substrate 4 and the terminal electrode 5, an insulating resin 6 is attached as an underfill resin that is cut to a size slightly larger than that of the semiconductor chip 1 as necessary. Here, an epoxy resin cured at 180 ° C. was used as the insulating resin 6.

図１（ｂ）に示すように搭載ツール７で半導体チップ１を吸着し、半導体チップ１のバンプ３が各相対応する端子電極５の上に重なり合うように配線基板４の上に搭載される。この時点で、バンプ３は絶縁性樹脂６に突き刺さった状態である。一部のバンプ３は絶縁性樹脂６を貫通し、端子電極５に当たって変形している。位置決め荷重は、１バンプ当たり１０ｇ程度である。搭載ツール７は内蔵するヒータにより加熱してもよいが樹脂を１００％以上硬化させてはいけない。搭載ツール７は半導体チップ１を搭載した後に離脱させる。   As shown in FIG. 1B, the semiconductor chip 1 is sucked by the mounting tool 7 and mounted on the wiring substrate 4 so that the bumps 3 of the semiconductor chip 1 overlap the terminal electrodes 5 corresponding to the respective phases. At this time, the bump 3 is in a state of being pierced into the insulating resin 6. Some of the bumps 3 penetrate the insulating resin 6 and are deformed by hitting the terminal electrodes 5. The positioning load is about 10 g per bump. The mounting tool 7 may be heated by a built-in heater, but the resin should not be cured 100% or more. The mounting tool 7 is detached after mounting the semiconductor chip 1.

なお、絶縁性樹脂６は、配線基板４の上に粘着して貼り付けられるように、あらかじめ、５０〜８０℃程度の温度で配線基板４を加熱しておいてもよいし、貼り付け装置のツール（図示せず）が加熱されるようになっていてもよい。貼り付け荷重は、５〜１０ｋｇｆ／ｃｍ２程度である。 The insulating resin 6 may be heated in advance at a temperature of about 50 to 80 ° C. so that the insulating resin 6 can be adhered and pasted onto the wiring board 4. A tool (not shown) may be heated. The sticking load is about 5 to 10 kgf / cm 2 .

この絶縁性樹脂６の厚みは５０μｍのものを使用した。絶縁性樹脂６が保護用セパレータ（図示せず）と２層になっていれば、それを剥がす。絶縁性樹脂６の絶縁性樹脂は、例えば、エポキシ樹脂、フェノール樹脂、ポリイミド、また、絶縁性熱可塑性樹脂では、ポリフェニレンサルファイド（ＰＰＳ）、ポリカーボネイト、変性ポリフェニレンオキサイド（ＰＰＯ）、または、これら、絶縁性熱硬化性樹脂と絶縁性熱可塑性樹脂を混合したものなどが使用できる。無機フィラー量は５０ｗｔ％のものを使用した。フィラー量は半導体チップ１と配線基板４との熱膨張、反りにより発生する応力から決定する。また、吸湿リフロー試験や湿中バイアス試験等による耐湿密着性による信頼性で決定する。また、絶縁性樹脂６は、リフロー耐熱性（２６５℃１０秒間）を有することが好ましい。   The insulating resin 6 having a thickness of 50 μm was used. If the insulating resin 6 has two layers with a protective separator (not shown), it is peeled off. The insulating resin 6 may be, for example, an epoxy resin, a phenol resin, a polyimide, or an insulating thermoplastic resin such as polyphenylene sulfide (PPS), polycarbonate, modified polyphenylene oxide (PPO), or these insulating materials. A mixture of a thermosetting resin and an insulating thermoplastic resin can be used. The amount of inorganic filler used was 50 wt%. The amount of filler is determined from the stress generated by thermal expansion and warpage between the semiconductor chip 1 and the wiring substrate 4. Moreover, it determines with the reliability by moisture-resistant adhesion by a moisture absorption reflow test, a humidity bias test, etc. The insulating resin 6 preferably has reflow heat resistance (265 ° C. for 10 seconds).

次に後工程を説明する。
後工程では、図１（ｂ）の実装状態の半導体チップ１の上に図２（ｂ）（ｃ）に示す圧着ツール８を用いて、図６に示すようにフィルム１３を押し付けて絶縁性樹脂６のフィレットの成形が行われる。 Next, a post process is demonstrated.
In the subsequent process, the film 13 is pressed on the semiconductor chip 1 mounted in FIG. 1B using the crimping tool 8 shown in FIGS. 2B and 2C, and the insulating resin is pressed as shown in FIG. 6 fillets are formed.

圧着ツール８は、図２（ａ）（ｂ）に示すように押圧部９とこの押圧部９の下面にネジ１１によって交換自在に取り付けられた枠体１０とで構成されている。枠体１０の材質は、熱硬化性のエポキシ樹脂、フェノール樹脂や、ポリイミド、シリコーン、または、テフロン、さらに、ゴム系樹脂でもよく、これら、絶縁性熱硬化性樹脂と絶縁性熱可塑性樹脂を混合したものでも良い。   As shown in FIGS. 2A and 2B, the crimping tool 8 includes a pressing portion 9 and a frame body 10 attached to the lower surface of the pressing portion 9 by screws 11 so as to be exchangeable. The material of the frame 10 may be a thermosetting epoxy resin, a phenol resin, polyimide, silicone, Teflon, or a rubber-based resin. These are a mixture of an insulating thermosetting resin and an insulating thermoplastic resin. What you did is fine.

図３（ａ）に示すように圧着ツール８とステージ１５の間に、支持治具１２ａ，１２ｂの間にフィルム１３が架張した状態で設けられており、フィルム１３の下方位置のステージ１５の上に、図１（ｂ）の実装状態の半導体チップ１がセットされている。フィルム１３の大きさは縦横とも半導体チップ１よりも大きい。フィルム１３は、耐熱性（ＮＣＦ硬化温度）を有するフィルムが望ましい。フィルム１３の材質は、例えば、ポリイミド、ポリフェニレンサルファイド、フッ素樹脂、シリコーンゴム、これらの２層構造等の耐熱性熱可塑フィルムが好ましい。ここではフィルム１３の厚みは２０〜３０μｍ程度のものを使用した。フィルム１３の両面は、フラットで、特にパターンは形成されていない。   As shown in FIG. 3A, the film 13 is provided between the crimping tool 8 and the stage 15 in a state where the film 13 is stretched between the support jigs 12a and 12b. On top, the semiconductor chip 1 in the mounted state of FIG. 1B is set. The size of the film 13 is larger than the semiconductor chip 1 both vertically and horizontally. The film 13 is preferably a film having heat resistance (NCF curing temperature). The material of the film 13 is preferably a heat-resistant thermoplastic film such as polyimide, polyphenylene sulfide, fluororesin, silicone rubber, or a two-layer structure thereof. Here, the film 13 has a thickness of about 20 to 30 μm. Both surfaces of the film 13 are flat and no pattern is formed.

図４では、ステージ１５に向かって支持治具１２ａ，１２ｂを降下させて当接させ、支持治具１２ａ，１２ｂによるフィルム１３の保持を緩めて、フィルム１３が半導体チップ１のほぼ上部に配置され、かつ、半導体チップ１の周囲にはみ出て貼り付けられている絶縁性樹脂６のほぼ上部に配置される。   In FIG. 4, the support jigs 12 a and 12 b are lowered and brought into contact with the stage 15 to loosen the holding of the film 13 by the support jigs 12 a and 12 b, and the film 13 is disposed almost on the semiconductor chip 1. In addition, the insulating resin 6 is disposed almost at the top of the semiconductor chip 1 that sticks out of the periphery of the semiconductor chip 1.

図５では、ステージ１５に向かって圧着ツール８をさらに降下させて前記枠体１０を半導体チップ１の上に被せ、半導体チップ１の上面と絶縁性樹脂６のフィレットの部分を、フィルム１３を介して加熱しながら押圧する。   In FIG. 5, the crimping tool 8 is further lowered toward the stage 15 to cover the frame body 10 on the semiconductor chip 1, and the upper surface of the semiconductor chip 1 and the fillet portion of the insulating resin 6 are interposed via the film 13. Press while heating.

なお、フィルム１３は配線基板４もしくはステージ１５側から吸着等で絶縁性樹脂６の上部に誘導配置されてもよい。
次に図６に示すように、フィルム１３を介して圧着ツール８によって半導体チップ１を配線基板４に加熱しながら更に押圧するとともに、半導体チップ１からはみ出た絶縁性樹脂６にフィルム１３を介して枠体１０が押し当てられて加熱加圧する。 The film 13 may be guided and disposed on the insulating resin 6 by suction or the like from the wiring board 4 or the stage 15 side.
Next, as shown in FIG. 6, the semiconductor chip 1 is further pressed against the wiring board 4 while being heated by the crimping tool 8 through the film 13, and the insulating resin 6 protruding from the semiconductor chip 1 is interposed through the film 13. The frame 10 is pressed and heated and pressurized.

次に図７に示すように、圧着ツール８によって加圧をつづけ、半導体チップ１のバンプ３を除々に変形させながら、同時に、枠体１０もまたフィルム１３越しに半導体チップ１からはみ出ている絶縁性樹脂６を加圧し続ける。圧着ツール８で荷重を加えることによって、バンプ３のすべてが絶縁性樹脂６を突き破り、配線基板４の端子電極５に接触しながら変形していく。   Next, as shown in FIG. 7, the pressure is continuously applied by the crimping tool 8 to gradually deform the bumps 3 of the semiconductor chip 1, and at the same time, the frame 10 also protrudes from the semiconductor chip 1 through the film 13. Continue to pressurize the functional resin 6. By applying a load with the crimping tool 8, all of the bumps 3 break through the insulating resin 6 and are deformed while being in contact with the terminal electrodes 5 of the wiring board 4.

圧着ツール８で半導体チップ１のバンプ３の高さを所望の値にし、絶縁性樹脂６を硬化する。これによって、次に図８に示すように、半導体チップ１の端からはみ出ている絶縁性樹脂６にフィルム１３のフラットな表面形状１３ａが転写される。   The height of the bump 3 of the semiconductor chip 1 is set to a desired value with the crimping tool 8 and the insulating resin 6 is cured. Thereby, as shown in FIG. 8, the flat surface shape 13 a of the film 13 is transferred to the insulating resin 6 protruding from the end of the semiconductor chip 1.

このときのバンプ変形荷重は１バンプ当たり５０ｇ程度である。バンプ３のサイズによって荷重をコントロールするが、この場合、バンプ高さは２５μｍｔとした。また、必要に応じて、ステージ１５を加熱したり、冷却して、絶縁性樹脂６にかかる内圧をコントロールし、ボイドの発生を抑えてもよい。   The bump deformation load at this time is about 50 g per bump. The load is controlled according to the size of the bump 3. In this case, the bump height is set to 25 μmt. Further, if necessary, the stage 15 may be heated or cooled to control the internal pressure applied to the insulating resin 6 and suppress the generation of voids.

圧着ツール８および支持治具１２ａ，１２ｂを解除してフリップチップ実装体が得られる。
次に、図８の状態のフリップチップ実装体における絶縁性樹脂６のフィレット部分６ａに、図９（ａ）（ｂ）のようにして凹凸層１６を形成し硬化する。 The crimping tool 8 and the supporting jigs 12a and 12b are released to obtain a flip chip mounting body.
Next, as shown in FIGS. 9A and 9B, the uneven layer 16 is formed and cured on the fillet portion 6a of the insulating resin 6 in the flip chip mounting body in the state of FIG.

具体的には、半導体チップからはみ出したアンダーフィル樹脂のフィレット部分６ａの少なくとも一部に、図９（ａ）（ｂ）に示すように第２の樹脂１６ｂをディスペンス１６ａによってメッシュ状に塗布していく。第２の樹脂１６ｂはチクソ性の高い樹脂にすると液垂れせず、凹凸形状が崩れないため、モールド樹脂との密着力低下を防ぐことができる。第２の樹脂１６ｂは、７００Ｐａ・ｓのエポキシ樹脂を使用した。第２の樹脂１６ｂとして導電性樹脂を使用することもできる。   Specifically, a second resin 16b is applied to at least a part of the fillet portion 6a of the underfill resin protruding from the semiconductor chip in a mesh shape with the dispense 16a as shown in FIGS. 9 (a) and 9 (b). Go. When the second resin 16b is a resin having high thixotropy, the liquid does not drip and the uneven shape does not collapse, so that it is possible to prevent a decrease in adhesion with the mold resin. As the second resin 16b, an epoxy resin of 700 Pa · s was used. A conductive resin can also be used as the second resin 16b.

ここでは、半導体チップからはみ出したフィレット部分６ａにメッシュ状に塗布したが、波状でも、螺旋状でも、アンダーフィル樹脂とモールド樹脂との接着面積が大きくなり、接着強度が増加するのであれば、パターンの形状は問わない。   Here, the fillet portion 6a that protrudes from the semiconductor chip is applied in a mesh shape. However, if the adhesion area between the underfill resin and the mold resin is increased and the adhesion strength is increased, the pattern can be obtained. The shape of is not questioned.

フィレット部分６ａに凹凸層１６が形成されたフリップチップ実装体に対して、さらに、図１０〜図１４の工程で容器４０を形成する。
図１０では、図９のフリップチップ実装体を基板固定ステージ２７の所望位置に設置し、トランスファーモールド金型２６をフリップチップ実装体の上方から被せる。 The container 40 is further formed in the steps of FIGS. 10 to 14 on the flip chip mounting body in which the uneven layer 16 is formed on the fillet portion 6a.
In FIG. 10, the flip chip mounting body of FIG. 9 is placed at a desired position of the substrate fixing stage 27, and the transfer mold 26 is covered from above the flip chip mounting body.

次に図１１に示すように、モールド樹脂３０をトランスファーモールド金型２６のゲート２８の部分から圧力シリンダ２９で押しながら加熱注入する。
次に図１２に示すように、モールド樹脂３０でフリップチップ実装体の半導体チップ１と凹凸層１６を含めてキャビティ２６Ａに完全に充填される。 Next, as shown in FIG. 11, the mold resin 30 is heated and injected from the gate 28 portion of the transfer mold 26 while being pushed by the pressure cylinder 29.
Next, as shown in FIG. 12, the cavity 26 </ b> A is completely filled with the mold resin 30 including the semiconductor chip 1 of the flip chip mounting body and the concavo-convex layer 16.

次に図１３に示すように、圧力シリンダ２９を開放し、トランスファーモールド金型２６を解除して取り外す。
次に図１４に示すように、モールドされたフリップチップ実装体をダイシングテープ３２で固定し、ダイシング装置にセットし、ブレード４１で所望のサイズにカットして図１５に示した、モールドされた半導体装置３３が完成する。 Next, as shown in FIG. 13, the pressure cylinder 29 is opened, and the transfer mold 26 is released and removed.
Next, as shown in FIG. 14, the molded flip chip mounting body is fixed with a dicing tape 32, set in a dicing apparatus, cut into a desired size with a blade 41, and the molded semiconductor shown in FIG. The device 33 is completed.

なお、モールドされたフリップチップ実装体はレーザーによるダイシングでもよい。その場合は、実装体は基板吸着固定治具に固定される。
この実施の形態のフリップチップ実装方法によると、ばらつきのない均一な凹凸層１６を介して、アンダーフィルとモールド樹脂が入り込んで接合され、両者の接触面積が大きく、アンカー（投錨）効果によって容器４０との接着強度を高めることができる。 The molded flip chip mounting body may be laser dicing. In that case, the mounting body is fixed to the substrate suction fixing jig.
According to the flip chip mounting method of this embodiment, the underfill and the mold resin enter and are joined through the uniform uneven layer 16 having no variation, the contact area between the two is large, and the container 40 can be obtained by the anchor (throwing) effect. The adhesive strength can be increased.

また、絶縁性樹脂６はフィルム１３を介して圧着ツール８によって加圧成型硬化されるため、ボイドの発生も抑えることができる。容器４０を接合したことによって、高温多湿の使用環境下において、配線基板４と半導体チップ１との電気接続個所に水分が侵入しにくい信頼性の高いものである。   Further, since the insulating resin 6 is pressure-molded and cured by the pressure bonding tool 8 through the film 13, generation of voids can be suppressed. By joining the container 40, it is highly reliable that moisture does not easily enter the electrical connection portion between the wiring substrate 4 and the semiconductor chip 1 in a high-temperature and high-humidity environment.

また、絶縁性樹脂６の内部への吸湿が少ないためリフロー時に水分が加熱されて膨張することが少なく、容器４０と絶縁性樹脂６の界面が剥離したりすることが極めて少なく、半導体チップ１のバンプ３と端子電極５との間に作用する引っ張りの応力を小さくすることができ、電気接続の信頼性が向上する。   In addition, since moisture absorption into the insulating resin 6 is small, moisture is hardly heated and expanded during reflow, and the interface between the container 40 and the insulating resin 6 is hardly peeled off. The tensile stress acting between the bump 3 and the terminal electrode 5 can be reduced, and the reliability of electrical connection is improved.

なお、この実施の形態での圧着ツール８は、フィルム１３を介して半導体チップ１に熱を伝え、絶縁性樹脂６の硬化温度を１８０℃になるようにするため、２１０℃に設定した。   The crimping tool 8 in this embodiment was set to 210 ° C. in order to transmit heat to the semiconductor chip 1 through the film 13 so that the curing temperature of the insulating resin 6 was 180 ° C.

また、コンスタントヒートタイプを使用したが、セラミック高速昇温タイプのものを使用してもよい。
また、上記の例ではフィレット部に図９（ｂ）に示すように第２の樹脂１６ｂをメッシュ状に形成したが、これは図１６に示すように第２の樹脂１６ｂを縦方向に向かって所定間隔で滑り台状に塗布して凹凸層１６を形成しても同様である。第２の樹脂１６ｂの塗布の幅は均一であっても、上部に対して下部の幅が小さくなっていても良い。 In addition, although the constant heat type is used, a ceramic fast temperature rising type may be used.
Further, in the above example, the second resin 16b is formed in a mesh shape in the fillet portion as shown in FIG. 9B. However, as shown in FIG. The same applies when the concave-convex layer 16 is formed by applying a slide at predetermined intervals. The application width of the second resin 16b may be uniform, or the lower width may be smaller than the upper area.

また、上記の例ではフィレット部に第２の樹脂１６ｂをメッシュ状または滑り台状に形成したが、図１７に示すように第２の樹脂１６ｂを横方向に向かって環状に所定間隔で塗布して凹凸層１６を形成しても同様である。   Further, in the above example, the second resin 16b is formed in a mesh shape or a slide shape in the fillet portion. However, as shown in FIG. 17, the second resin 16b is applied annularly at predetermined intervals in the lateral direction. The same applies when the uneven layer 16 is formed.

また、上記の例ではフィレット部に第２の樹脂１６ｂをメッシュ状または滑り台状に形成したが、図１８に示すように第２の樹脂１６ｂを横斜め方向に向かって所定間隔で螺旋状に塗布して凹凸層１６を形成しても同様である。   In the above example, the second resin 16b is formed in a mesh shape or a slide shape in the fillet portion. However, as shown in FIG. 18, the second resin 16b is spirally applied at a predetermined interval in the horizontal oblique direction. The same applies to the formation of the concavo-convex layer 16.

上記の各実施の形態では、絶縁性樹脂６を使用したが、この絶縁性樹脂６に替えて異方性導電膜（ＡＣＦ）を用いてもよく、さらに異方性導電膜に含まれる導電粒子（図示せず）として、ニッケル粉に金メッキを施したものを用いることにより、端子電極５とバンプ３との間での接続抵抗値を低下せしめることができて良好な接続信頼性が得られる。さらに、導電粒子は樹脂ボールにニッケルや金メッキを施した粒子を使ってもよい。さらに、導電粒子は、半田等の微粒子を使用することによって、端子電極５とバンプ３との間での接触状態の接続から、合金状態の接続を得ることもでき、さらに接続信頼性を向上させることができる。   In each of the above embodiments, the insulating resin 6 is used. However, an anisotropic conductive film (ACF) may be used instead of the insulating resin 6, and conductive particles contained in the anisotropic conductive film. By using a nickel powder plated with gold as (not shown), the connection resistance value between the terminal electrode 5 and the bump 3 can be lowered, and good connection reliability can be obtained. Furthermore, the conductive particles may be particles obtained by applying nickel or gold plating to resin balls. Furthermore, the conductive particles can be obtained in an alloy state from the contact state connection between the terminal electrode 5 and the bump 3 by using fine particles such as solder, and further improve the connection reliability. be able to.

以上のように本発明のフリップチップ実装方法によれば、短リードタイムで生産性の高い、高信頼性の半導体装置を製造することができる。
上記の実施の形態では、ディスペンス塗布によって絶縁性樹脂６のフィレット部６ａに凹凸層１６を形成し、この上に容器４０を形成して容器４０と半導体チップ１との接着を機械的に信頼性を高めたが、ディスペンス塗布以外に、金属フィルムシートや樹脂フィルムシートを網状にネット加工したものを図７の半導体チップ１の上に予め覆い被せておいてから、この上に容器４０を形成することによって、アンダーフィル部のみに凹凸層１６を形成するのではなく、半導体チップ裏面にも凹凸層１６を形成することもできる。また、アンダーフィル部のみに凹凸層１６を形成する場合であれば、半導体チップ１の部分をくり抜いた金属フィルムシートや樹脂フィルムシートを図７の半導体チップ１の上に予め覆い被せておいてから、この上に容器４０を形成することによって実現できる。 As described above, according to the flip chip mounting method of the present invention, a highly reliable semiconductor device with a short lead time and high productivity can be manufactured.
In the above embodiment, the concave-convex layer 16 is formed on the fillet portion 6a of the insulating resin 6 by dispensing, and the container 40 is formed thereon to provide mechanically reliable adhesion between the container 40 and the semiconductor chip 1. However, in addition to dispensing, a metal film sheet or resin film sheet net-processed in a net shape is previously covered on the semiconductor chip 1 of FIG. 7, and then a container 40 is formed thereon. Accordingly, the uneven layer 16 can be formed not only on the underfill portion but also on the back surface of the semiconductor chip. Further, in the case where the uneven layer 16 is formed only on the underfill portion, a metal film sheet or a resin film sheet obtained by hollowing out the portion of the semiconductor chip 1 is previously covered on the semiconductor chip 1 of FIG. This can be realized by forming the container 40 thereon.

また、上記の各実施の形態において、第２の樹脂１６ｂとして導電性樹脂を使用した場合、半導体チップ１の上に覆い被せる金属フィルムシートや樹脂フィルムシートに導電性のものを使用した場合には、第２の樹脂１６ｂを配線基板４のグランドなどの基準電位に接続された端子電極５に接続してグランドと接続することによって、他の信号配線の電気的信号および電位を安定化させることができる。   In each of the above embodiments, when a conductive resin is used as the second resin 16b, a conductive film is used for the metal film sheet or resin film sheet that covers the semiconductor chip 1. By connecting the second resin 16b to the terminal electrode 5 connected to a reference potential such as the ground of the wiring substrate 4 and connecting it to the ground, the electrical signals and potentials of other signal wirings can be stabilized. it can.

第２の樹脂１６ｂの具体例としては、ダムフィルエポキシ樹脂、導電性接着剤を例に挙げることができる。また、半導体チップ１の上に覆い被せる金属フィルムシートや樹脂フィルムシートとしては、メッシュ状粘着型樹脂フィルムシート、メッシュ状粘着型金属フィルムシート、メッシュ型金属箔貼りプリプレグ基板、メッシュ状織布ガラエポクロス、ひも状ガラエポクロス、メッシュ状織布有機（アラミド）耐熱クロス、ひも状織布有機（アラミド）耐熱クロス、メッシュ状金属薄膜、マスクパターンエッチング状金属薄膜などを挙げることができる。   Specific examples of the second resin 16b include dam fill epoxy resin and conductive adhesive. The metal film sheet or resin film sheet that covers the semiconductor chip 1 includes a mesh-like adhesive resin film sheet, a mesh-like adhesive metal film sheet, a mesh-type metal foil-attached prepreg substrate, and a mesh-like woven cloth glass epoxy cloth. , String-like glass epoxy cloth, mesh-like woven organic (aramid) heat-resistant cloth, string-like woven organic (aramid) heat-resistant cloth, mesh-like metal thin film, mask pattern-etched metal thin film, and the like.

本発明は、配線基板に半導体チップがフリップチップ実装された小型薄型の半導体装置等の高性能化に寄与できる。   INDUSTRIAL APPLICABILITY The present invention can contribute to high performance of a small and thin semiconductor device in which a semiconductor chip is flip-chip mounted on a wiring board.

本発明の実施の形態のフリップチップ実装工程の断面図Sectional drawing of the flip chip mounting process of embodiment of this invention 同実施の形態のフリップチップ実装工程で使用する圧着ツール８の分解図と組み立て図と底面図Exploded view, assembly view and bottom view of the crimping tool 8 used in the flip chip mounting process of the embodiment 同実施の形態のフリップチップ実装工程の前工程の断面図Sectional drawing of the pre-process of the flip chip mounting process of the same embodiment 同実施の形態のフリップチップ実装工程の前工程の断面図Sectional drawing of the pre-process of the flip chip mounting process of the same embodiment 同実施の形態のフリップチップ実装工程の前工程の断面図Sectional drawing of the pre-process of the flip chip mounting process of the same embodiment 同実施の形態のフリップチップ実装工程の前工程の断面図Sectional drawing of the pre-process of the flip chip mounting process of the same embodiment 同実施の形態のフリップチップ実装工程の前工程の断面図Sectional drawing of the pre-process of the flip chip mounting process of the same embodiment 同実施の形態のフリップチップ実装工程の前工程の断面図Sectional drawing of the pre-process of the flip chip mounting process of the same embodiment 同実施の形態の前工程で形成された半導体チップのフィレット部に凹凸層１６を形成する工程の説明図Explanatory drawing of the process of forming the uneven | corrugated layer 16 in the fillet part of the semiconductor chip formed at the previous process of the embodiment 同実施の形態のフリップチップ実装工程の後工程の断面図Sectional drawing of the post process of the flip chip mounting process of the same embodiment 同実施の形態のフリップチップ実装工程の後工程の断面図Sectional drawing of the post process of the flip chip mounting process of the same embodiment 同実施の形態のフリップチップ実装工程の後工程の断面図Sectional drawing of the post process of the flip chip mounting process of the same embodiment 同実施の形態のフリップチップ実装工程の後工程の断面図Sectional drawing of the post process of the flip chip mounting process of the same embodiment 同実施の形態のフリップチップ実装工程の後工程の断面図Sectional drawing of the post process of the flip chip mounting process of the same embodiment 同実施の形態の完成した半導体装置の断面図Sectional view of the completed semiconductor device of the embodiment 第２の樹脂１６ｂを縦方向に向かって所定間隔で滑り台状に塗布して凹凸層１６を形成した場合の説明図Explanatory drawing at the time of forming the uneven | corrugated layer 16 by apply | coating 2nd resin 16b to a slide base shape at predetermined intervals toward the vertical direction. 第２の樹脂１６ｂを横方向に向かって環状に塗布して凹凸層１６を形成した場合の説明図Explanatory drawing at the time of apply | coating 2nd resin 16b cyclically | annularly toward a horizontal direction, and forming the uneven | corrugated layer 16 第２の樹脂１６ｂを横斜め方向に向かって所定間隔で螺旋状に塗布して凹凸層１６を形成した場合の説明図Explanatory drawing at the time of forming the uneven | corrugated layer 16 by apply | coating the 2nd resin 16b spirally at predetermined intervals toward the diagonal direction. 従来例のフリップチップ実装体の断面図Cross-sectional view of conventional flip chip mounting body 別の従来例のフリップチップ実装体の断面図Cross-sectional view of another conventional flip chip mounting body

符号の説明Explanation of symbols

１ 半導体チップ
２ 電極パッド
３ バンプ
４ 配線基板
５ 端子電極
６ 絶縁性樹脂
７ 搭載ツール
８ 圧着ツール
９ 押圧部
１０ 枠体
１１ 固定ネジ
１２ 支持治具
１３ フィルム
１５ ステージ
１６ 凹凸層
２６ トランスファーモールド金型
２６Ａ キャビティ
２８ ゲート
２９ 圧力シリンダ
３０ モールド樹脂
３２ ダイシングテープ
３３ 半導体装置
４０ 容器
４１ ブレード DESCRIPTION OF SYMBOLS 1 Semiconductor chip 2 Electrode pad 3 Bump 4 Wiring board 5 Terminal electrode 6 Insulating resin 7 Mounting tool 8 Crimping tool 9 Pressing part 10 Frame 11 Fixing screw 12 Support jig 13 Film 15 Stage 16 Concavity and convexity layer 26 Transfer mold die 26A Cavity 28 Gate 29 Pressure cylinder 30 Mold resin 32 Dicing tape 33 Semiconductor device 40 Container 41 Blade

Claims (8)

熱硬化性のアンダーフィル樹脂を半導体チップと配線基板の間に介在させて半導体チップを配線基板にフリップチップ実装するとともに、前記配線基板の上に前記半導体チップを覆う容器を接合するに際し、
前記配線基板と前記半導体チップの間に熱硬化性のアンダーフィル樹脂を挟んで位置決め配設された前記半導体チップを圧着ツールで加圧加熱して前記半導体チップの周囲にはみ出したアンダーフィル樹脂の表面に、凹凸形成用の第２の樹脂を塗布して凹凸層を形成し、
前記半導体チップを覆う前記容器の内面とアンダーフィル樹脂表面の前記凹凸層とを接合する
フリップチップ実装方法。 When the thermosetting underfill resin is interposed between the semiconductor chip and the wiring board to flip-chip mount the semiconductor chip on the wiring board, and when the container covering the semiconductor chip is joined to the wiring board,
The surface of the underfill resin that protrudes around the semiconductor chip by pressurizing and heating the semiconductor chip positioned and sandwiched between the wiring board and the semiconductor chip with a crimping tool. To form a concavo-convex layer by applying a second resin for forming the concavo-convex,
A flip chip mounting method in which an inner surface of the container covering the semiconductor chip and the uneven layer on the surface of an underfill resin are joined. 前記第２の樹脂を、前記アンダーフィル樹脂の表面にメッシュ状、ひも状、パンチング形状の何れかに塗布する
請求項１記載のフリップチップ実装方法。 The flip chip mounting method according to claim 1, wherein the second resin is applied to the surface of the underfill resin in any one of a mesh shape, a string shape, and a punching shape. 前記第２の樹脂として導電性樹脂を使用する
請求項１記載のフリップチップ実装方法。 The flip chip mounting method according to claim 1, wherein a conductive resin is used as the second resin. 熱硬化性のアンダーフィル樹脂を半導体チップと配線基板の間に介在させて半導体チップを配線基板にフリップチップ実装するとともに、前記配線基板の上に前記半導体チップを覆う容器を接合するに際し、
前記配線基板と前記半導体チップの間に熱硬化性のアンダーフィル樹脂を挟んで位置決め配設された前記半導体チップを圧着ツールで加圧加熱して前記半導体チップの周囲にはみ出したアンダーフィル樹脂の表面に、表面に凹凸をした金属フィルムシートまたは樹脂フィルムシートを覆い被せて凹凸層を形成し、
前記半導体チップを覆う前記容器の内面とアンダーフィル樹脂表面の前記凹凸層とを接合する
フリップチップ実装方法。 When the thermosetting underfill resin is interposed between the semiconductor chip and the wiring board to flip-chip mount the semiconductor chip on the wiring board, and when the container covering the semiconductor chip is joined to the wiring board,
The surface of the underfill resin that protrudes around the semiconductor chip by pressurizing and heating the semiconductor chip positioned and sandwiched between the wiring board and the semiconductor chip with a crimping tool. In addition, an uneven layer is formed by covering a metal film sheet or resin film sheet having an uneven surface,
A flip chip mounting method in which an inner surface of the container covering the semiconductor chip and the uneven layer on the surface of an underfill resin are joined. 熱硬化性のアンダーフィル樹脂を半導体チップと配線基板の間に介在させて半導体チップを配線基板にフリップチップ実装するとともに、前記配線基板の上に前記半導体チップを覆う容器を接合した半導体装置であって、
前記半導体チップの周囲にはみ出したアンダーフィル樹脂の表面と前記容器の間に、凹凸形成用の第２の樹脂を塗布して形成された凹凸層を有している
半導体装置。 A semiconductor device in which a thermosetting underfill resin is interposed between a semiconductor chip and a wiring board, the semiconductor chip is flip-chip mounted on the wiring board, and a container covering the semiconductor chip is bonded onto the wiring board. And
A semiconductor device having an uneven layer formed by applying a second resin for forming unevenness between the surface of the underfill resin that protrudes around the semiconductor chip and the container. 前記第２の樹脂が導電性樹脂で前記配線基板の端子電極に接続されている
請求項５記載の半導体装置。 The semiconductor device according to claim 5, wherein the second resin is a conductive resin and is connected to a terminal electrode of the wiring board. 熱硬化性のアンダーフィル樹脂を半導体チップと配線基板の間に介在させて半導体チップを配線基板にフリップチップ実装するとともに、前記配線基板の上に前記半導体チップを覆う容器を接合した半導体装置であって、
前記半導体チップの周囲にはみ出したアンダーフィル樹脂の表面と前記容器の間に、表面に凹凸をした金属フィルムシートまたは樹脂フィルムシートを覆い被せて形成された凹凸層を有している
半導体装置。 A semiconductor device in which a thermosetting underfill resin is interposed between a semiconductor chip and a wiring board, the semiconductor chip is flip-chip mounted on the wiring board, and a container covering the semiconductor chip is bonded onto the wiring board. And
A semiconductor device having an uneven layer formed by covering a surface of an underfill resin protruding around the semiconductor chip and the container with a metal film sheet or resin film sheet having an uneven surface. 前記金属フィルムシートまたは樹脂フィルムシートが導電性で前記配線基板の端子電極に接続されている
請求項７記載の半導体装置。 The semiconductor device according to claim 7, wherein the metal film sheet or the resin film sheet is conductive and connected to a terminal electrode of the wiring board.
JP2008331662A 2008-12-16 2008-12-26 Flip-chip mounting method and semiconductor device Pending JP2010153670A (en)

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PCT/JP2009/005890 WO2010070806A1 (en) 2008-12-16 2009-11-06 Semiconductor device, flip-chip mounting method and flip-chip mounting apparatus
CN2009801208771A CN102047404B (en) 2008-12-16 2009-11-06 Semiconductor device, flip-chip mounting method and flip-chip mounting apparatus

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JP2013062472A (en) * 2011-09-15 2013-04-04 Toppan Printing Co Ltd Semiconductor package and manufacturing method of the same
JP2016527718A (en) * 2013-07-16 2016-09-08 シンガポール科学技術研究庁Ａｇｅｎｃｙ ｆｏｒ Ｓｃｉｅｎｃｅ， Ｔｅｃｈｎｏｌｏｇｙ ａｎｄ Ｒｅｓｅａｒｃｈ Method and apparatus for integrating chips on a wafer
US20210233887A1 (en) * 2017-06-16 2021-07-29 Micron Technology, Inc. Thermocompression bond tips and related apparatus and methods

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013062472A (en) * 2011-09-15 2013-04-04 Toppan Printing Co Ltd Semiconductor package and manufacturing method of the same
JP2016527718A (en) * 2013-07-16 2016-09-08 シンガポール科学技術研究庁Ａｇｅｎｃｙ ｆｏｒ Ｓｃｉｅｎｃｅ， Ｔｅｃｈｎｏｌｏｇｙ ａｎｄ Ｒｅｓｅａｒｃｈ Method and apparatus for integrating chips on a wafer
US20210233887A1 (en) * 2017-06-16 2021-07-29 Micron Technology, Inc. Thermocompression bond tips and related apparatus and methods
US11705425B2 (en) * 2017-06-16 2023-07-18 Micron Technology, Inc. Thermocompression bond tips and related apparatus and methods

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