JP5845855B2 - Semiconductor device and manufacturing method of semiconductor device - Google Patents

Semiconductor device and manufacturing method of semiconductor device Download PDF

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JP5845855B2
JP5845855B2 JP2011261348A JP2011261348A JP5845855B2 JP 5845855 B2 JP5845855 B2 JP 5845855B2 JP 2011261348 A JP2011261348 A JP 2011261348A JP 2011261348 A JP2011261348 A JP 2011261348A JP 5845855 B2 JP5845855 B2 JP 5845855B2
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support substrate
substrate
recess
semiconductor
adhesive
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JP2013115290A (en
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孝行 乗松
孝行 乗松
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Socionext Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/15321—Connection portion the connection portion being formed on the die mounting surface of the substrate being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip

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Description

本発明は、半導体装置及び半導体装置の製造方法に関する。   The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

電子機器の薄型化が進むとともに、電子機器に搭載される半導体パッケージの薄型化が要求されており、半導体チップの薄化技術の開発が行われている。半導体パッケージは、支持基板の上に半導体チップを搭載し、半導体チップを樹脂によって封止したものである。複数の半導体パッケージを積層するＰｏＰ（パッケージオンパッケージ）構造においては、上層の半導体パッケージと下層の半導体パッケージとを接続する端子のファインピッチ化によって、上下層の半導体パッケージ間の間隙は狭くなっている。ＰｏＰ構造においても、下層の半導体パッケージが有する半導体チップの薄型化を行うことが求められている。   As electronic devices become thinner, there is a demand for thinner semiconductor packages mounted on electronic devices, and development of thinning technology for semiconductor chips is underway. A semiconductor package has a semiconductor chip mounted on a support substrate and the semiconductor chip is sealed with resin. In a PoP (package on package) structure in which a plurality of semiconductor packages are stacked, the gap between the upper and lower semiconductor packages is narrowed by the fine pitch of the terminals connecting the upper semiconductor package and the lower semiconductor package. . Even in the PoP structure, it is required to reduce the thickness of a semiconductor chip included in a lower semiconductor package.

実開２００４−２８１９２０号公報Japanese Utility Model Publication No. 2004-281920 特開２００９−３０２２１２号公報JP 2009-302212 A

半導体チップの薄型化を行うことで、搬送や実装による半導体チップの破壊、電気特性の劣化等の様々な問題が発生する可能性がある。そのため、半導体チップの薄型化を行わずに、半導体装置の薄型化が求められている。本件は、半導体装置を薄型化する技術を提供することを目的とする。   By reducing the thickness of the semiconductor chip, various problems such as destruction of the semiconductor chip due to transportation and mounting, and deterioration of electrical characteristics may occur. Therefore, there is a demand for thinning of the semiconductor device without reducing the thickness of the semiconductor chip. The object of the present invention is to provide a technique for thinning a semiconductor device.

本件の一観点による半導体装置は、基板と、前記基板の上面に設けられた半導体素子と、前記基板の上面に設けられた接着剤と、を備え、前記基板の上面に、前記半導体素子の少なくとも一部を収容する凹部が形成され、前記接着剤は、前記基板と前記半導体素子との間に設けられているとともに、前記基板の凹部を覆っている。   A semiconductor device according to an aspect of the present invention includes a substrate, a semiconductor element provided on an upper surface of the substrate, and an adhesive provided on the upper surface of the substrate, and the upper surface of the substrate includes at least the semiconductor element. A recess for accommodating a part is formed, and the adhesive is provided between the substrate and the semiconductor element and covers the recess of the substrate.

本件によれば、半導体装置を薄型化することが可能となる。   According to this case, the semiconductor device can be thinned.

図１Ａは、本実施形態に係る半導体装置１の断面図である。FIG. 1A is a cross-sectional view of the semiconductor device 1 according to the present embodiment. 図１Ｂは、本実施形態に係る半導体装置１の断面図である。FIG. 1B is a cross-sectional view of the semiconductor device 1 according to the present embodiment. 図２Ａは、半導体装置１の要部拡大断面図である。FIG. 2A is an enlarged cross-sectional view of a main part of the semiconductor device 1. 図２Ｂは、支持基板１１に凹部１３を形成していない場合の半導体装置１Ａの要部拡大断面図である。FIG. 2B is an enlarged cross-sectional view of a main part of the semiconductor device 1 </ b> A when the concave portion 13 is not formed on the support substrate 11. 図３は、半導体装置１と半導体装置１Ａとを、薄型の電子機器１００に実装した場合の電子機器１００の断面図である。FIG. 3 is a cross-sectional view of the electronic device 100 when the semiconductor device 1 and the semiconductor device 1 </ b> A are mounted on the thin electronic device 100. 図４は、支持基板１１の上面に接着剤１４を形成した場合の半導体装置１の製造工程図である。FIG. 4 is a manufacturing process diagram of the semiconductor device 1 when the adhesive 14 is formed on the upper surface of the support substrate 11. 図５は、フリップチップボンダーのステージ３１の上に支持基板１１を設置した場合の半導体装置１の製造工程図である。FIG. 5 is a manufacturing process diagram of the semiconductor device 1 when the support substrate 11 is installed on the stage 31 of the flip chip bonder. 図６は、支持基板１１の上方に半導体チップ２１を配置した場合の半導体装置１の製造工程図である。FIG. 6 is a manufacturing process diagram of the semiconductor device 1 when the semiconductor chip 21 is arranged above the support substrate 11. 図７は、支持基板１１の中央部分をフリップチップボンダーのステージ３１の凹部３２に押し込んだ場合の半導体装置１の製造工程図である。FIG. 7 is a manufacturing process diagram of the semiconductor device 1 when the central portion of the support substrate 11 is pushed into the recess 32 of the stage 31 of the flip chip bonder. 図８は、支持基板１１の中央部分をフリップチップボンダーのステージ３１の凹部３２に押し込んだ場合の半導体装置１の製造工程図である。FIG. 8 is a manufacturing process diagram of the semiconductor device 1 when the central portion of the support substrate 11 is pushed into the recess 32 of the stage 31 of the flip chip bonder. 図９Ａは、接着剤１４の量が少ない場合の支持基板１１の断面図である。FIG. 9A is a cross-sectional view of the support substrate 11 when the amount of the adhesive 14 is small. 図９Ｂは、接着剤１４が、支持基板１１に形成された凹部１３を覆っていない場合の支持基板１１の断面図である。FIG. 9B is a cross-sectional view of the support substrate 11 when the adhesive 14 does not cover the recess 13 formed in the support substrate 11. 図９Ｃは、支持基板１１がフラットな状態に戻った場合の支持基板１１の断面図である。FIG. 9C is a cross-sectional view of the support substrate 11 when the support substrate 11 returns to a flat state. 図１０は、支持基板１１の下面に複数の半田ボール１５を搭載した場合の半導体装置１の製造工程図である。FIG. 10 is a manufacturing process diagram of the semiconductor device 1 when a plurality of solder balls 15 are mounted on the lower surface of the support substrate 11. 図１１は、ＰｏＰ（パッケージオンパッケージ）構造を有する半導体装置１の断面図である。FIG. 11 is a cross-sectional view of the semiconductor device 1 having a PoP (package on package) structure. 図１２は、凹部１３が形成されていない支持基板１１を有する半導体パッケージ６１に対して、半導体パッケージ５１を実装した場合の半導体装置１Ａの断面図である。FIG. 12 is a cross-sectional view of the semiconductor device 1 </ b> A when the semiconductor package 51 is mounted on the semiconductor package 61 having the support substrate 11 in which the recess 13 is not formed.

以下、図面を参照して、発明を実施するための形態（以下、実施形態という）に係る半導体装置について説明する。以下の構成は例示であり、本実施形態は以下の構成に限定されない。   Hereinafter, a semiconductor device according to a mode for carrying out the invention (hereinafter referred to as an embodiment) will be described with reference to the drawings. The following configuration is an example, and the present embodiment is not limited to the following configuration.

本実施形態に係る半導体装置１の断面図を図１Ａに示す。図１Ａに示すように、半導体装置１は、支持基板１１及び半導体チップ２１を有している。支持基板１１の上面（主面）に、半導体チップ（半導体集積回路チップ）２１が設置されている。半導体チップ２１は、半導体素子の一例である。半導体チップ２１は、例えば、フリップチップ（フェイスダウン）方式により支持基板１１の上面に実装される。半導体チップ２１は、支持基板１１の上面の中央部分に設置されてもよい。   A sectional view of the semiconductor device 1 according to the present embodiment is shown in FIG. 1A. As illustrated in FIG. 1A, the semiconductor device 1 includes a support substrate 11 and a semiconductor chip 21. A semiconductor chip (semiconductor integrated circuit chip) 21 is installed on the upper surface (main surface) of the support substrate 11. The semiconductor chip 21 is an example of a semiconductor element. The semiconductor chip 21 is mounted on the upper surface of the support substrate 11 by, for example, a flip chip (face down) method. The semiconductor chip 21 may be installed in the central portion of the upper surface of the support substrate 11.

支持基板１１は、配線基板、インターポーザ又は回路基板とも称される。支持基板１１は、例えば、ビルドアップ基板、多層基板、フレキシブル基板等の有機基板である。有機基板は、例えば、ガラスエポキシ樹脂、ガラス−ＢＴ（ビスマレイミドトリアジン）及びポリイミド等を基材としてもよい。   The support substrate 11 is also referred to as a wiring board, an interposer, or a circuit board. The support substrate 11 is, for example, an organic substrate such as a build-up substrate, a multilayer substrate, or a flexible substrate. The organic substrate may use, for example, glass epoxy resin, glass-BT (bismaleimide triazine), polyimide, or the like as a base material.

支持基板１１の上面には、複数のパッド電極１２が形成されている。パッド電極１２は、例えば、銅（Ｃｕ）等の金属である。支持基板１１の上面には、パッド電極１２が形成されている箇所を除いて、ソルダーレジスト（図示せず）が形成されている。半導体チップ２１の上面（主面）には、複数のパッド電極２２が形成されている。パッド電極２２は、銅（Ｃｕ）等の金属である。半導体チップ２１の上面は、パッド電極２２が形成された面（電極形成面）である。半導体チップ２１の上面には、複数のバンプ（突起電極）２３が設けられている。バンプ２３は、例えば、金バンプ、半田バンプ、銅バンプ、又は、半田及び銅を含むバンプである。バンプ２３は、半導体チップ２１のパッド電極２２に接続されているとともに、支持基板１１のパッド電極１２に接続されている。したがって、バンプ２３を介して、支持基板１１と半導体チップ２１とが電気的に接続されている。   A plurality of pad electrodes 12 are formed on the upper surface of the support substrate 11. The pad electrode 12 is, for example, a metal such as copper (Cu). A solder resist (not shown) is formed on the upper surface of the support substrate 11 except for a portion where the pad electrode 12 is formed. A plurality of pad electrodes 22 are formed on the upper surface (main surface) of the semiconductor chip 21. The pad electrode 22 is a metal such as copper (Cu). The upper surface of the semiconductor chip 21 is a surface (electrode forming surface) on which the pad electrode 22 is formed. A plurality of bumps (projection electrodes) 23 are provided on the upper surface of the semiconductor chip 21. The bump 23 is, for example, a gold bump, a solder bump, a copper bump, or a bump containing solder and copper. The bumps 23 are connected to the pad electrodes 22 of the semiconductor chip 21 and to the pad electrodes 12 of the support substrate 11. Therefore, the support substrate 11 and the semiconductor chip 21 are electrically connected via the bumps 23.

支持基板１１の上面の中央部分は、支持基板１１の上面の中央部分を囲む外周部分よりも窪んでおり、支持基板１１の下面（背面）の中央部分は、支持基板１１の下面の外周部分よりも突出している。これにより、支持基板１１の上面の中央部分には、凹部１３が形成されている。すなわち、支持基板１１が撓むことにより、支持基板１１の上面の中央部
分に凹部１３が形成されている。ただし、支持基板１１の凹部１３は、支持基板１１の上面の中央部分に限らず、支持基板１１の上面の中央部分以外の部分に形成されてもよい。また、支持基板１１の凹部１３は、支持基板１１の上面の所定部分に形成されてもよい。支持基板１１の上面の所定部分は、支持基板１１の上面の中央部分であってもよい。支持基板１１の所定部分は、支持基板１１の上面の中央部分以外の部分であってもよい。 The central portion of the upper surface of the support substrate 11 is recessed from the outer peripheral portion surrounding the central portion of the upper surface of the support substrate 11, and the central portion of the lower surface (back surface) of the support substrate 11 is lower than the outer peripheral portion of the lower surface of the support substrate 11. Is also prominent. Thereby, a recess 13 is formed in the central portion of the upper surface of the support substrate 11. That is, the concave portion 13 is formed in the central portion of the upper surface of the support substrate 11 by bending the support substrate 11. However, the recess 13 of the support substrate 11 is not limited to the central portion of the upper surface of the support substrate 11, and may be formed in a portion other than the central portion of the upper surface of the support substrate 11. Further, the recess 13 of the support substrate 11 may be formed in a predetermined portion of the upper surface of the support substrate 11. The predetermined portion on the upper surface of the support substrate 11 may be a central portion of the upper surface of the support substrate 11. The predetermined portion of the support substrate 11 may be a portion other than the central portion of the upper surface of the support substrate 11.

図１Ａに示すように、半導体チップ２１の少なくとも一部分が、支持基板１１の凹部１３に収容される。半導体チップ２１の一部分が、支持基板１１の凹部１３に収容されてもよいし、半導体チップ２１の全体が支持基板１１の凹部１３に収容されてもよい。支持基板１１の凹部１３の底面のサイズは、半導体チップ２１の外形サイズと同じ又は半導体チップ２１の外形サイズよりも大きくなっている。そのため、半導体チップ２１は、支持基板１１の凹部１３に安定した状態で収容されている。   As shown in FIG. 1A, at least a part of the semiconductor chip 21 is accommodated in the recess 13 of the support substrate 11. A part of the semiconductor chip 21 may be accommodated in the recess 13 of the support substrate 11, or the entire semiconductor chip 21 may be accommodated in the recess 13 of the support substrate 11. The size of the bottom surface of the recess 13 of the support substrate 11 is the same as the outer size of the semiconductor chip 21 or larger than the outer size of the semiconductor chip 21. Therefore, the semiconductor chip 21 is housed in a stable state in the recess 13 of the support substrate 11.

支持基板１１の上面には、接着剤１４が設けられている。接着剤１４は、支持基板１１と半導体チップ２１との間に設けられているとともに、支持基板１１の凹部１３を覆っている。接着剤１４の量を調整することにより、図１Ｂに示すように、支持基板１１の上面の水平な底部とその周囲の傾斜部からなる凹部１３の周囲（凹部１３の傾斜部より外側）に接着剤１４を設けるようにしてもよい。すなわち、支持基板１１の凹部１３を囲むように接着剤１４を設けるようにしてもよい。接着剤１４は、半導体チップ２１を支持基板１１に固着するとともに、支持基板１１の凹部１３の形状を保持する。接着剤１４は、ペースト状であってもよいし、フィルム状であってもよい。ペースト状の接着剤１４として、例えば、ＮＣＰ（Non-Conductive Paste）及びＡＣＰ（Anisotropic Conductive Paste）等を用いてもよい。フィルム状の接着剤１４として、例えば、ＮＣＦ（Non-Conductive Film）及びＡＣＦ（Anisotropic Conductive Film）等を用いてもよい。   An adhesive 14 is provided on the upper surface of the support substrate 11. The adhesive 14 is provided between the support substrate 11 and the semiconductor chip 21 and covers the recess 13 of the support substrate 11. By adjusting the amount of the adhesive 14, as shown in FIG. 1B, it adheres to the periphery of the concave portion 13 (outside the inclined portion of the concave portion 13) composed of the horizontal bottom portion of the upper surface of the support substrate 11 and the peripheral inclined portion thereof. An agent 14 may be provided. That is, you may make it provide the adhesive agent 14 so that the recessed part 13 of the support substrate 11 may be enclosed. The adhesive 14 fixes the semiconductor chip 21 to the support substrate 11 and holds the shape of the recess 13 of the support substrate 11. The adhesive 14 may be in the form of a paste or a film. As the paste adhesive 14, for example, NCP (Non-Conductive Paste), ACP (Anisotropic Conductive Paste), or the like may be used. As the film adhesive 14, for example, NCF (Non-Conductive Film), ACF (Anisotropic Conductive Film), or the like may be used.

支持基板１１の下面には、複数の半田ボール１５が設けられている。半田ボール１５は、支持基板１１の下面に形成されたボールパッド（図示せず）に搭載されている。   A plurality of solder balls 15 are provided on the lower surface of the support substrate 11. The solder ball 15 is mounted on a ball pad (not shown) formed on the lower surface of the support substrate 11.

本実施形態に係る半導体装置１によれば、半導体チップ２１の一部分が、支持基板１１の凹部１３に収容されることにより、半導体装置１を薄型化することができる。図２Ａは、半導体装置１の要部拡大断面図である。図２Ｂは、支持基板１１に凹部１３を形成していない場合の半導体装置１Ａの要部拡大断面図である。図２Ｂに示す半導体装置１Ａでは、支持基板１１に凹部１３が形成されていないため、半導体装置１Ａの高さ（Ｈ３）及び支持基板１１の上面から半導体チップ２１までの高さ（Ｈ４）が低くなっていない。   According to the semiconductor device 1 according to the present embodiment, a part of the semiconductor chip 21 is accommodated in the recess 13 of the support substrate 11, so that the semiconductor device 1 can be thinned. FIG. 2A is an enlarged cross-sectional view of a main part of the semiconductor device 1. FIG. 2B is an enlarged cross-sectional view of a main part of the semiconductor device 1 </ b> A when the concave portion 13 is not formed on the support substrate 11. In the semiconductor device 1A shown in FIG. 2B, since the recess 13 is not formed in the support substrate 11, the height (H3) of the semiconductor device 1A and the height (H4) from the upper surface of the support substrate 11 to the semiconductor chip 21 are low. is not.

図２Ａに示す半導体装置１は、半導体チップ２１の一部分が、支持基板１１の凹部１３に収容されている。そのため、図２Ａに示す半導体装置１は、図２Ｂに示す半導体装置１Ａと比較して、半導体装置１の高さ（Ｈ１）及び支持基板１１の上面から半導体チップ２１までの高さ（Ｈ２）が低くなる。本実施形態では、半導体チップ２１の一部分を支持基板１１の凹部１３に収容することにより、半導体チップ２１の薄型化を行わずに半導体装置１の薄型化を行うことができる。   In the semiconductor device 1 shown in FIG. 2A, a part of the semiconductor chip 21 is accommodated in the recess 13 of the support substrate 11. Therefore, the semiconductor device 1 shown in FIG. 2A has a height (H1) of the semiconductor device 1 and a height (H2) from the upper surface of the support substrate 11 to the semiconductor chip 21 as compared with the semiconductor device 1A shown in FIG. 2B. Lower. In this embodiment, by accommodating a part of the semiconductor chip 21 in the recess 13 of the support substrate 11, the semiconductor device 1 can be thinned without thinning the semiconductor chip 21.

図３に示すように、半導体装置１と半導体装置１Ａとを、薄型の電子機器１００に実装した場合、半導体装置１は、実装ボード１０１に設けられたケース１０２と接触しないが、半導体装置１Ａは、ケース１０２と接触する。このように、本実施形態に係る半導体装置１は、半導体装置１Ａと比較して、より薄型の機器に実装することが可能となる。   As shown in FIG. 3, when the semiconductor device 1 and the semiconductor device 1A are mounted on a thin electronic device 100, the semiconductor device 1 does not contact the case 102 provided on the mounting board 101, but the semiconductor device 1A In contact with the case 102. Thus, the semiconductor device 1 according to the present embodiment can be mounted on a thinner device as compared with the semiconductor device 1A.

図４から図８及び図１０を参照して、本実施形態に係る半導体装置１の製造方法について説明する。図４に示すように、支持基板１１を用意した後、支持基板１１に接着剤１４を塗布することにより、支持基板１１の上面に接着剤１４を形成する。図５に示すように
、フリップチップボンダー（接合装置）のステージ３１の上に支持基板１１を設置する。ステージ３１の上部には、ステージ３１の中央部分の上面が、ステージ３１の中央部分を囲む外周部分の上面よりも窪んだ凹部３２が設けられている。 A method for manufacturing the semiconductor device 1 according to the present embodiment will be described with reference to FIGS. 4 to 8 and 10. As shown in FIG. 4, after preparing the support substrate 11, the adhesive 14 is formed on the upper surface of the support substrate 11 by applying the adhesive 14 to the support substrate 11. As shown in FIG. 5, the support substrate 11 is placed on a stage 31 of a flip chip bonder (joining apparatus). On the upper part of the stage 31, there is provided a recess 32 in which the upper surface of the central part of the stage 31 is recessed from the upper surface of the outer peripheral part surrounding the central part of the stage 31.

図６に示すように、フリップチップボンダーのボンディングツール３３を用いて、支持基板１１の上面と半導体チップ２１の上面とが向かい合うように、支持基板１１の上方に半導体チップ２１を配置する。ボンディングツール３３の吸引口３４から半導体チップ２１の下面（背面）を吸引することにより、ボンディングツール３３は半導体チップ２１を保持している。半導体チップ２１の下面は、半導体チップ２１の電極形成面の反対面である。   As shown in FIG. 6, the semiconductor chip 21 is arranged above the support substrate 11 so that the upper surface of the support substrate 11 and the upper surface of the semiconductor chip 21 face each other using a flip chip bonder bonding tool 33. The bonding tool 33 holds the semiconductor chip 21 by sucking the lower surface (back surface) of the semiconductor chip 21 from the suction port 34 of the bonding tool 33. The lower surface of the semiconductor chip 21 is the opposite surface of the electrode formation surface of the semiconductor chip 21.

図７に示すように、ボンディングツール３３を降下させ、半導体チップ２１の上面を接着剤１４に押し付けるとともに、半導体チップ２１のバンプ２３を支持基板１１のパッド電極１２に押し付ける。図７に示すように、半導体チップ２１に荷重（圧力）が加えられ、半導体チップ２１が支持基板１１に押し当てられることによって、支持基板１１が撓み、支持基板１１の中央部分がステージ３１の凹部３２に押し込まれる。支持基板１１の中央部分をステージ３１の凹部３２に押し込むことにより、支持基板１１の上面の中央部分が、支持基板１１の上面の中央部分を囲む外周部分よりも窪み、支持基板１１の下面の中央部分が、支持基板１１の下面の外周部分よりも突出する。これにより、支持基板１１の中央部分に、半導体チップ２１の少なくとも一部分を収容する凹部１３が形成される。また、支持基板１１の中央部分以外の部分をステージ３１の凹部３２に押し込むことにより、支持基板１１の上面の中央部分以外の部分に、凹部１３を形成してもよい。また、支持基板１１の所定部分をステージ３１の凹部３２に押し込むことにより、支持基板１１の上面の所定部分に、凹部１３を形成してもよい。   As shown in FIG. 7, the bonding tool 33 is lowered, and the upper surface of the semiconductor chip 21 is pressed against the adhesive 14, and the bumps 23 of the semiconductor chip 21 are pressed against the pad electrode 12 of the support substrate 11. As shown in FIG. 7, when a load (pressure) is applied to the semiconductor chip 21 and the semiconductor chip 21 is pressed against the support substrate 11, the support substrate 11 is bent, and the central portion of the support substrate 11 is a concave portion of the stage 31. 32. By pushing the center portion of the support substrate 11 into the recess 32 of the stage 31, the center portion of the upper surface of the support substrate 11 is depressed more than the outer peripheral portion surrounding the center portion of the upper surface of the support substrate 11, and the center of the lower surface of the support substrate 11 The portion protrudes from the outer peripheral portion of the lower surface of the support substrate 11. As a result, a recess 13 that accommodates at least a part of the semiconductor chip 21 is formed in the central portion of the support substrate 11. Further, the recess 13 may be formed in a portion other than the central portion of the upper surface of the support substrate 11 by pushing a portion other than the central portion of the support substrate 11 into the recess 32 of the stage 31. Further, the recess 13 may be formed in a predetermined portion of the upper surface of the support substrate 11 by pushing a predetermined portion of the support substrate 11 into the recess 32 of the stage 31.

支持基板１１の凹部１３の深さは、支持基板１１の剛性、半導体チップ２１の実装時の荷重（圧力）及びステージ３１の凹部３２の深さによって決定される。例えば、支持基板１１の変形量が、ステージ３１の凹部３２の深さよりも大きい場合（支持基板１１の変形量＞ステージ３１の凹部３２の深さ）、図７に示すように、支持基板１１の凹部１３の深さは、ステージ３１の凹部３２の深さと同じになる。支持基板１１の剛性が低い（例えば、支持基板１１の板厚が薄い、支持基板１１がフレキシブル基板である等）場合や、半導体チップ２１の実装時の荷重（圧力）が大きい場合は、支持基板１１の変形量は大きくなる。支持基板１１の変形量が、ステージ３１の凹部３２の深さよりも大きい場合、支持基板１１の変形量は、支持基板１１の剛性、半導体チップ２１の実装時の荷重（圧力）及びステージ３１の凹部３２の深さによって決定される。   The depth of the recess 13 of the support substrate 11 is determined by the rigidity of the support substrate 11, the load (pressure) when mounting the semiconductor chip 21, and the depth of the recess 32 of the stage 31. For example, when the deformation amount of the support substrate 11 is larger than the depth of the concave portion 32 of the stage 31 (the deformation amount of the support substrate 11> the depth of the concave portion 32 of the stage 31), as shown in FIG. The depth of the recess 13 is the same as the depth of the recess 32 of the stage 31. When the rigidity of the support substrate 11 is low (for example, the support substrate 11 is thin, the support substrate 11 is a flexible substrate, etc.), or when the load (pressure) when mounting the semiconductor chip 21 is large, the support substrate The amount of deformation of 11 increases. When the amount of deformation of the support substrate 11 is larger than the depth of the recess 32 of the stage 31, the amount of deformation of the support substrate 11 includes the rigidity of the support substrate 11, the load (pressure) when mounting the semiconductor chip 21, and the recess of the stage 31. Determined by the depth of 32.

例えば、支持基板１１の変形量が、ステージ３１の凹部３２の深さよりも小さい場合（支持基板１１の変形量＜ステージ３１の凹部３２の深さ）、図８に示すように、支持基板１１の凹部１３の深さは、支持基板１１の変形量となる。支持基板１１の剛性が高い（例えば、支持基板１１の板厚が厚い等）場合や、半導体チップ２１の実装時の荷重（圧力）が小さい場合は、支持基板１１の変形量は小さくなる。支持基板１１の変形量が、ステージ３１の凹部３２の深さよりも小さい場合、支持基板１１の変形量は、支持基板１１の剛性及び半導体チップ２１の実装時の荷重（圧力）によって決定される。   For example, when the deformation amount of the support substrate 11 is smaller than the depth of the concave portion 32 of the stage 31 (the deformation amount of the support substrate 11 <the depth of the concave portion 32 of the stage 31), as shown in FIG. The depth of the recess 13 is the amount of deformation of the support substrate 11. When the rigidity of the support substrate 11 is high (for example, when the thickness of the support substrate 11 is thick) or when the load (pressure) at the time of mounting the semiconductor chip 21 is small, the deformation amount of the support substrate 11 is small. When the deformation amount of the support substrate 11 is smaller than the depth of the recess 32 of the stage 31, the deformation amount of the support substrate 11 is determined by the rigidity of the support substrate 11 and the load (pressure) when the semiconductor chip 21 is mounted.

支持基板１１に凹部１３が形成された後、加熱処理を行うことにより、接着剤１４を硬化する。例えば、ボンディングツール３３を加熱し、接着剤１４を１５０℃以上２５０℃以下に加熱することにより、接着剤１４を硬化する。また、ボンディングツール３３を加熱するとともに、ステージ３１を加熱してもよい。接着剤１４が硬化することにより、支持基板１１に形成された凹部１３の形状が保持される。   After the recess 13 is formed on the support substrate 11, the adhesive 14 is cured by performing a heat treatment. For example, the bonding tool 33 is heated, and the adhesive 14 is heated to 150 ° C. or higher and 250 ° C. or lower to cure the adhesive 14. Further, the bonding tool 33 may be heated and the stage 31 may be heated. As the adhesive 14 is cured, the shape of the recess 13 formed in the support substrate 11 is maintained.

支持基板１１に凹部１３を形成するために、支持基板１１として、容易に変形させることが可能な有機基板を用いることが好ましい。支持基板１１が有機基板である場合、支持基板１１をステージ３１の凹部３２に押し込んだだけでは、支持基板１１に形成された凹部１３の形状は保持されず、支持基板１１は元のフラットな状態に戻ってしまう。本実施形態では、支持基板１１の凹部１３を接着剤１４で覆い、接着剤１４を硬化することにより、支持基板１１に形成された凹部１３の形状を保持している。   In order to form the recess 13 in the support substrate 11, it is preferable to use an organic substrate that can be easily deformed as the support substrate 11. When the support substrate 11 is an organic substrate, simply pressing the support substrate 11 into the recess 32 of the stage 31 does not maintain the shape of the recess 13 formed in the support substrate 11, and the support substrate 11 is in an original flat state. Will return to. In the present embodiment, the concave portion 13 of the support substrate 11 is covered with the adhesive 14 and the adhesive 14 is cured, so that the shape of the concave portion 13 formed on the support substrate 11 is maintained.

例えば、図９Ａに示すように、支持基板１１の上面に形成された接着剤１４の量が少ない場合、図９Ｂに示すように、接着剤１４は、支持基板１１に形成された凹部１３を覆わない。接着剤１４が、支持基板１１に形成された凹部１３を覆っていない場合、ステージ３１及びボンディングツール３３を取り外すと、図９Ｃに示すように、支持基板１１に形成された凹部１３の形状が保持されず、支持基板１１は元のフラットな状態に戻る。   For example, as shown in FIG. 9A, when the amount of the adhesive 14 formed on the upper surface of the support substrate 11 is small, the adhesive 14 covers the recess 13 formed in the support substrate 11 as shown in FIG. 9B. Absent. When the adhesive 14 does not cover the recess 13 formed in the support substrate 11, when the stage 31 and the bonding tool 33 are removed, the shape of the recess 13 formed in the support substrate 11 is maintained as shown in FIG. 9C. Instead, the support substrate 11 returns to the original flat state.

一方、接着剤１４が、支持基板１１の凹部１３を覆っている場合、支持基板１１の撓んでいる部分と接着剤１４とが接触している。支持基板１１の撓んでいる部分と接着剤１４とが接触することにより、支持基板１１の撓んでいる部分が元の状態に戻ることが抑制される。支持基板１１の凹部１３の周囲に接着剤１４を設けることにより、支持基板１１の撓んでいる部分が元の状態に戻ることがより抑制される。支持基板１１の撓んでいる部分が元の状態に戻ることが抑制されるため、支持基板１１に形成された凹部１３の形状が保持される。   On the other hand, when the adhesive 14 covers the recess 13 of the support substrate 11, the bent portion of the support substrate 11 and the adhesive 14 are in contact with each other. When the bending part of the support substrate 11 and the adhesive 14 contact, it is suppressed that the bending part of the support substrate 11 returns to an original state. By providing the adhesive 14 around the recess 13 of the support substrate 11, it is further suppressed that the bent portion of the support substrate 11 returns to the original state. Since it is suppressed that the bent part of the support substrate 11 returns to an original state, the shape of the recessed part 13 formed in the support substrate 11 is maintained.

支持基板１１の剛性が高い場合、接着剤１４が支持基板１１の凹部１３を覆うとともに、接着剤１４が支持基板１１の凹部１３の周囲に設けられていることが好ましい。支持基板１１の種類、厚さ等に応じて、支持基板１１の凹部１３の周囲に接着剤１４を設けるか否かを決定してもよい。   When the rigidity of the support substrate 11 is high, it is preferable that the adhesive 14 covers the recess 13 of the support substrate 11 and the adhesive 14 is provided around the recess 13 of the support substrate 11. Whether or not the adhesive 14 is provided around the recess 13 of the support substrate 11 may be determined according to the type and thickness of the support substrate 11.

接着剤１４が硬化した後、ステージ３１及びボンディングツール３３を取り外し、図１０に示すように、支持基板１１の下面に複数の半田ボール１５を搭載する。半田ボール１５は、支持基板１１の下面に形成されたボールパッド（図示せず）に搭載される。   After the adhesive 14 is cured, the stage 31 and the bonding tool 33 are removed, and a plurality of solder balls 15 are mounted on the lower surface of the support substrate 11 as shown in FIG. The solder ball 15 is mounted on a ball pad (not shown) formed on the lower surface of the support substrate 11.

図４から図８及び図１０を参照して説明した半導体装置１の製造方法では、支持基板１１の凹部１３の周囲に接着剤１４を設けているが、支持基板１１の凹部１３の周囲に接着剤１４を設けないようにしてもよい。また、支持基板１１の凹部１３の底部全てと傾斜部の一部まで接着剤１４を設けてもよい。   In the method for manufacturing the semiconductor device 1 described with reference to FIGS. 4 to 8 and 10, the adhesive 14 is provided around the recess 13 of the support substrate 11. The agent 14 may not be provided. Further, the adhesive 14 may be provided up to the entire bottom portion of the recess 13 of the support substrate 11 and a part of the inclined portion.

半導体装置１をＰｏＰ（パッケージオンパッケージ）構造としてもよい。すなわち、図１１に示すように、半導体装置１は、半導体パッケージ４１と、半導体パッケージ４１に実装された半導体パッケージ５１とを備えてもよい。図１１に示す半導体装置１は、支持基板１１と、支持基板１１の上面に設けられた半導体パッケージ５１と、支持基板１１と半導体パッケージ５１との間に設けられた半導体チップ２１と、を備えている。   The semiconductor device 1 may have a PoP (package on package) structure. That is, as shown in FIG. 11, the semiconductor device 1 may include a semiconductor package 41 and a semiconductor package 51 mounted on the semiconductor package 41. A semiconductor device 1 shown in FIG. 11 includes a support substrate 11, a semiconductor package 51 provided on the upper surface of the support substrate 11, and a semiconductor chip 21 provided between the support substrate 11 and the semiconductor package 51. Yes.

半導体パッケージ４１は、凹部１３が形成された支持基板１１と、支持基板１１の上面に設けられた接着剤１４と、支持基板１１の上面に設置された半導体チップ２１と、を有している。半導体チップ２１は、支持基板１１の上面の中央部分に設置されてもよい。支持基板１１の下面には、複数の半田ボール１５が設けられている。   The semiconductor package 41 includes the support substrate 11 in which the recess 13 is formed, the adhesive 14 provided on the upper surface of the support substrate 11, and the semiconductor chip 21 installed on the upper surface of the support substrate 11. The semiconductor chip 21 may be installed in the central portion of the upper surface of the support substrate 11. A plurality of solder balls 15 are provided on the lower surface of the support substrate 11.

半導体パッケージ５１は、支持基板５２と、支持基板５２の上面に設けられた半導体チップ５３と、半導体チップ５３を封止するモールド樹脂５４と、を有している。支持基板５２の下面には、複数の半田ボール５５が設けられている。   The semiconductor package 51 includes a support substrate 52, a semiconductor chip 53 provided on the upper surface of the support substrate 52, and a mold resin 54 that seals the semiconductor chip 53. A plurality of solder balls 55 are provided on the lower surface of the support substrate 52.

半導体チップ５３の上面には、複数のパッド電極５６が形成されている。半導体チップ５３は、パッド電極５６に接続されたボンディングワイヤ５７を介して、支持基板５２に電気的に接続されている。支持基板５２の下面に設けられた半田ボール５５と、支持基板１１の上面に形成された電極（図示せず）とが接合されることにより、半導体パッケージ４１と半導体パッケージ５１とが電気的に接続される。図１１に示す半導体装置１では、支持基板１１の凹部１３の周囲に接着剤１４を設けているが、支持基板１１の凹部１３の周囲に接着剤１４を設けないようにしてもよい。また、支持基板１１の凹部１３の底部全てと傾斜部の一部まで接着剤１４を設けてもよい。   A plurality of pad electrodes 56 are formed on the upper surface of the semiconductor chip 53. The semiconductor chip 53 is electrically connected to the support substrate 52 via bonding wires 57 connected to the pad electrode 56. The solder balls 55 provided on the lower surface of the support substrate 52 and the electrodes (not shown) formed on the upper surface of the support substrate 11 are joined, so that the semiconductor package 41 and the semiconductor package 51 are electrically connected. Is done. In the semiconductor device 1 shown in FIG. 11, the adhesive 14 is provided around the recess 13 of the support substrate 11, but the adhesive 14 may not be provided around the recess 13 of the support substrate 11. Further, the adhesive 14 may be provided up to the entire bottom portion of the recess 13 of the support substrate 11 and a part of the inclined portion.

図１１に示すように、半導体チップ２１と、半導体パッケージ５１とは接触していない。すなわち、半導体チップ２１と支持基板５２との間には間隙５８が設けられており、半導体チップ２１の下面と支持基板５２の下面とは接触していない。支持基板５２の下面は、半導体チップ５３が設置されている面の反対面である。凹部１３が形成されていない支持基板１１を有する半導体パッケージ６１に対して、半導体パッケージ５１を実装した場合、図１２に示すように、半導体チップ２１と、半導体パッケージ５１とが接触する。図１２は、凹部１３が形成されていない支持基板１１を有する半導体パッケージ６１に対して、半導体パッケージ５１を実装した場合の半導体装置１Ａの断面図である。図１１に示す半導体装置１では、半導体チップ２１と、半導体パッケージ５１とが接触していないため、半導体チップ２１の破損が抑制される。支持基板５２の下面に設けられた半田ボール５５を所定の高さにすることにより、半導体チップ２１と支持基板５２との間に間隙５８を形成することが可能である。   As shown in FIG. 11, the semiconductor chip 21 and the semiconductor package 51 are not in contact with each other. That is, a gap 58 is provided between the semiconductor chip 21 and the support substrate 52, and the lower surface of the semiconductor chip 21 and the lower surface of the support substrate 52 are not in contact with each other. The lower surface of the support substrate 52 is the opposite surface to the surface on which the semiconductor chip 53 is installed. When the semiconductor package 51 is mounted on the semiconductor package 61 having the support substrate 11 in which the recess 13 is not formed, the semiconductor chip 21 and the semiconductor package 51 come into contact as shown in FIG. FIG. 12 is a cross-sectional view of the semiconductor device 1 </ b> A when the semiconductor package 51 is mounted on the semiconductor package 61 having the support substrate 11 in which the recess 13 is not formed. In the semiconductor device 1 shown in FIG. 11, since the semiconductor chip 21 and the semiconductor package 51 are not in contact with each other, damage to the semiconductor chip 21 is suppressed. It is possible to form a gap 58 between the semiconductor chip 21 and the support substrate 52 by setting the solder balls 55 provided on the lower surface of the support substrate 52 to a predetermined height.

本実施形態によれば、半導体チップ２１の一部分を支持基板１１の凹部１３に収容し、下層の半導体パッケージ４１が有する支持基板１１と上層の半導体パッケージ５１との間をより狭くすることにより、半導体装置１を薄型化することができる。   According to this embodiment, a part of the semiconductor chip 21 is accommodated in the recess 13 of the support substrate 11, and the space between the support substrate 11 included in the lower semiconductor package 41 and the upper semiconductor package 51 is made narrower. The apparatus 1 can be thinned.

１ 半導体装置
１１、４２ 支持基板
１２ パッド電極
１３、３２ 凹部
１４ 接着剤
１５、５５ 半田ボール
２１、５３ 半導体チップ
２２、５７ パッド電極
２３ バンプ
３１ ステージ
３３ ボンディングツール
４１、５１ 半導体パッケージ
５４ モールド樹脂
５６ ボンディングワイヤ
５８ 間隙 DESCRIPTION OF SYMBOLS 1 Semiconductor device 11, 42 Support substrate 12 Pad electrode 13, 32 Recess 14 Adhesive 15, 55 Solder ball 21, 53 Semiconductor chip 22, 57 Pad electrode 23 Bump 31 Stage 33 Bonding tool 41, 51 Semiconductor package 54 Mold resin 56 Bonding Wire 58 gap

Claims (6)

基板と、
前記基板の上面に設けられた半導体素子と、
前記基板の上面に設けられた接着剤と、
を備え、
前記基板の上面に、前記半導体素子の少なくとも一部を収容する凹部が形成され、
前記接着剤は、前記基板と前記半導体素子との間に設けられているとともに、前記基板の凹部を覆い、前記基板の凹部の周囲に設けられていることを特徴とする半導体装置。 A substrate,
A semiconductor element provided on the upper surface of the substrate;
An adhesive provided on the upper surface of the substrate;
With
A recess for accommodating at least a part of the semiconductor element is formed on the upper surface of the substrate,
The adhesive, with is provided between the substrate and the semiconductor element, not covering the concave portion of the substrate, wherein a provided around the concave portion of the substrate. 前記基板の凹部は、前記基板の上面の中央部分が、前記基板の上面の中央部分を囲む外周部分よりも窪み、前記基板の下面の中央部分が、前記基板の下面の中央部分を囲む外周部分よりも突出することにより形成されていることを特徴とする請求項１に記載の半導体装置。   The concave portion of the substrate is such that the central portion of the upper surface of the substrate is depressed more than the outer peripheral portion surrounding the central portion of the upper surface of the substrate, and the central portion of the lower surface of the substrate surrounds the central portion of the lower surface of the substrate The semiconductor device according to claim 1, wherein the semiconductor device is formed so as to protrude further. 前記基板の上面に設けられた半導体パッケージを備え、A semiconductor package provided on the upper surface of the substrate;
前記基板と前記半導体パッケージとの間に前記半導体素子が設けられており、The semiconductor element is provided between the substrate and the semiconductor package;
前記半導体素子と前記半導体パッケージとは接触していないことを特徴とする請求項１又は２に記載の半導体装置。The semiconductor device according to claim 1, wherein the semiconductor element and the semiconductor package are not in contact with each other. 基板の上面に接着剤を形成する工程と、Forming an adhesive on the upper surface of the substrate;
凹部を有するステージの上に前記基板を設置する工程と、Installing the substrate on a stage having a recess;
前記基板の上面と半導体素子の電極形成面とが向かい合うように、前記接着剤の上方に前記半導体素子を配置する工程と、Placing the semiconductor element above the adhesive so that the upper surface of the substrate and the electrode formation surface of the semiconductor element face each other;
前記半導体素子の電極形成面を前記接着剤に押し付けるとともに、前記半導体素子の電極を前記基板に押し付けて、前記ステージの凹部に前記基板を押し込むことにより、前記基板の上面に、前記半導体素子の少なくとも一部を収容する凹部を形成する工程と、The electrode forming surface of the semiconductor element is pressed against the adhesive, the electrode of the semiconductor element is pressed against the substrate, and the substrate is pressed into the recess of the stage, so that at least the semiconductor element is placed on the upper surface of the substrate. Forming a recess to accommodate a portion;
加熱処理により、前記接着剤を硬化する工程と、A step of curing the adhesive by heat treatment;
を備え、With
前記接着剤は、前記基板と前記半導体素子との間に設けられているとともに、前記基板の凹部を覆い、前記基板の凹部の周囲に設けられていることを特徴とする半導体装置の製The adhesive is provided between the substrate and the semiconductor element, covers the recess of the substrate, and is provided around the recess of the substrate.
造方法。Manufacturing method. 前記ステージの凹部に前記基板の中央部分を押し込み、前記基板の上面の中央部分を、前記基板の上面の中央部分を囲む外周部分よりも窪ませ、前記基板の下面の中央部分を、前記基板の下面の中央部分を囲む外周部分よりも突出させることにより、前記基板の上面に凹部を形成することを特徴とする請求項４に記載の半導体装置の製造方法。The central portion of the substrate is pushed into the recess of the stage, the central portion of the upper surface of the substrate is recessed from the outer peripheral portion surrounding the central portion of the upper surface of the substrate, and the central portion of the lower surface of the substrate is 5. The method of manufacturing a semiconductor device according to claim 4, wherein a recess is formed on the upper surface of the substrate by protruding from an outer peripheral portion surrounding a central portion of the lower surface. 前記基板の上面に半導体パッケージを設置する工程を備え、Providing a semiconductor package on the upper surface of the substrate;
前記基板と前記半導体パッケージとの間に前記半導体素子が設けられており、The semiconductor element is provided between the substrate and the semiconductor package;
前記半導体素子と前記半導体パッケージとは接触していないことを特徴とする請求項４又は５に記載の半導体装置の製造方法。6. The method of manufacturing a semiconductor device according to claim 4, wherein the semiconductor element and the semiconductor package are not in contact with each other.
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