JP5016811B2 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
JP5016811B2
JP5016811B2 JP2005345410A JP2005345410A JP5016811B2 JP 5016811 B2 JP5016811 B2 JP 5016811B2 JP 2005345410 A JP2005345410 A JP 2005345410A JP 2005345410 A JP2005345410 A JP 2005345410A JP 5016811 B2 JP5016811 B2 JP 5016811B2
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JP
Japan
Prior art keywords
semiconductor chip
chip
pattern
semiconductor device
base substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2005345410A
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English (en)
Japanese (ja)
Other versions
JP2007150154A (ja
JP2007150154A5 (https=
Inventor
俊彦 秋葉
孝洋 内藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Electronics Corp
Original Assignee
Renesas Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Electronics Corp filed Critical Renesas Electronics Corp
Priority to JP2005345410A priority Critical patent/JP5016811B2/ja
Publication of JP2007150154A publication Critical patent/JP2007150154A/ja
Publication of JP2007150154A5 publication Critical patent/JP2007150154A5/ja
Application granted granted Critical
Publication of JP5016811B2 publication Critical patent/JP5016811B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/099—Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/9413—Dispositions of bond pads on encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/791—Package configurations characterised by the relative positions of pads or connectors relative to package parts of direct-bonded pads
    • H10W90/792—Package configurations characterised by the relative positions of pads or connectors relative to package parts of direct-bonded pads between multiple chips

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  • Production Of Multi-Layered Print Wiring Board (AREA)
JP2005345410A 2005-11-30 2005-11-30 半導体装置 Expired - Fee Related JP5016811B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2005345410A JP5016811B2 (ja) 2005-11-30 2005-11-30 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2005345410A JP5016811B2 (ja) 2005-11-30 2005-11-30 半導体装置

Publications (3)

Publication Number Publication Date
JP2007150154A JP2007150154A (ja) 2007-06-14
JP2007150154A5 JP2007150154A5 (https=) 2009-01-22
JP5016811B2 true JP5016811B2 (ja) 2012-09-05

Family

ID=38211157

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2005345410A Expired - Fee Related JP5016811B2 (ja) 2005-11-30 2005-11-30 半導体装置

Country Status (1)

Country Link
JP (1) JP5016811B2 (https=)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4571679B2 (ja) * 2008-01-18 2010-10-27 Ｏｋｉセミコンダクタ株式会社 半導体装置
WO2011108308A1 (ja) 2010-03-04 2011-09-09 日本電気株式会社 半導体素子内蔵配線基板
WO2011125380A1 (ja) 2010-04-08 2011-10-13 日本電気株式会社 半導体素子内蔵配線基板
KR101145041B1 (ko) * 2010-10-19 2012-05-11 주식회사 네패스 반도체칩 패키지, 반도체 모듈 및 그 제조 방법
KR102205195B1 (ko) * 2018-01-23 2021-01-20 주식회사 네패스 반도체 칩 적층 패키지 및 그 제조 방법
KR102061850B1 (ko) * 2018-02-26 2020-01-02 삼성전자주식회사 팬-아웃 반도체 패키지
US11171115B2 (en) 2019-03-18 2021-11-09 Kepler Computing Inc. Artificial intelligence processor with three-dimensional stacked memory
US11836102B1 (en) 2019-03-20 2023-12-05 Kepler Computing Inc. Low latency and high bandwidth artificial intelligence processor
KR102436025B1 (ko) * 2019-04-10 2022-08-25 주식회사 네패스 안테나를 포함하는 반도체 패키지
US11152343B1 (en) 2019-05-31 2021-10-19 Kepler Computing, Inc. 3D integrated ultra high-bandwidth multi-stacked memory
US12086410B1 (en) 2019-05-31 2024-09-10 Kepler Computing Inc. Ferroelectric memory chiplet in a multi-dimensional packaging with I/O switch embedded in a substrate or interposer
US11844223B1 (en) 2019-05-31 2023-12-12 Kepler Computing Inc. Ferroelectric memory chiplet as unified memory in a multi-dimensional packaging
US11791233B1 (en) 2021-08-06 2023-10-17 Kepler Computing Inc. Ferroelectric or paraelectric memory and logic chiplet with thermal management in a multi-dimensional packaging

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4157829B2 (ja) * 2003-06-03 2008-10-01 カシオ計算機株式会社 半導体装置およびその製造方法

Also Published As

Publication number Publication date
JP2007150154A (ja) 2007-06-14

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