JP4980049B2 - 遷移後の薄層の緩和 - Google Patents

遷移後の薄層の緩和 Download PDF

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Publication number
JP4980049B2
JP4980049B2 JP2006502498A JP2006502498A JP4980049B2 JP 4980049 B2 JP4980049 B2 JP 4980049B2 JP 2006502498 A JP2006502498 A JP 2006502498A JP 2006502498 A JP2006502498 A JP 2006502498A JP 4980049 B2 JP4980049 B2 JP 4980049B2
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JP
Japan
Prior art keywords
layer
strained
vitreous
substrate
sio
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Expired - Lifetime
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JP2006502498A
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English (en)
Japanese (ja)
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JP2006519488A (ja
Inventor
ブリュノ、ギスレン
カルロ、マズル
エマニュエル、アレヌ
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Soitec SA
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Soitec SA
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Publication of JP2006519488A publication Critical patent/JP2006519488A/ja
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Publication of JP4980049B2 publication Critical patent/JP4980049B2/ja
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Expired - Lifetime legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76259—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along a porous layer

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Recrystallisation Techniques (AREA)
JP2006502498A 2003-02-28 2004-03-01 遷移後の薄層の緩和 Expired - Lifetime JP4980049B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
FR0302518 2003-02-28
FR0302518A FR2851847B1 (fr) 2003-02-28 2003-02-28 Relaxation d'une couche mince apres transfert
PCT/IB2004/000927 WO2004077552A1 (fr) 2003-02-28 2004-03-01 Relaxation d'une couche mince apres son transfert

Publications (2)

Publication Number Publication Date
JP2006519488A JP2006519488A (ja) 2006-08-24
JP4980049B2 true JP4980049B2 (ja) 2012-07-18

Family

ID=32843091

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006502498A Expired - Lifetime JP4980049B2 (ja) 2003-02-28 2004-03-01 遷移後の薄層の緩和

Country Status (4)

Country Link
EP (1) EP1597758A1 (fr)
JP (1) JP4980049B2 (fr)
FR (1) FR2851847B1 (fr)
WO (1) WO2004077552A1 (fr)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7235812B2 (en) * 2004-09-13 2007-06-26 International Business Machines Corporation Method of creating defect free high Ge content (>25%) SiGe-on-insulator (SGOI) substrates using wafer bonding techniques
CN100481345C (zh) * 2005-02-24 2009-04-22 硅绝缘体技术有限公司 SiGe层的热氧化及其应用
TWI457984B (zh) * 2008-08-06 2014-10-21 Soitec Silicon On Insulator 應變層的鬆弛方法
EP2151856A1 (fr) 2008-08-06 2010-02-10 S.O.I. TEC Silicon Relâchement de couches tendues
EP2151852B1 (fr) 2008-08-06 2020-01-15 Soitec Relâchement et transfert de couches tendues
EP2159836B1 (fr) * 2008-08-25 2017-05-31 Soitec Couches de durcissement pour le relâchement de couches contraintes
CN102239538A (zh) * 2008-09-24 2011-11-09 S.O.I.探测硅绝缘技术公司 形成经松弛半导体材料层、半导体结构、装置的方法及包含经松弛半导体材料层、半导体结构、装置的工程衬底
FR2936903B1 (fr) * 2008-10-07 2011-01-14 Soitec Silicon On Insulator Relaxation d'une couche de materiau contraint avec application d'un raidisseur
EP2221853B1 (fr) * 2009-02-19 2012-04-25 S.O.I. TEC Silicon Relaxation et transfert de couches de matériaux sous contrainte

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5906951A (en) * 1997-04-30 1999-05-25 International Business Machines Corporation Strained Si/SiGe layers on insulator
US5882987A (en) * 1997-08-26 1999-03-16 International Business Machines Corporation Smart-cut process for the production of thin semiconductor material films
US20020089032A1 (en) * 1999-08-23 2002-07-11 Feng-Yi Huang Processing method for forming dislocation-free silicon-on-insulator substrate prepared by implantation of oxygen
JP4226175B2 (ja) * 1999-12-10 2009-02-18 富士通株式会社 半導体装置およびその製造方法
KR100429869B1 (ko) * 2000-01-07 2004-05-03 삼성전자주식회사 매몰 실리콘 저머늄층을 갖는 ｃｍｏｓ 집적회로 소자 및기판과 그의 제조방법
JP2002164520A (ja) * 2000-11-27 2002-06-07 Shin Etsu Handotai Co Ltd 半導体ウェーハの製造方法
US6940089B2 (en) * 2001-04-04 2005-09-06 Massachusetts Institute Of Technology Semiconductor device structure
JP2002305293A (ja) * 2001-04-06 2002-10-18 Canon Inc 半導体部材の製造方法及び半導体装置の製造方法
JP3648466B2 (ja) * 2001-06-29 2005-05-18 株式会社東芝 電界効果トランジスタ、半導体基板、電界効果トランジスタの製造方法及び半導体基板の製造方法
JP2003031495A (ja) * 2001-07-12 2003-01-31 Hitachi Ltd 半導体装置用基板の製造方法および半導体装置の製造方法

Also Published As

Publication number Publication date
EP1597758A1 (fr) 2005-11-23
FR2851847A1 (fr) 2004-09-03
FR2851847B1 (fr) 2005-10-14
JP2006519488A (ja) 2006-08-24
WO2004077552A1 (fr) 2004-09-10

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