JP4956295B2 - 半導体記憶装置 - Google Patents

半導体記憶装置 Download PDF

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Publication number
JP4956295B2
JP4956295B2 JP2007169015A JP2007169015A JP4956295B2 JP 4956295 B2 JP4956295 B2 JP 4956295B2 JP 2007169015 A JP2007169015 A JP 2007169015A JP 2007169015 A JP2007169015 A JP 2007169015A JP 4956295 B2 JP4956295 B2 JP 4956295B2
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JP
Japan
Prior art keywords
flag
bit
data transfer
bits
circuit
Prior art date
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Active
Application number
JP2007169015A
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English (en)
Japanese (ja)
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JP2009009289A (ja
JP2009009289A5 (enExample
Inventor
友之 柴田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Micron Memory Japan Ltd
Original Assignee
Elpida Memory Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Elpida Memory Inc filed Critical Elpida Memory Inc
Priority to JP2007169015A priority Critical patent/JP4956295B2/ja
Priority to US12/146,121 priority patent/US7941573B2/en
Publication of JP2009009289A publication Critical patent/JP2009009289A/ja
Publication of JP2009009289A5 publication Critical patent/JP2009009289A5/ja
Application granted granted Critical
Publication of JP4956295B2 publication Critical patent/JP4956295B2/ja
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
    • G06F13/4243—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with synchronous protocol
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • G11C7/1012—Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1066—Output synchronization
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/10—Aspects relating to interfaces of memory device to external buses
    • G11C2207/107—Serial-parallel conversion of data or prefetch
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Databases & Information Systems (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Dc Digital Transmission (AREA)
JP2007169015A 2007-06-27 2007-06-27 半導体記憶装置 Active JP4956295B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2007169015A JP4956295B2 (ja) 2007-06-27 2007-06-27 半導体記憶装置
US12/146,121 US7941573B2 (en) 2007-06-27 2008-06-25 Semiconductor memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2007169015A JP4956295B2 (ja) 2007-06-27 2007-06-27 半導体記憶装置

Publications (3)

Publication Number Publication Date
JP2009009289A JP2009009289A (ja) 2009-01-15
JP2009009289A5 JP2009009289A5 (enExample) 2011-04-14
JP4956295B2 true JP4956295B2 (ja) 2012-06-20

Family

ID=40162070

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007169015A Active JP4956295B2 (ja) 2007-06-27 2007-06-27 半導体記憶装置

Country Status (2)

Country Link
US (1) US7941573B2 (enExample)
JP (1) JP4956295B2 (enExample)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8045412B2 (en) * 2008-10-21 2011-10-25 Seagate Technology Llc Multi-stage parallel data transfer
US8928386B1 (en) * 2013-03-12 2015-01-06 Xilinx, Inc. Circuits for and methods of asychronously transmitting data in an integrated circuit
JP6694284B2 (ja) 2016-01-29 2020-05-13 シナプティクス・ジャパン合同会社 画像データ伝送システム、送信回路及び受信回路
CN112712834B (zh) * 2019-10-25 2024-09-06 长鑫存储技术(上海)有限公司 写操作电路、半导体存储器和写操作方法

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62217387A (ja) * 1986-03-18 1987-09-24 Nec Corp パタ−ン識別装置
JP2599998B2 (ja) * 1989-09-08 1997-04-16 富士通株式会社 復調装置
JP2599999B2 (ja) * 1989-09-13 1997-04-16 富士通株式会社 変復調装置
JPH05334206A (ja) 1992-05-29 1993-12-17 Toshiba Corp インターフェース制御装置
US5532940A (en) * 1993-11-24 1996-07-02 Intel Corporation Process, apparatus and system for selecting quantization levels for encoding video signals
GB9614561D0 (en) * 1996-07-11 1996-09-04 4Links Ltd Communication system with improved code
JP3684560B2 (ja) * 1996-09-03 2005-08-17 ソニー株式会社 データ受信装置および方法
JP4447200B2 (ja) * 2002-07-19 2010-04-07 Ｎｅｃエレクトロニクス株式会社 映像データ転送方法、表示制御回路及び液晶表示装置
JP4068427B2 (ja) 2002-10-08 2008-03-26 エルピーダメモリ株式会社 データインバージョン回路及び半導体装置
US6992506B2 (en) * 2003-03-26 2006-01-31 Samsung Electronics Co., Ltd. Integrated circuit devices having data inversion circuits therein with multi-bit prefetch structures and methods of operating same
US7395482B2 (en) * 2003-12-18 2008-07-01 International Business Machines Corporation Data storage systems
DE102005011386B4 (de) * 2005-03-11 2013-10-24 Qimonda Ag Schaltungseinheit zur Datenbitinvertierung
JP2007110258A (ja) * 2005-10-11 2007-04-26 Rohm Co Ltd 誤り検査装置およびそれを用いた再生装置
GB2447985B (en) * 2007-03-30 2011-12-28 Wolfson Microelectronics Plc Pattern detection circuitry
JP5214422B2 (ja) * 2008-02-15 2013-06-19 株式会社東芝 データ記憶システム
US7667629B2 (en) * 2008-05-27 2010-02-23 International Business Machines Corporation Generating a gray code for an odd length sequence using a virtual space

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Publication number Publication date
JP2009009289A (ja) 2009-01-15
US20090006687A1 (en) 2009-01-01
US7941573B2 (en) 2011-05-10

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