JP4945287B2 - Hard random number generator error detection method - Google Patents

Description

  The present invention relates to an error detection method for a hard random number generation circuit, and more particularly to an error detection method capable of detecting an abnormality in bit units for a hard random number generated by a hard random number generation circuit.

  Conventionally, in a gaming machine such as a ball game machine or a revolving game machine, a random number is generated at a predetermined timing to determine a lottery, that is, a winning combination and a defeat (losing, unfair winning combination). There are two types of random number generation: a soft random number generated from a count value obtained by realizing an increment counter by a software program and a hard random number generated using an increment counter that is hardware. Soft random numbers tend to be fraudulent because the increment counter operates in synchronization with the external clock. In addition, since the generation of soft random numbers is limited to the processing capability of the CPU in the gaming machine, hard random numbers are often used for lottery in the gaming machine.

  On the other hand, when a hard random number is used in a lottery in a gaming machine, it is difficult to detect an abnormality in the hard random number even if there is an abnormality in the increment counter that is hardware. In particular, when a problem occurs only in a specific bit of a hard random number, the occurrence frequency of winning is different from the design value. Therefore, a hard random number monitoring device is known in which comparison means is provided for each of the upper and lower bits of the counter value output from the increment counter (see, for example, Patent Document 1). This device detects an abnormality of the hard random number by comparing each of the upper bit and the lower bit of the hard random number with each of the upper bit and the lower bit of the previously acquired hard random number.

Japanese Patent Laying-Open No. 2005-168562 (pages 4-11, FIGS. 3-10)

  However, the conventional hard random number monitoring device only detects an abnormality for each of the upper bit and lower bit set of the hard random number. That is, if the bit value is changed even at one place in any of the bit sets, it is not regarded as a hard random number abnormality. There is a problem that an abnormal state in which only one specific bit in any bit set does not change cannot be detected as a hard random number abnormality.

  Moreover, in the conventional hard random number monitoring apparatus, since the hard random number acquired previously is compared with the hard random number acquired this time, an abnormality cannot be detected unless the game is executed twice or more. That is, in the state where no game is played, it is not possible to detect an abnormality of the hard random number. Furthermore, there is a problem that putting the determination process in the game interrupts the game and affects the shortest time of one game.

  The present invention has been made in view of such a problem, and an object of the present invention is to provide a hard random number generation circuit capable of detecting abnormality in bit units for hard random numbers without affecting the game. To provide an error detection method.

Game present invention, in order to achieve the object, a first aspect of the present invention, which includes a hard random number generating circuit which occurs the hard random number at a predetermined timing to draw the Toraku game machine In the error detection method for detecting an abnormality of the hard random number generation circuit in a machine, the central processing unit of the gaming machine acquires a plurality of hard random numbers from the hard random number generation circuit, and the plurality of hard random number bits It is determined whether or not there is an abnormality in the hard random number generation circuit by confirming whether or not all bits constituting the hard random number have been updated by performing an operation, and the bit operation is performed using the acquired first hardware A first step of performing a logical OR operation with a register A in which all the bits are 0 and storing them in the register A, the first hard random number, and a register in which all the bits are 1 A second step of performing an exclusive OR operation with B and storing it in the register B, and a third step of performing an OR operation with the register B and a register C in which all bits are 0 and storing in the register C And the obtained second hard random number, the fourth step of performing an OR operation with the register A and storing it in the register A, the second hard random number, and the register B in which all the bits are 1 are exclusive. A fifth step of performing a logical OR operation and storing in the register B, and a sixth step of performing a logical OR operation with the register B and storing in the register C, the fourth step The sixth step is repeated a number of times obtained by subtracting 1 from the obtained number of the hard random numbers, and when all the bits of the register A and the register C are 1, the hard random number And judging that there is no abnormality in the raw circuit.

According to a second aspect of the present invention, in the error detection method of the hard random number generation circuit according to the first aspect , one random number update confirmation process is performed in one game in the gaming machine, and the random number update confirmation is performed. The process is performed between the end of the previous one game and the lottery process using the hard random number of the next one game.

According to a third aspect of the present invention, in the error detection method of the hard random number generation circuit according to the first aspect , one random number update confirmation process is performed in one game in the gaming machine, and the random number update confirmation is performed. process, characterized in that it is performed during the pre Ki抽 election process a waiting process after.

According to a fourth aspect of the present invention, in the error detection method of the hard random number generation circuit according to the second or third aspect, the one game represents from detection of input of game value to payout processing .

  As described above, according to the present invention, the random number update confirmation process is performed once in one game, and the central processing unit of the gaming machine acquires a plurality of hard random numbers from the hard random number generation circuit. Since it is determined whether or not there is an abnormality in the hard random number generation circuit by performing bit operations on a plurality of hard random numbers and checking whether all the bits constituting the hard random numbers have been updated, An abnormality can be detected in units.

  In addition, the random number update confirmation process is performed from the end of the previous game until the lottery process using the hard random number of the next one game, or the standby process after the lottery process using the hard random number is performed. By executing the above, error detection of the hard random number generation circuit can be performed without affecting the game.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the present embodiment, a hard random number generation circuit of a revolving game machine will be described as an example, but it can also be applied to a hard random number generation circuit of a ball game machine or other game machines.

  FIG. 1 is a diagram showing an external appearance of a swivel type gaming machine according to an embodiment of the present invention. The spinning cylinder gaming machine 100 of the present embodiment includes display windows 101 to 103 that display symbols of a reel (rotating cylinder) that rotates inside, and a medal slot 104 into which medals used as gaming values are inserted. , A credit amount display device 115 for displaying the credit amount, bet buttons 116 to 118, a start lever 119, and stop buttons 120 to 122. In the display windows 101 to 103, winning line displays 105 to 109 for displaying five lines that can be effective lines for symbol stop are provided, and effective lines LEDs 110 to 110 for displaying lines that are activated depending on the number of inserted medals. 114 is provided.

  The credit number display device 115 displays the addition of the number of inserted medals when a medal is inserted from the medal insertion slot 104 or the number of medals to be paid out corresponding to the combination using a 7-segment LED or the like. When the bet button 116 is pressed, one credited medal is inserted, the credit number displayed on the credit number display device 115 is decreased by 1, and the effective line LED 110 is turned on. When the bet button 117 is pressed, two credited medals are inserted, the credit number displayed on the credit amount display device 115 is decreased by 2, and the effective lines LEDs 110 to 112 are turned on. When the bet button 118 is pressed, three credited medals are inserted, the number of credits displayed on the credit number display device 115 is decreased by 3, and the effective lines LEDs 110 to 114 are turned on.

  When the player operates the start lever 119 (start lever ON), the reels in the display windows 101 to 103 arranged in three horizontal rows in order from the left start to rotate from top to bottom. Simultaneously with the rotation of the reel, a lottery is performed in a main control unit (described later), and winning / losing of a combination is determined. When the stop buttons 120 to 122 are pressed, an opportunity to stop the reels rotating in order from the left is given.

  In addition, the swing type gaming machine 100 includes a payout number display device 123 that displays the number of medals to be paid out, a medal discharge port 124 from which medals are released, a medal tray 125 for storing the released medals, and a game It has a status lamp 126 for notifying the status and a checkout button 128 for checking out the credit. Further, in order to produce a game for the player, the revolving game machine 100 can acquire a speaker 127 that outputs sound effects, a notification lamp 129 that indicates that the lottery is won, and the player can acquire. It has a game counter display device 130 indicating the number of medals, and an image display device 131 on which an effect image is displayed.

  FIG. 2 is a block diagram showing a control circuit of the spinning cylinder game machine according to the embodiment of the present invention. The control circuit of the spinning-reel game machine of this embodiment is divided into a main control unit 201 and a sub-control unit 202 that is connected to the output of the main control unit 201 and executes processing related to effects. The main control unit 201 includes a central processing unit (CPU) 211, a read-only storage area (ROM) 212 that stores read-only data, a temporary storage area (RAM) 213 that stores readable and writable data, An increment counter 214, which is hardware (for example, an IC) that outputs a counter value, is connected to each other via a bus.

  In addition, the control circuit controls the input port 215 that receives a signal input for detecting the state change of the above-described buttons, levers, etc., and the above-described reel, LED, display device, etc. And an output port 216 for transmitting a signal output.

  FIG. 3 shows details of a hard random number generation circuit according to an embodiment of the present invention. When the player turns on the start lever 119, an STTSW signal is transmitted to the latch circuit 221 of the main control unit 201. In response to the output of the latch circuit 221, the two 8-bit counters 214a and 214b constituting the increment counter 214 start incrementing. The CPU 211 transmits a chip select (CS) signal to the 8-bit counters 214 a and 214 b at a predetermined timing, and takes in a 16-bit counter value via the data bus 222.

  That is, the increment counter 214 of the main control unit 201 simply increments the value from 0 to FFFF in hexadecimal by 1 and the 16-bit counter value read from the increment counter 214 by the CPU 211 at a predetermined timing is a hard random number. Become. The CPU 211 stores the fetched counter value in the RAM 213. The CPU 211 compares the counter value stored in the RAM 213 with the value of the lottery table stored in the ROM 212. In the lottery table, values corresponding to each combination are stored, and when the value matches any one, it is determined that the corresponding combination is won.

  In the hard random number generation circuit of this embodiment, the CPU and the counter are composed of separate elements. However, a counter circuit provided in the CPU may be used, or one 16-bit counter may be used. May be used.

  FIG. 4 is a flowchart showing an error detection method of the hard random number generation circuit according to the first exemplary embodiment of the present invention. The error detection method is stored as a program in the ROM 212 of the main control unit 201 and is incorporated in the main loop process of the main control unit 201. The main loop process is a loop process performed for each game. When the rotary gaming machine is turned on, the main control unit 201 performs an initialization process (S301), and performs a random number update confirmation process described later, that is, an error detection of a hard random number generation circuit (S302). When insertion of a medal as a game value is detected, one game is started, processing is performed according to the pressed bet button (S303), and the start lever is turned on.

  When the start lever is turned on (S304), a replay insertion process (S305) is performed, and then a random number lottery process is performed using a hard random number generation circuit (S306). In response to the start lever being turned on, the reels in the display windows arranged in three horizontal rows in order from the left start to rotate (S307), and the reels are stopped according to the pressing of the stop button (S308). When the reels stop, payout processing is performed according to the lottery result (S309), one game ends, and the process returns to the random number update confirmation processing (S302).

  In the first embodiment, the random number update confirmation process is performed before the medal insertion process (S303). That is, processing is performed when the CPU 211 is in a standby state. Since the random number update confirmation process is a process of several μs, it may be performed at any time after the end of the initialization process or between the end of the previous one game and the random number lottery process of the next one game. According to the first embodiment, the random number update confirmation process can be performed for each game, and the game is interrupted because it is performed using the idle time of the processing of the CPU 211 until the reel starts to rotate. Nor.

  FIG. 5 is a flowchart showing an error detection method of the hard random number generation circuit according to the second exemplary embodiment of the present invention. In the second embodiment, the random number update confirmation process is executed immediately before starting the spinning cylinder rotation process. Procedures and contents of initialization processing (S401), medal insertion processing / bet button processing (S402), start lever pressing processing (S403), replay insertion processing (S404), random number lottery processing (S405) are the same as in the first embodiment. Is the same. Here, since it is determined that the interval between one game and the game is 4.1 seconds or more, the next rotation process, that is, the reel rotation start time, The waiting process is performed so that the time until the reel is rotated is 4.1 seconds (S406). Therefore, a random number update confirmation process is performed during this standby process (S407). Thereafter, the spinning cylinder rotation process (S408), the spinning cylinder stop process (S409), and the payout process (S410) are performed in the same procedure as in the first embodiment, and the process returns to before the medal insertion process (S402).

  In the second embodiment, the random number update confirmation process is performed during the standby process. Since the random number update confirmation process is a process of several μs, the random number update confirmation process can be performed without affecting the minimum time of one game of 4.1 seconds. In the second embodiment, the random number update confirmation process is not necessarily performed for each game, but generally it is sufficient for error detection of the hard random number generation circuit in consideration of the frequency of the standby process.

  FIG. 6 is a flowchart showing random number update confirmation processing according to an embodiment of the present invention. This is processing performed in S302 and S407 of the flowchart described above. First, the CPU 211 stores a 16-bit counter value storage area (register X), a bit value 0 confirmation area A (register A), a bit value 1 confirmation area B (register B), and a bit value 1 confirmation in the RAM 213, respectively. An area C (register C) is set. The CPU 211 initializes all the bit value 0 confirmation area A and the bit value 1 confirmation area C to 0, and all the bit value 1 confirmation areas B to 1 (S501). In addition, the number of processing times is also set.

  In the random number check process, the CPU 211 performs a bit operation (S502), and updates the area set in the RAM 213. Details of the random number check process will be described later with reference to FIG. The CPU 211 reads the bit value 0 confirmation area A and confirms whether all the bits have changed from 0 to 1 (S503). Further, the bit value 1 confirmation area C is read to confirm whether all the bits have changed from 1 to 0 (S504). If both are positive, it is determined that there is no abnormality in the hard random number generation circuit, and the process ends.

  If either S503 or S504 is negative, random number check processing (S502) is performed until the number of processing times is reached (S505). If all the bits have not changed from 0 → 1 or 1 → 0 even after the number of processing times has been reached, it is determined that an abnormality has occurred in the random number generation circuit, and error processing is executed (S506). In this way, in the random number update confirmation process, the CPU 211 acquires a plurality of hard random numbers from the hard random number generation circuit, performs bit calculation of the plurality of hard random numbers, and has updated all the bits constituting the hard random numbers. Whether or not there is an abnormality in the hard random number generation circuit is determined.

  For example, if the number of processing times is 100, the random number update confirmation processing is completed in about 1.8 μs when the program for random number update confirmation processing is about 150 cycles and the system clock is 8 MHz. Therefore, the error detection of the hard random number generation circuit can be performed by one random number update confirmation processing in one game.

  FIG. 7 shows a random number check process according to an embodiment of the present invention. This is the process of S502 in the flowchart of FIG. FIG. 8 shows the transition of the result of bit operation for each area set in the RAM 213. During the random number update confirmation process, the CPU 211 transmits a control (CONT) signal to the latch circuit 221 to keep the increment counter 214 in the increment operation state. The CPU 211 transmits a chip select (CS) signal at a predetermined timing, and stores the 16-bit counter value read from the increment counter 214 in the counter value storage area (S601). Next, the contents of the counter value storage area and the contents of the bit value 0 confirmation area A are ORed (S602) and stored in the bit value 0 confirmation area A (S603). Since the bit value 0 confirmation calculation (S603) is performed every time the random number update confirmation process is performed, it is confirmed that all bits have changed from 0 to 1 by executing at least several tens of processes. be able to. In other words, it is possible to detect an abnormal state that there is a bit that has not changed from 0 even after several tens of executions.

  On the other hand, the contents of the counter value storage area and the contents of the bit value 1 confirmation area B are subjected to an exclusive OR (XOR) operation and stored in the bit value 1 confirmation area B. In the bit value 1 confirmation area B, the contents obtained by inverting the contents 0 and 1 of the counter value storage area are stored. Next, the contents of the bit value 1 confirmation area B and the contents of the bit value 1 confirmation area C are ORed (S604) and stored in the bit value 1 confirmation area C (S605). The bit value 1 confirmation area B is all reset to 1 before the next processing. Since the calculation for checking the bit value 1 is performed every time the initial random number update confirmation processing is performed, it is confirmed that all bits have changed from 1 to 0 by executing at least several tens of processing times. be able to. In other words, it is possible to detect an abnormal state in which there is a bit that has not changed from 1 even after several tens of executions.

  In this way, the error detection of the hard random number generation circuit confirms that all the bits of the increment counter 214 have changed from 0 → 1 and 1 → 0. The presence or absence can be detected.

  According to the present embodiment, the error detection of the hard random number generation circuit can be detected by one random number update check process in one game, which affects the shortest time of one game of 4.1 seconds. Absent. In addition, since it is possible to detect abnormalities in units of hard random numbers, malfunctions in the hard random number generation circuit that occurred during the production of a revolving game machine, and problems in the hard random number generation circuit after it was introduced to the market It becomes possible to discover.

It is a figure which shows the external appearance of the rotary type game machine concerning one Embodiment of this invention. It is a block diagram which shows the control circuit of the rotary type game machine concerning one Embodiment of this invention. It is a figure which shows the hard random number generation circuit concerning one Example of this invention. It is a flowchart which shows the error detection method of the hard random number generation circuit concerning 1st Example of this invention. It is a flowchart which shows the error detection method of the hard random number generation circuit concerning the 2nd Example of this invention. It is a flowchart which shows the random number update confirmation process concerning one Embodiment of this invention. It is a flowchart which shows the random number check process concerning one Embodiment of this invention. It is a figure which shows the transition of the result of the bit calculation of each area | region set to RAM in the random number check process.

Explanation of symbols

100-turn-type game machine 101-103 display window 104 medal slot 105-109 winning line display 110-114 active line LED
115 Credit Number Display Device 116-118 Bet Button 119 Start Lever 120-122 Stop Button 123 Payout Number Display Device 124 Medal Release Port 125 Medal Receiving Plate 126 Status Lamp 127 Speaker 128 Checkout Button 129 Notification Lamp 130 Game Counter Display Device 131 Image Display Device 201 Main control unit 202 Sub control unit 211 Central processing unit (CPU)
212 Read-only storage area (ROM)
213 Temporary storage area (RAM)
214 Increment counter 215 Input port 216 Output port 221 Latch circuit 222 Data bus

Claims (4)

In the gaming machine having a hard random number generating circuit which occurs the hard random number at a predetermined timing to draw the Toraku of the game machine, the error detection method for detecting an abnormality of the hardware random number generator,
Whether the central processing unit of the gaming machine has acquired a plurality of hard random numbers from the hard random number generation circuit, performs bit operations on the plurality of hard random numbers, and has updated all the bits constituting the hard random numbers By determining whether or not there is an abnormality in the hard random number generation circuit ,
The bit operation is
A first step of performing an OR operation with the acquired first hard random number and the register A in which all bits are 0, and storing the result in the register A;
A second step of performing an exclusive OR operation with the first hard random number and the register B in which all bits are 1 and storing the result in the register B;
A third step of performing an OR operation with the register B and a register C in which all bits are 0 and storing the result in the register C;
A fourth step of performing an OR operation with the obtained second hard random number and the register A and storing it in the register A;
A fifth step of performing an exclusive OR operation with the second hard random number and the register B in which all bits are 1 and storing the result in the register B;
A sixth step of performing an OR operation with the register B and storing the register B in the register C;
Repeating the fourth step to the sixth step by subtracting 1 from the obtained number of the hard random numbers,
An error detection method for a hard random number generation circuit, wherein when all the bits of the register A and the register C are 1, it is determined that there is no abnormality in the hard random number generation circuit. One random number update confirmation process is performed in one game in the gaming machine,
2. The hard random number according to claim 1, wherein the random number update check process is executed between the end of the previous one game and the lottery process using the hard random number of the next one game. Error detection method for generating circuit. One random number update confirmation process is performed in one game in the gaming machine,
The random number update check processing, the error detection method of the hard random number generating circuit according to claim 1, characterized in that it is performed during the pre Ki抽 election process a waiting process after. 4. The hard random number generation circuit error detection method according to claim 2, wherein the one game represents from detection of game value input to payout processing.

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