JP4943959B2 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP4943959B2
JP4943959B2 JP2007176037A JP2007176037A JP4943959B2 JP 4943959 B2 JP4943959 B2 JP 4943959B2 JP 2007176037 A JP2007176037 A JP 2007176037A JP 2007176037 A JP2007176037 A JP 2007176037A JP 4943959 B2 JP4943959 B2 JP 4943959B2
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substrate
semiconductor
electrode
pressure contact
pressure
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JP2009016522A5 (en
JP2009016522A (en
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謙太郎 熊澤
善広 戸村
雄一郎 山田
一博 登
鉄平 岩瀬
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Panasonic Corp
Panasonic Holdings Corp
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Panasonic Corp
Matsushita Electric Industrial Co Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/1301Shape
    • H01L2224/13016Shape in side view
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/1301Shape
    • H01L2224/13016Shape in side view
    • H01L2224/13018Shape in side view comprising protrusions or indentations
    • H01L2224/13019Shape in side view comprising protrusions or indentations at the bonding interface of the bump connector, i.e. on the surface of the bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01087Francium [Fr]
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    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06Polymers
    • H01L2924/078Adhesive characteristics other than chemical
    • H01L2924/0781Adhesive characteristics other than chemical being an ohmic electrical conductor
    • H01L2924/07811Extrinsic, i.e. with electrical conductive fillers
    • HELECTRICITY
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    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/3011Impedance
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    • H01ELECTRIC ELEMENTS
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    • H01L2924/35Mechanical effects
    • H01L2924/351Thermal stress
    • H01L2924/3511Warping

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Abstract

<P>PROBLEM TO BE SOLVED: To provide a highly reliable semiconductor device capable of obtaining the predetermined electrical characteristic in the semiconductor packaged under a satisfactory junction. <P>SOLUTION: A substrate 2 and the semiconductor 1 are press-contacted and electrically jointed through a substrate electrode 2A and a semiconductor electrode 3, and the semiconductor device is manufactured by adhering and sealing between the substrate 2 and the semiconductor 1 by an adhesive-sealing material 4. At least one assembly of the substrate electrode 2A and the semiconductor electrode 3 are jointed while one or the both of the substrate electrode 2A and the semiconductor electrode 3 have a press-contacting surface 2A-1 slanted orthogonally to the direction of the press-contact. <P>COPYRIGHT: (C)2009,JPO&amp;INPIT

Description

本発明は、電子回路用プリント基板(特許請求の範囲および本明細書において、代表例として「基板」と称しているが、この「基板」にはインタポーザや電子部品が装着される他の部品などの被装着体を意味する。)に電子部品例えばICチップで代表される半導体や表面弾性波(SAW)デバイスなどを単体(ICの場合にはベアIC)状態で基板に実装した半導体装置に関するものである。   The present invention relates to a printed circuit board for electronic circuits (referred to as a “substrate” as a representative example in the claims and the present specification, and other components on which an interposer or an electronic component is mounted, etc.) A semiconductor device in which an electronic component such as a semiconductor represented by an IC chip or a surface acoustic wave (SAW) device is mounted on a substrate in a single state (a bare IC in the case of an IC). It is.

今日、電子回路基板は、多様な製品に使用されるようになり、日増しにその性能が向上し、回路基板上で用いられる周波数も高くなっている。これに対応してICをパッケージのない裸のままのフリップチップとして実装することによりインピーダンスが低くなるフリップチップ実装は、高周波を使用する近時の電子機器に適した実装方式となっている。また、このフリップチップ実装は携帯機器が増加するのに併せ日進月歩する薄型化、小型化からも強く求められている。しかし、このような裸での実装方式により、回路基板に搭載したICや、電子機器、フラットパネルディスプレイへ実装したICはダメージを受けやすく、実装後のICには不良品が混在している。   Nowadays, electronic circuit boards are used in various products, their performance is improved day by day, and the frequencies used on the circuit boards are also increasing. Corresponding to this, flip chip mounting, in which impedance is lowered by mounting an IC as a bare flip chip without a package, is a mounting method suitable for recent electronic devices using high frequencies. In addition, the flip chip mounting is strongly demanded from the trend of thinning and miniaturization, which is steadily advancing as the number of portable devices increases. However, with such a bare mounting method, an IC mounted on a circuit board, an IC mounted on an electronic device or a flat panel display is easily damaged, and defective products are mixed in the mounted IC.

このため、薄型化、小型化して提供されるようになったCSP(Chip Size Package)や薄型化、小型化、高密度集積化されるようになったBGA(Ball Grid Array)がフリップチップに代わって用いられるようにもなっている。   For this reason, CSP (Chip Size Package), which has been provided in a thinner and smaller size, and BGA (Ball Grid Array), which has become thinner, smaller, and more densely integrated, replace flip-chips. It has come to be used.

図17は従来例1を示し、それらの半導体86を基板としての液晶ディスプレイ84に接合するのに異方性導電接着剤層81を用いる方法(例えば、特許文献1参照。)を採用している。異方性導電接着剤層81は、絶縁性樹脂83の中に導電性微片82を加え厚さ方向にだけ導電性を持たせたものである。これを用いた実装方法は、図17(A)に示すようにセパレータ85に貼り合わせてある異方性導電接着剤層81をセパレータ85から剥して、図17(B)に示すように液晶ディスプレイ84のガラスに貼り付けた上から、半導体86を加熱しながら加圧して、異方性導電接着剤層81を半導体86および液晶ディスプレイ84の両表面に馴染ませて硬化させることにより行われる。これにより、半導体86は、異方性導電接着剤層81を介し液晶ディスプレイ84上への接着固定と、液晶ディスプレイ84との間の封止がなされ、かつ、対向し合うAuなどよりなる突起状の半導体電極87と基板電極88とは、異方性導電接着剤層81の厚さ方向の導電性によって電気的に接続され、半導体電極87と基板電極88が対向し合わない領域では、半導体86側と液晶ディスプレイ84側とが電気的に接続されることはない。   FIG. 17 shows a conventional example 1, which employs a method of using an anisotropic conductive adhesive layer 81 (see, for example, Patent Document 1) to join the semiconductor 86 to a liquid crystal display 84 as a substrate. . The anisotropic conductive adhesive layer 81 is obtained by adding a conductive fine piece 82 to an insulating resin 83 to provide conductivity only in the thickness direction. As shown in FIG. 17 (A), the mounting method using this is such that the anisotropic conductive adhesive layer 81 bonded to the separator 85 is peeled off from the separator 85, and the liquid crystal display as shown in FIG. 17 (B). Then, the semiconductor 86 is pressed while being heated, and the anisotropic conductive adhesive layer 81 is made to conform to both surfaces of the semiconductor 86 and the liquid crystal display 84 and is cured. As a result, the semiconductor 86 is bonded and fixed on the liquid crystal display 84 via the anisotropic conductive adhesive layer 81 and is sealed between the liquid crystal display 84 and has a protruding shape made of facing Au or the like. The semiconductor electrode 87 and the substrate electrode 88 are electrically connected by the conductivity in the thickness direction of the anisotropic conductive adhesive layer 81, and in the region where the semiconductor electrode 87 and the substrate electrode 88 do not face each other, the semiconductor 86. The side and the liquid crystal display 84 side are not electrically connected.

また、従来例2として、主として導電性微片を含まないUV硬化樹脂を用いて実装することも行われている。このような実装は、UV硬化樹脂を基板の上に塗布し、その上に半導体を加熱しながら加圧して、UV硬化樹脂を一旦軟化ないしは溶融させて、半導体および基板間に馴染ませるのに併せ、対向し合う突起状の半導体電極を基板電極に圧接した電気的な接合状態に保って、UV照射によりUV硬化樹脂を硬化させて行われる。これにより、UV樹脂の硬化時の収縮による引き付けにて半導体電極および基板電極間の接合状態をより強めて半導体および基板が接着されると共に両者間の封止がなされる。   In addition, as a conventional example 2, mounting is mainly performed using a UV curable resin that does not include conductive fine particles. In such mounting, a UV curable resin is applied onto a substrate, and a semiconductor is pressurized while being heated, so that the UV curable resin is once softened or melted so as to fit between the semiconductor and the substrate. The process is performed by curing the UV curable resin by UV irradiation while keeping the projecting semiconductor electrodes facing each other in an electrical contact state in pressure contact with the substrate electrode. As a result, the bonding state between the semiconductor electrode and the substrate electrode is further strengthened by the attraction due to the shrinkage when the UV resin is cured, and the semiconductor and the substrate are bonded together, and the both are sealed.

また、従来例3として、導電性微片を含まない接着フィルムを用いて実装することも行われている。このような実装は、基板に接着フィルムを貼った上から、突起状の電極がレベリングされていない半導体を加熱しながら加圧して行われる。これによって、半導体はレベリングされていない突起状の半導体電極が接着フィルムを突き破って基板電極に圧接することでレベリングされると共に電気的な接合状態となり、このレベリング接合状態にて接着フィルムにより基板に接着されるのと同時に両者間が封止される。
特公昭62−6652号公報
Further, as Conventional Example 3, mounting is also performed using an adhesive film that does not include conductive fine pieces. Such mounting is performed by applying pressure while heating a semiconductor on which a protruding electrode is not leveled after an adhesive film is attached to a substrate. As a result, the semiconductor is leveled by protruding semiconductor electrodes that are not leveled through the adhesive film and press-contacting the substrate electrode, and the semiconductor electrode is brought into an electrically bonded state. In this leveled bonded state, the semiconductor film is bonded to the substrate. At the same time, the gap between the two is sealed.
Japanese Examined Patent Publication No. 62-6652

ところが、本発明者は上記いずれの実装方式によっても接合不良が発生することを経験しており、特に半導体86は所定の電気的特性が得られないこともある。これは、図16に模式的に示すように、半導体101を加圧ヘッド111によって接合ステージ112上の基板102に圧接しながら実装するのに、半導体101および基板102の半導体電極103および基板電極105の圧接位置に半導体101および基板102に垂直な圧接力F(半導体101に働く状態で図示している。)が半導体101や基板102に対し働くことによる。このような圧接力Fは、半導体電極87、基板電極88相互の接合部、半導体101および基板102の一方または双方に残留応力σが発生し、接合不良を引き起こす要因となる。   However, the present inventor has experienced that bonding failure occurs by any of the above mounting methods, and in particular, the semiconductor 86 may not obtain predetermined electrical characteristics. As schematically shown in FIG. 16, the semiconductor 101 and the semiconductor electrode 103 of the substrate 102 and the substrate electrode 105 are mounted on the semiconductor 101 while being pressed against the substrate 102 on the bonding stage 112 by the pressure head 111. This is because a pressing force F (shown in a state of acting on the semiconductor 101) perpendicular to the semiconductor 101 and the substrate 102 is exerted on the semiconductor 101 and the substrate 102 at the pressing position. Such a pressure contact force F causes a residual stress σ at one or both of the semiconductor electrode 87 and the junction between the substrate electrodes 88 and at one or both of the semiconductor 101 and the substrate 102 and causes a bonding failure.

また、今日の微細化が進んだICチップにあっては前記残留応力σによって結晶構造に歪みが生じるので、ICチップ内のトランジスタを動作させる電流が変動し、これがトランジスタ特性変動を引き起こし所定の電気特性を得ることができないことがある。   Further, in today's miniaturized IC chips, the crystal structure is distorted by the residual stress σ, so that the current for operating the transistors in the IC chip fluctuates, which causes transistor characteristic fluctuations and a predetermined electric current. The characteristics may not be obtained.

本発明の目的は、十分な電気的接合の基に実装した半導体に所定の電気特性が得られる信頼性の高い半導体装置を提供することにある。   An object of the present invention is to provide a highly reliable semiconductor device in which predetermined electrical characteristics can be obtained in a semiconductor mounted on the basis of sufficient electrical bonding.

上記の目的を達成するために、本発明の半導体装置は、半導体と、基板と、前記半導体に形成された半導体電極と、前記半導体電極に接合された前記基板上の基板電極と、前記半導体と前記基板との間に位置する接着・封止材と、前記基板の前記半導体が位置する面と異なる面に位置するシール層とを有し、前記基板のシール層がない部分を傾斜させ、前記傾斜させた傾斜面にて、前記基板電極と前記半導体電極とを接合したことを特徴としている。 To achieve the above object, a semiconductor device of the present invention includes a semiconductor, a substrate, a semi-conductor electrode formed on the semiconductor, and the board electrode on the substrate that has been engaged against the semiconductor electrode, An adhesive / sealing material located between the semiconductor and the substrate, and a seal layer located on a surface different from the surface where the semiconductor is located on the substrate, wherein the portion of the substrate without the seal layer is inclined is allowed at the inclined surface is inclined, and that it has bonding the semiconductor electrode and the substrate electrode and feature.

このような構成では、半導体および基板の半導体電極および基板電極は、基板の前記傾斜させている傾斜面にて、互いが接合されていることにより、半導体および基板が接着・封止材による接合過程での接着・封止を受けている間、半導体電極および基板電極間にく力を、接合方向分力と、基板の傾斜面に平行な傾斜方向分力とに分解して所定の接合状態に保たれ、傾斜方向分力は半導体および基板に接合方向の内部応力を生じさせる働きはしないので、その分半導体および基板の接合による内部残留応力が低減する。 In such a configuration, semi-conductor electrode and the substrate electrode of the semiconductor and the substrate, at the inclined surface that is the tilt of the substrate, by each other are joined, a semi-conductor and the substrate with an adhesive-sealant while undergoing bonding and sealing in the joining process, the work rather force to the semiconductor electrode and the substrate electrodeposition machining gap, the welding direction component force, is decomposed into parallel tilt direction component force on the inclined surface of the substrate a predetermined In this case, the component force in the tilt direction does not act to cause internal stress in the bonding direction in the semiconductor and the substrate, so that the internal residual stress due to the bonding between the semiconductor and the substrate is reduced accordingly.

上記において、さらに、前記半導体を前記傾斜面で屈曲させたものとすることができる。In the above, the semiconductor may be further bent at the inclined surface.

このような構成では、半導体および基板間で圧接状態に保持して互いが電気的に接合されている半導体電極および基板電極の互いに対向し合う組は、その圧接面の一方または双方が前記対向し合う方向において圧接の方向に直角な向きに対して傾斜していることにより、圧接状態での半導体および基板が接着・封止材による接合状態での接着・封止を受けている間、半導体電極および基板電極の圧接面に垂直に働く圧接力を、半導体および基板に垂直な圧接方向分力と、半導体および基板に平行で圧接方向に直角な圧接方向直角分力とに分解するが、接合している半導体電極と基板電極との組の互いが対向し合う組間で、前記対向し合う方向において互いに逆向きな圧接方向直角分力を生じさせて半導体や基板を介し釣り合わせ半導体や基板を移動させないので、半導体や基板の移動を阻止する特別な措置なしにも、前記所定の接合状態をよく保ち、これが緩むことはない。また、圧接方向直角分力は半導体電極、基板電極の接合状態維持に貢献はするが、半導体および基板に圧接方向の内部応力を生じさせる働きはしないので、その分半導体および基板の圧接による内部残留応力が低減する。   In such a configuration, the semiconductor electrode and the substrate electrode, which are held in pressure contact between the semiconductor and the substrate and are electrically connected to each other, have one or both of the pressure contact surfaces facing each other. By being inclined with respect to the direction perpendicular to the direction of press contact in the mating direction, the semiconductor electrode while the semiconductor and the substrate in the press contact state are bonded / sealed in a bonded state by an adhesive / sealing material The pressure force acting perpendicularly to the pressure contact surface of the substrate electrode is decomposed into a force component in the pressure direction perpendicular to the semiconductor and the substrate and a force component perpendicular to the pressure direction parallel to the semiconductor and the substrate, but perpendicular to the pressure direction. A pair of semiconductor electrodes and substrate electrodes that are opposed to each other, in which the perpendicular force components in the pressing direction opposite to each other in the opposing direction are generated to balance the semiconductor and the substrate via the semiconductor and the substrate Since not moved, even without special measures to prevent the movement of the semiconductor and the substrate, keeping well the predetermined bonding condition, it will not loosen. In addition, although the perpendicular component force in the pressure direction contributes to maintaining the bonding state of the semiconductor electrode and the substrate electrode, it does not work to cause internal stress in the pressure direction in the semiconductor and the substrate. Stress is reduced.

上記において、さらに、前記傾斜面は、前記基板の端である一辺の部分であるものとすることができる。In the above, the inclined surface may be a part of one side which is an end of the substrate.

上記において、さらに、前記一辺の部分に外部電極を設けたものとすることができる。In the above, an external electrode may be provided on the one side.

上記において、さらに、前記シール層は、レジストであるものとすることができる。In the above, the seal layer may be a resist.

上記において、さらに、前記半導体は、メモリチップであり、さらに、前記基板のシール層がない部分にコントロールチップが前記基板に接合されているものとすることができる。In the above, the semiconductor may be a memory chip, and a control chip may be bonded to the substrate at a portion where the sealing layer of the substrate is not provided.

上記において、さらに、半導体装置は、SDメモリカードであるものとすることができる。In the above, the semiconductor device may be an SD memory card.

本発明の半導体装置によれば、基板の前記傾斜させている傾斜面にて接合されている半導体電極および基板電極の組による接合位置では、半導体および基板が接合過程で接着・封止を受けている間、互いの接合面間に働く圧接力を、接合方向分力と、基板の傾斜面に平行な傾斜方向分力とに分解して所定の接合状態を保ち、傾斜方向分力が半導体および基板に接合方向の内部応力を生じさせる働きをしない分、半導体および基板の接合による内部残留応力を低減するので、半導体や基板の内部残留応力に弱い部分に適用して、接合不良が生じたり、半導体に所定の電気特性が得られなくなるようなことを防止することができ、信頼性の高い実装が実現する。 According to the semiconductor device of the present invention, the semiconductor and the substrate are bonded and sealed in the bonding process at the bonding position of the set of the semiconductor electrode and the substrate electrode bonded on the inclined inclined surface of the substrate. during are, the pressure contact force acting between the bonding surfaces to each other, the bonding direction component force, is decomposed into parallel tilt direction component force on the inclined surface of the substrate maintaining a predetermined bonding condition, the inclination direction component force semiconductor and Since it does not work to generate internal stress in the bonding direction on the substrate, it reduces the internal residual stress due to the bonding of the semiconductor and the substrate. It is possible to prevent the predetermined electrical characteristics from being obtained in the semiconductor, and to realize highly reliable mounting.

以下、本発明の実施の形態に係る半導体装置につき、図を参照しながら詳細に説明し、本発明の理解に供する。なお、以下に示す実施の形態は本発明の具体例であって、本発明の技術的範囲の記載事項を限定するものではない。   Hereinafter, a semiconductor device according to an embodiment of the present invention will be described in detail with reference to the drawings for understanding of the present invention. The following embodiments are specific examples of the present invention and do not limit the items described in the technical scope of the present invention.

本実施の形態の半導体装置は、場合別に代表的に例示した、図1に示す例、図2に示す例、図3に示す例、図4に示す例、図5に示す例、図6に示す例、図7に示す例、図8に示す例、図9に示す例、図10に示す例、図11に示す例、図12に示す例、図13に示す例、図14に示す例、図15に示す例、図16に示す例のように、半導体1、1B、1C、1Dと、基板2と、半導体1に形成された複数の半導体電極3と、この半導体電極3に図1(b)の模式図のようにステージ11および加圧ヘッド12間でのアクチュエータ13などによる加圧力にてV方向の圧接を伴い電気的に接合された基板2上の複数の基板電極2Aと、半導体1と基板2との間に位置する接着・封止材4と、を備えている。半導体1は既述したベアIC、CSP、BGAのいずれでも使用できる。しかし、これに限られることはなく表面弾性波デバイスなどを単体で取り扱い実装対象とする場合を含む。また、基板2は電子回路用プリント基板であるが、既述したようにインタポーザや各種電子部品が装着される他の部品などの被装着体を意味する。接着・封止材4は、既述した異方性導電接着剤、UV硬化樹脂、導電性微片を含まない接着フィルムを用いてよいが、これに限られることはない。多くの場合、半導体電極3はワイヤボンディングなどにより形成した1段ないしは2段形態の突起状電極、いわゆるバンプとされ、基板電極4はプリント配線の一部として平坦に形成される。   The semiconductor device of this embodiment is representatively exemplified in each case, the example shown in FIG. 1, the example shown in FIG. 2, the example shown in FIG. 3, the example shown in FIG. 4, the example shown in FIG. Example shown in FIG. 7, example shown in FIG. 8, example shown in FIG. 9, example shown in FIG. 10, example shown in FIG. 11, example shown in FIG. 12, example shown in FIG. 13, example shown in FIG. 15, the semiconductor 1, 1B, 1C, 1D, the substrate 2, the plurality of semiconductor electrodes 3 formed on the semiconductor 1, and the semiconductor electrode 3 as shown in FIG. A plurality of substrate electrodes 2A on the substrate 2 that are electrically joined together with pressure contact in the V direction by a pressure applied by an actuator 13 or the like between the stage 11 and the pressure head 12 as shown in the schematic diagram of FIG. And an adhesive / sealing material 4 positioned between the semiconductor 1 and the substrate 2. The semiconductor 1 can be any of the bare IC, CSP, and BGA described above. However, the present invention is not limited to this, and includes a case where a surface acoustic wave device or the like is handled alone and is a mounting target. Moreover, although the board | substrate 2 is a printed circuit board for electronic circuits, as above-mentioned, it means to-be-mounted bodies, such as other components with which an interposer and various electronic components are mounted | worn. The adhesive / sealant 4 may be an adhesive film that does not include the previously described anisotropic conductive adhesive, UV curable resin, and conductive fine pieces, but is not limited thereto. In many cases, the semiconductor electrode 3 is a one-step or two-step protruding electrode formed by wire bonding or the like, or a so-called bump, and the substrate electrode 4 is formed flat as a part of the printed wiring.

しかし、本実施の形態は、上記例示の各半導体装置において、基板電極2Aと半導体電極3との少なくとも1つの組は、それら基板電極2Aおよび半導体電極3の一方または双方が圧接の方向Vに直角な向きHに対して角度θ傾斜した圧接面2A−1(図1〜図5、図7〜図15)または圧接面3−A(図3、図6)を有して接合されていることを特徴としている。従って、例えば図3、図6に示す例のように半導体電極3に傾斜した圧接面3−Aを形成するには、ワイヤボンディングによって形成したバンプと称される突起状の半導体電極3に対し、切断や傾斜面の押し付けによる加工によって傾斜した圧接面3−Aとすればよいが、傾斜した圧接面3−Aとしない場合は特に突起電極としなくてよくなる。また、図1〜図5に示す各例のように、基板電極2Aに基板2の面から傾斜した圧接面2A−1を形成するには突起電極として加工するのが好適となるが、プリント配線によっては形成が困難であるため、平坦なプリント配線、電極上にワイヤボンディングなどによって突起状電極を形成した後、傾斜した圧接面2A−1を加工により形成することになる。   However, according to the present embodiment, in each of the semiconductor devices illustrated above, at least one set of the substrate electrode 2A and the semiconductor electrode 3 is perpendicular to the direction V in which one or both of the substrate electrode 2A and the semiconductor electrode 3 are pressed. A pressure contact surface 2A-1 (FIGS. 1 to 5, FIG. 7 to FIG. 15) or a pressure contact surface 3-A (FIGS. 3 and 6) inclined at an angle θ with respect to a specific direction H. It is characterized by. Therefore, for example, in order to form the inclined pressure contact surface 3-A on the semiconductor electrode 3 as in the example shown in FIGS. 3 and 6, the bump-shaped semiconductor electrode 3 called bump formed by wire bonding is used. The pressure contact surface 3-A may be inclined by cutting or pressing of the inclined surface. However, when the inclined pressure contact surface 3-A is not used, the protruding electrode is not particularly required. In addition, as in each example shown in FIGS. 1 to 5, it is preferable to process as a protruding electrode in order to form the press contact surface 2A-1 inclined from the surface of the substrate 2 on the substrate electrode 2A. In some cases, it is difficult to form the projection electrode, and after forming the protruding electrode on the flat printed wiring and the electrode by wire bonding or the like, the inclined pressure contact surface 2A-1 is formed by processing.

以上のように、互いの圧接面の一方または双方が図1(b)に基板電極2Aにて代表して示すように圧接方向Vに直角な向きHに対して傾斜した圧接面2A−1(またはおよび3A)とされていると、半導体1および基板2間で圧接状態に保持して互いが電気的に接合されている半導体電極3および基板電極2Aは、その圧接面2A−1(またはおよび3A)が圧接方向Vに直角な向きHに対して傾斜していることにより、圧接状態での半導体1および基板2が接着・封止材4による接合状態での接着・封止を受けている間、半導体電極3および基板電極2Aの傾斜した圧接面2A−1(またはおよび3A)に垂直に働く圧接力Fを、半導体1および基板2に垂直な圧接方向分力F1と、半導体1および基板2に平行で圧接方向Vに直角な圧接方向直角分力F2とに分解して所定の接合状態に保たれ、圧接方向直角分力F2は半導体1および基板2に圧接方向の内部応力を生じさせる働きはしないので、その分半導体1および基板2の圧接による内部残留応力が低減する。   As described above, one or both of the pressure contact surfaces are pressed against the direction H perpendicular to the pressure direction V as shown by the substrate electrode 2A in FIG. Or 3A), the semiconductor electrode 3 and the substrate electrode 2A, which are held in pressure contact between the semiconductor 1 and the substrate 2 and are electrically connected to each other, have their pressure contact surfaces 2A-1 (or 3A) is inclined with respect to the direction H perpendicular to the press-contact direction V, so that the semiconductor 1 and the substrate 2 in the press-contact state are bonded and sealed in the bonded state by the bond and sealing material 4. In the meantime, the pressure contact force F acting perpendicular to the inclined pressure contact surface 2A-1 (or 3A) of the semiconductor electrode 3 and the substrate electrode 2A, the pressure component F1 perpendicular to the semiconductor 1 and the substrate 2, and the semiconductor 1 and the substrate Pressure parallel to 2 and perpendicular to the pressure direction V It is decomposed into a direction perpendicular component force F2 and kept in a predetermined bonded state, and the pressure direction perpendicular component force F2 does not act to generate internal stress in the direction of pressure contact on the semiconductor 1 and the substrate 2, and accordingly, the semiconductor 1 and substrate The internal residual stress due to the pressure contact of 2 is reduced.

この結果、圧接面2A−1(またはおよび3A双方)が、接合時の圧接の方向Vに直角な向きHに対して傾斜して電気的に接合されている半導体電極3および基板電極2Aの組がある接合位置では、半導体1および基板2が圧接状態で接着・封止を受けている間、互いの圧接面2A−1(またはおよび3A)に垂直に働く圧接力Fを、半導体1および基板2に垂直な圧接方向分力F1と、半導体1および基板2に平行で圧接方向Vに直角な圧接方向直角分力F2とに分解して所定の接合状態を保ち、圧接方向直角分力F2が半導体1および基板2に圧接方向の内部応力を生じさせる働きをしない分、半導体1および基板2の圧接による内部残留応力を低減するので、半導体1や基板2の内部残留応力に弱い部分に適用して、接合不良が生じたり、半導体1などに所定の電気特性が得られなくなるようなことを防止することができ、信頼性の高い実装が実現する。また、半導体1や基板2の残留内部応力に弱い箇所に限って適用することにより、圧接面2A−1(またはおよび3A)を形成する不要な手間が省けるし、圧接方向直角分力F2が不要に働いて加圧ヘッド12に吸着などして保持されているだけの半導体1が移動して位置ずれする、具体的には基板電極2Aに対する半導体電極3の位置がずれる電極ずれなどの原因になるのを防止しやすい。基板2は位置固定しやすく特に問題とはならない。   As a result, the set of the semiconductor electrode 3 and the substrate electrode 2A in which the pressure contact surface 2A-1 (or both 3A) is electrically bonded with an inclination with respect to the direction H perpendicular to the direction V of the pressure contact at the time of bonding. At a certain bonding position, while the semiconductor 1 and the substrate 2 are bonded and sealed in the pressure contact state, the pressure contact force F acting perpendicularly to the pressure contact surfaces 2A-1 (or 3A) is applied to the semiconductor 1 and the substrate. 2 and a pressure direction perpendicular component force F2 parallel to the semiconductor 1 and the substrate 2 and perpendicular to the pressure direction V to be kept in a predetermined joined state. Since the internal residual stress due to the pressure welding of the semiconductor 1 and the substrate 2 is reduced by the amount that does not cause the internal stress in the pressure welding direction to occur in the semiconductor 1 and the substrate 2, it is applied to a portion that is weak to the internal residual stress of the semiconductor 1 and the substrate 2. Caused poor bonding. , It is possible to prevent such as predetermined electric characteristics can not be obtained in a semiconductor 1, realizes a highly reliable mounting. Further, by applying only to a portion that is weak against the residual internal stress of the semiconductor 1 or the substrate 2, unnecessary labor for forming the pressure contact surface 2A-1 (or 3A) can be saved, and the component force F2 perpendicular to the pressure direction is unnecessary. As a result, the semiconductor 1 that is only held by being sucked and held by the pressure head 12 moves and is displaced, specifically, an electrode displacement in which the position of the semiconductor electrode 3 is displaced with respect to the substrate electrode 2A. It is easy to prevent. The substrate 2 is easy to fix the position and does not cause a problem.

図1(a)、図2に示す例では、特に、傾斜した圧接面2A−1(またはおよび3A)を有して互いに接合されている基板電極2A、半導体電極3の組が複数あって、互いに対向し合う組どうしにおいて、圧接面2A−1(またはおよび3A)が前記対向し合う方向に同じ側、図では右側に向いて傾斜したものとしている。このため、圧接方向直角分力F2は同じ側に向いて生じ、半導体1を図の右側に移動させやすくなるが、向きHに対する傾斜の角度θを小さ目に調整することによって移動を防止することができる。しかし、角度θが小さすぎると圧接方向直角分力F2が小さくなり圧接方向分力F1がより大きくなり過ぎるので、半導体1や基板2の圧接時の残留内部応力による接合不良や所定の電気特性が得られない原因になる。   In the example shown in FIGS. 1A and 2, in particular, there are a plurality of sets of the substrate electrode 2 </ b> A and the semiconductor electrode 3 having the inclined pressure contact surface 2 </ b> A- 1 (or 3 </ b> A) and bonded to each other, In the pairs facing each other, the pressure contact surfaces 2A-1 (or 3A) are inclined toward the same side in the facing direction, that is, toward the right side in the drawing. For this reason, the pressure component perpendicular to the welding direction F2 is generated toward the same side, and it is easy to move the semiconductor 1 to the right side of the figure, but the movement can be prevented by adjusting the inclination angle θ with respect to the direction H to a small value. it can. However, if the angle θ is too small, the pressure direction perpendicular component force F2 becomes small and the pressure direction component force F1 becomes too large, so that the bonding failure due to the residual internal stress at the time of pressure welding of the semiconductor 1 and the substrate 2 and predetermined electrical characteristics are caused. It becomes a cause that cannot be obtained.

そこで、本発明者は、傾斜の角度θに対する、接合ピッチが80μmにおいて問題となる位置ずれ、半導体(IC)の特性不良の関係につき実験したところ、下記表1のようになった。   Therefore, the present inventor conducted an experiment on the relationship between the tilt angle θ and the misalignment at the junction pitch of 80 μm and the semiconductor (IC) characteristic failure. The results are shown in Table 1 below.

Figure 0004943959
Figure 0004943959

表1は、傾斜角θを1°、5°、10°、30°、45°、60°、80°の7通りに設定して、各角度で半導体1を100個ずつ実装したときの位置ずれや特性不良に該当した個数を示している。位置ずれは10°から1個が発生し、30°では5個となり、45°では7個となり、60°では10個とやや多いが採算内である。これに対し80°では30個と実用に耐えない結果となった。また、特性不良は1°では10個発生し実用に耐えないが、5°では1個となり十分実用でき、10°以上では発生しなかった。これを総合評価すると、本発明の実施例とする有効範囲は5°〜60°であるが、外観できず検査しにくい内部欠陥を重要欠陥とする立場からは、10°〜60°の範囲がよく、採算性も十分に配慮すると10°〜30°とするのがさらに好適である。しかし、これに限られることはない。他の実施例においても上記と同様の結果が得られる。   Table 1 shows the positions at which 100 semiconductors 1 are mounted at each angle with the inclination angle θ set to seven types of 1 °, 5 °, 10 °, 30 °, 45 °, 60 °, and 80 °. The number corresponding to the deviation or characteristic failure is shown. One misalignment occurs from 10 °, 5 at 30 °, 7 at 45 °, and 10 at 60 °, which are somewhat more profitable. On the other hand, at 80 °, 30 pieces were not practically used. Further, ten characteristic defects occurred at 1 ° and could not withstand practical use, but at 5 °, one defect was sufficient and could be practically used, and did not occur at 10 ° or more. When this is comprehensively evaluated, the effective range of the embodiment of the present invention is 5 ° to 60 °. However, from the standpoint that an internal defect that cannot be seen and difficult to inspect is an important defect, the effective range is 10 ° to 60 °. Well, considering the profitability sufficiently, it is more preferable that the angle is 10 ° to 30 °. However, it is not limited to this. In other examples, the same result as above can be obtained.

図2に示す例は、特に、図1に示す例の接着・封止材4に無機フィラー9を30〜70%含有したものを採用している。これにより、接着・封止材4は温度変化によって生じる応力が軽減して半導体1への応力影響を小さくするので、半導体1の内部応力による特性変化を抑えられ、寿命の増大が図れる。   The example shown in FIG. 2 employs, in particular, an adhesive / sealing material 4 of the example shown in FIG. 1 containing 30 to 70% of an inorganic filler 9. Thereby, the adhesive / sealing material 4 reduces the stress caused by the temperature change and reduces the influence of the stress on the semiconductor 1. Therefore, the characteristic change due to the internal stress of the semiconductor 1 can be suppressed and the life can be increased.

図3に示す例では、基板電極2Aおよび半導体電極3が共に当初から傾斜した圧接面2A−1、3Aを有して互いに接合されている。これにより、圧接による図1(b)に示すような半導体電極3側などの変形なしに十分な広さの接合面積が得られるので、圧接力Fを小さくしても接合不良が生じにくく、前記5°でも前記さらに好適な範囲となり得る。   In the example shown in FIG. 3, the substrate electrode 2 </ b> A and the semiconductor electrode 3 are joined together with pressure contact surfaces 2 </ b> A- 1 and 3 </ b> A inclined from the beginning. As a result, a sufficiently large joining area can be obtained without deformation on the semiconductor electrode 3 side or the like as shown in FIG. 1B due to pressure welding, so that even if the pressure welding force F is reduced, bonding failure hardly occurs. Even the angle of 5 ° can be the more preferable range.

図3に示す例では、さらに、基板電極2Aおよび半導体電極3の当初から傾斜した圧接面2A−1、3A間に導電性微片5を介在させて電気的な接合を行っている。これによって、圧接力Fをさらに小さくしても電気的な接合効率を高められる分だけ、傾斜した圧接面2A−1またはおよび3Aの傾斜の角度θをさらに小さくしやすく、図1に示す場合の接合の高信頼性を損なわない半導体1の位置ずれ防止に好適となる。従って、前記5°より小さい角度θでも前記さらに好適な範囲に入り得る。   In the example shown in FIG. 3, electrical bonding is further performed by interposing the conductive fine pieces 5 between the press contact surfaces 2A-1 and 3A inclined from the beginning of the substrate electrode 2A and the semiconductor electrode 3. Accordingly, even if the pressure F is further reduced, the inclination angle θ of the inclined pressure contact surfaces 2A-1 and 3A can be further reduced as much as the electrical joining efficiency can be increased. This is suitable for preventing misalignment of the semiconductor 1 without impairing the high reliability of bonding. Therefore, the angle θ smaller than 5 ° can fall within the more preferable range.

図4に示す例、図5に示す例、図6に示す例では、傾斜した圧接面2A−1またはおよび3Aを有して接合されている半導体電極3と基板電極2Aとの組の互いが対向し合う組間において、半導体1および基板2間の空間において前記対向し合う方向に互いに逆向きな内向きまたは外向きとなり圧接方向Vに直角で互いに逆向きな圧接方向直角分力F2を生じさせる向きに傾斜している。これにより、接合している半導体電極3と基板電極2Aとの組の互いが対向し合う組間において、互いに逆向き生じる圧接方向直角分力F2が半導体1や基板2を介し釣り合い半導体1や基板2を移動させない。従って、半導体1や基板2の移動を阻止する特別な措置なしにも、所定の接合状態をよく保ち、これが接着・封止の間緩むことはない。圧接面2A−1またはおよび3Aの傾斜の角度θを大きくして圧接時の残留応力による接合不良や所定の電気特性が得られなくなるのを確実に防止しながら、半導体1の基板2に対する位置ずれも防止し、半導体装置製造上の歩留まりを高められる。従って、位置ずれが生じにくく、前記60°やそれ以上の角度θでも前記さらに好適な範囲に入り得る。しかし、圧接される基板電極2Aや半導体電極3の一方または双方に圧接方向Vと直角な向きに変形して逃げ接合不良の原因になるような大きな角度θは外す必要がある。   In the example shown in FIG. 4, the example shown in FIG. 5, and the example shown in FIG. 6, the pair of the semiconductor electrode 3 and the substrate electrode 2 </ b> A joined with the inclined pressure contact surfaces 2 </ b> A- 1 and 3 </ b> A are connected to each other. In the space between the opposing groups, in the space between the semiconductor 1 and the substrate 2, the inward or outward directions opposite to each other in the opposing direction are generated, and the pressure direction perpendicular component force F <b> 2 perpendicular to the pressure direction V and opposite to each other is generated. It is inclined in the direction to make it. As a result, in the pair of the semiconductor electrode 3 and the substrate electrode 2A that are joined to each other, the pressure direction perpendicular component force F2 generated in the opposite directions is balanced via the semiconductor 1 and the substrate 2 to the semiconductor 1 and the substrate 2 2 is not moved. Therefore, even without special measures for preventing the movement of the semiconductor 1 and the substrate 2, the predetermined bonding state is maintained well, and this does not loosen during the bonding / sealing. The displacement 1 of the semiconductor 1 with respect to the substrate 2 is reliably prevented by increasing the inclination angle θ of the pressure contact surface 2A-1 or 3A and reliably preventing poor bonding due to the residual stress during pressure welding and inability to obtain predetermined electrical characteristics. This can also prevent the manufacturing yield of semiconductor devices. Therefore, the position shift hardly occurs, and even the angle θ of 60 ° or more can fall within the more preferable range. However, it is necessary to remove a large angle θ that causes deformation of one or both of the substrate electrode 2A and the semiconductor electrode 3 to be pressed in a direction perpendicular to the pressing direction V to cause escape joint failure.

このような互いに逆向きな接合方向直角分力F2の釣り合いによる位置ずれ防止効果は、それら互いに逆な接合方向直角分力F2が生じる基板電極2A、半導体電極3の各組の内側域や外側位置に、向きHに平行な圧接面を有して接合された基板電極2Aおよび半導体電極3の組みがあっても発揮される。   The effect of preventing misalignment due to the balance of the mutually perpendicular bonding direction perpendicular component forces F2 is such that the pair of substrate electrode 2A and semiconductor electrode 3 in which the opposite direction perpendicular component forces F2 are opposite to each other are generated. In addition, even if there is a set of the substrate electrode 2A and the semiconductor electrode 3 joined with a pressure contact surface parallel to the direction H, this is exhibited.

特に、図4に示す例では、前記互いに逆向きな圧接方向直角分力F2は、その釣り合い上、半導体1に圧縮を与える向き、つまり半導体1および基板2間に形成される空間における内向きとなっており、圧接方向Vに直角な向きの耐圧縮性が高い半導体1に好適となり、基板2には引っ張り力が働くことになるので、圧接方向Vに直角な向きの耐引っ張り性が高い基板2に好適となる。   In particular, in the example shown in FIG. 4, the opposite pressure direction perpendicular component forces F <b> 2 opposite to each other are in a direction to apply compression to the semiconductor 1, that is, inward in a space formed between the semiconductor 1 and the substrate 2. Therefore, it is suitable for the semiconductor 1 having high compression resistance in the direction perpendicular to the pressure contact direction V, and a tensile force acts on the substrate 2. Therefore, the substrate having high tensile resistance in the direction perpendicular to the pressure direction V. 2 is suitable.

また、反対に、図5に示す例、図6に示す例では、互いに逆向きな圧接方向直角分力F2は、その釣り合い上半導体1に引っ張りを与える向き、つまり半導体1および基板2間に形成される空間における外向きとなっており、圧接方向Vに直角な向きの耐引っ張り性が高い半導体1に好適となり、基板2には圧縮力が働くことになるので、圧接方向Vに直角な向きの耐圧縮性が高い基板2に好適となる。   On the other hand, in the example shown in FIG. 5 and the example shown in FIG. 6, the pressure direction perpendicular component forces F <b> 2 that are opposite to each other are formed in the direction in which the semiconductor 1 is pulled due to its balance, that is, between the semiconductor 1 and the substrate 2. Is suitable for the semiconductor 1 having a high tensile resistance in a direction perpendicular to the pressure direction V, and a compressive force is applied to the substrate 2. It is suitable for the substrate 2 having a high compression resistance.

これら互いに逆向きな接合方向直角分力F2の圧縮と引っ張りの釣り合い方式の選択は、半導体1や基板2の位置や向きで耐圧縮性、耐引っ張り性が異なる場合、その位置や向きでの耐圧縮性、耐引っ張り性に合せた部分的に異なった選択をすることもできる。   The selection of the compression and tension balance method of these mutually perpendicular joining direction perpendicular component forces F2 is selected when the compression resistance and the tensile resistance are different depending on the position and orientation of the semiconductor 1 and the substrate 2, respectively. Partially different selections can be made to suit the compressibility and tensile resistance.

図7に示す例では、基板電極2Aは、基板2の一面側に凸他面側に凹の反り形状による圧接方向Vに直角な向きに対し半導体1と前記基板2との間に形成される空間において外向きまたはおよび内向き、図示例では凸の反り形状にて外向きとなる圧接方向Vに直角な向きに対する傾斜により、傾斜した圧接面2A−1を有して対向し合うように位置し、半導体電極3と接合されている。これにより、基板2の互いに対向して位置する複数の基板電極2Aは、基板2の凸(またはおよび凹)の反り形状にて半導体1と基板2との間に形成される空間において外向き(またはおよび内向き)となる圧接方向Vに直角な向きに対する傾斜により、傾斜した圧接面2A−1を有して半導体電極3と接合されていて、半導体1および基板2が圧接状態を保って接着・封止材4による接着・封止を受けている間、その圧接面2A−1に垂直に働く圧接力Fを、半導体1に垂直な圧接方向分力F1と、半導体1に平行で前記空間に対し外向き(またはおよび内向き)に対向し合う互いに逆向きで釣り合う圧接方向直角分力F2と、に分解して、半導体電極3と所定の接合状態によく保たれ、これが緩むことはない。また、圧接方向直角分力F2は半導体1および基板2に圧接方向Vの内部応力を生じさせる働きはしないので、その分半導体1および基板2の圧接による内部残留応力が低減する。特に、基板電極2Aの圧接面2A−1の傾斜は基板2の反り形状によるもので、半導体電極3や基板電極2Aに半導体1や基板2の面に対して傾斜を持たせた特殊な形態に形成しなくてもよい上、予め反らせた基板2を採用して実現するが、基板2の反り形状も図示したように凸の支持面11aで基板2を支持して半導体1を圧接したときの反り変形によるものとすることにより、基板2を予め反らせておく手間も省略できる。なお、基板2の反り形状は接着・封止材4による接着・封止によって固定される。   In the example shown in FIG. 7, the substrate electrode 2 </ b> A is formed between the semiconductor 1 and the substrate 2 with respect to the direction perpendicular to the pressure contact direction V due to the warped shape of the concave surface on the other surface side of the substrate 2. Positioned so as to face each other with an inclined pressure contact surface 2A-1 due to an inclination with respect to a direction perpendicular to the pressure contact direction V, which is outward or inward in space, and convex outward in the illustrated example. The semiconductor electrode 3 is joined. As a result, the plurality of substrate electrodes 2 </ b> A positioned opposite to each other on the substrate 2 face outward (in a space formed between the semiconductor 1 and the substrate 2 in a convex (or concave) warped shape of the substrate 2 ( In addition, the semiconductor electrode 3 is bonded to the semiconductor electrode 3 with the inclined pressure contact surface 2A-1 by the inclination with respect to the direction perpendicular to the pressure contact direction V which is inward), and the semiconductor 1 and the substrate 2 are bonded in a pressure contact state. The pressure F acting perpendicularly to the pressure contact surface 2A-1 during the adhesion / sealing by the sealing material 4 is applied to the pressure direction component F1 perpendicular to the semiconductor 1 and the space parallel to the semiconductor 1 Are separated into pressure contact direction perpendicular component forces F2 that face each other outward (and inward) and balance each other in opposite directions, and are kept in a predetermined bonding state with the semiconductor electrode 3, which does not loosen. . In addition, since the perpendicular component F2 in the pressure direction does not act to cause internal stress in the pressure direction V on the semiconductor 1 and the substrate 2, the internal residual stress due to pressure contact between the semiconductor 1 and the substrate 2 is reduced accordingly. In particular, the inclination of the pressure contact surface 2A-1 of the substrate electrode 2A is due to the warped shape of the substrate 2, and the semiconductor electrode 3 or the substrate electrode 2A has a special form with an inclination with respect to the surface of the semiconductor 1 or the substrate 2. It is not necessary to form the substrate 2 and the substrate 2 is warped in advance. However, the warped shape of the substrate 2 is also supported when the semiconductor 2 is pressed by supporting the substrate 2 with the convex support surface 11a as shown in the figure. By using the warp deformation, the trouble of warping the substrate 2 in advance can be omitted. The warped shape of the substrate 2 is fixed by adhesion / sealing by the adhesion / sealing material 4.

図8に示す例では、反り形状の基板2の凸面側、凹面側の双方に半導体1、1Bを実装してあり、凸面で対向し合う基板電極2Aは半導体1と基板2との間に形成される空間において外向きに傾斜して半導体電極3と接合されて、接合時半導体1に引っ張りを与える圧接方向直角分力F2を生じさせるが、凹面で対向し合う基板電極2Aは半導体1Bと基板2との間に形成される空間において内向きに傾斜して半導体電極3Bと接合されて、接合時半導体1に圧縮を与える圧接方向直角分力F2を生じさせる。従って、半導体1は耐引っ張り性の高いものに適用し、半導体1Bは耐圧縮性に高いものに適したものとなる。この場合も、予め反らせた基板2を採用して実現するが、基板2の反り形状も図7に示す例のように上に凸の支持面基板2を支持して半導体1を圧接したときの反り変形によるものとすることにより、基板2を予め反らせておく手間が省略でき、半導体1の実装後に半導体1Bを実装すればよい。   In the example shown in FIG. 8, the semiconductors 1 and 1B are mounted on both the convex surface side and the concave surface side of the warped substrate 2, and the substrate electrodes 2A facing each other on the convex surface are formed between the semiconductor 1 and the substrate 2. In this space, the substrate electrode 2A is inclined outward and joined to the semiconductor electrode 3 to generate a perpendicular force F2 in the press-contact direction that pulls the semiconductor 1 at the time of joining. 2 is inclined inwardly in the space formed between the semiconductor electrode 3B and the semiconductor electrode 3B and joined to the semiconductor electrode 3B to generate a pressure component perpendicular to the pressure direction F2 that compresses the semiconductor 1 at the time of bonding. Therefore, the semiconductor 1 is suitable for those having high tensile resistance, and the semiconductor 1B is suitable for those having high compression resistance. This case is also realized by using the substrate 2 warped in advance, but the warped shape of the substrate 2 is also when the semiconductor 1 is pressed against the support surface substrate 2 that is convex upward as in the example shown in FIG. By being caused by warping deformation, it is possible to omit the trouble of warping the substrate 2 in advance, and the semiconductor 1B may be mounted after the semiconductor 1 is mounted.

図9に示す例では、図8に示す例のように反り形状の基板2の両面に第1、第2の半導体1C、1を実装しているが、特に、互いに接合される第1半導体電極3c、3cどうしと基板電極2A、2Aどうしは同一の第1対向距離L1を有して対向配置され、互いに接合される半導体電極3、3どうしおよび基板電極2A、2Aどうしは互いに同一で第1対向距離L1より大きな第2対向距離L2を有して対向配置され、第1対向距離L1域は基板2上で第2対向距離L2域内に位置し、対向し合う第1対向距離L1を有して対向し合う基板電極2A、2Aどうしおよび第2対向距離L2を有して対向し合う基板電極2A、2Aどうしは、基板2の半導体1C側に凹で半導体1側に凸の反り形状により、凹側では、圧接方向Vに直角な向きに対し対向し合う方向に互いに逆向きな半導体1Cおよび基板2間の空間において内向きとなるように傾斜した圧接面2A−1を有して半導体電極Cと接合されている。凸側では、圧接方向Vに直角な向きに対し対向し合う方向に互いに逆向きな半導体1Cおよび基板2間の空間において外向きとなるように傾斜した圧接面2A−1を有して半導体電極3と接合されている。これにより、図8の例の場合同様に、予め反り形状を持たせた基板2により実現するが、基板2の第1、第2半導体1、1Cのいずれかを実装したときの、あるいはそれらを同時に圧接したときの第1、第2対向距離L1、L2の大小の違いを利用した反り変形によるものとすることにより、基板2の反り形状を予め付与しておく手間も省略できる。   In the example shown in FIG. 9, the first and second semiconductors 1C and 1 are mounted on both surfaces of the warped substrate 2 as in the example shown in FIG. The semiconductor electrodes 3 and 3 and the substrate electrodes 2A and 2A that are joined to each other have the same first opposing distance L1, and the semiconductor electrodes 3 and 3 and the substrate electrodes 2A and 2A that are joined to each other are the same as each other. The first opposing distance L1 region is located within the second opposing distance L2 region on the substrate 2 and has a first opposing distance L1 that faces each other. The substrate electrodes 2A, 2A that face each other and the substrate electrodes 2A, 2A that face each other with a second facing distance L2 are warped so as to be concave on the semiconductor 1C side of the substrate 2 and convex on the semiconductor 1 side. On the concave side, it is A contact face 2A-1 which is inclined such that the inwardly facing direction each other in the space between the opposite semiconductor 1C and the substrate 2 to each other is joined to the semiconductor electrode C. On the convex side, a semiconductor electrode having a semiconductor contact electrode 2A-1 inclined so as to face outward in the space between the semiconductor 1C and the substrate 2 opposite to each other in a direction opposite to the direction perpendicular to the pressure contact direction V. 3 is joined. As in the case of the example of FIG. 8, this is realized by the substrate 2 having a warp shape in advance, but when either the first or second semiconductor 1 or 1C of the substrate 2 is mounted, or those By using the warp deformation utilizing the difference in size between the first and second opposing distances L1 and L2 when they are simultaneously pressed, it is possible to omit the time and effort of previously giving the warp shape of the substrate 2.

図10に示す例では、基板2は、基板電極2Aを有した互いに対向し合う各辺部2a、2bがそれらの間の中央部よりも耐屈曲性が小さく、両辺部2a、2bにある基板電極2Aどうしは、基板2の各辺部2a、2bの半導体1と基板2との間に形成される空間において前記対向する方向にて外向きとなる圧接方向Vに直角な向きに対する互いに逆向きな傾斜により、傾斜した圧接面2A−1を有して半導体電極3と接合されている。これにより、基板電極2Aの圧接面2A−1の傾斜は基板2の両辺部2a、2bの傾斜によるもので、半導体電極3や基板電極2Aに半導体1や基板2の面に対して傾斜を持たせた特殊な形態に形成しなくてもよい上、基板2の両辺部2a、2bの傾斜も中央部よりも耐屈曲性が小さく屈曲しやすいことを利用した予めの変形によっても実現するが、半導体1の圧接による変形によるものとすることにより、基板2の両辺部2a、2bを予め傾斜させておく手間も省略できる。図示例では基板2の両辺部2a、2bが中央部よりも厚さが小さくなる段差14を有したものであることにより、中央部よりも耐屈曲性が小さくなるものとなっている。また、段差14は基板2を平坦な支持面で支持したときに両辺部2a、2bを浮かせて半導体1の圧接により傾斜させやすくもする。しかし、これに限られることはなく、材質や内部構造など他の要因の違いを利用したものとしてよいし、また段差14は支持面側に設けて両辺部2a、2bを浮かせ圧接時に傾斜させやすくなっている。   In the example shown in FIG. 10, the substrate 2 is a substrate in which the side portions 2 a and 2 b facing each other having the substrate electrode 2 </ b> A have less bending resistance than the central portion between them, and are located on both sides 2 a and 2 b. The electrodes 2A are opposite to each other with respect to the direction perpendicular to the pressure contact direction V, which faces outward in the opposite direction in the space formed between the semiconductor 1 and the substrate 2 of each side 2a, 2b of the substrate 2. Due to the inclination, the semiconductor electrode 3 is joined with the inclined pressure contact surface 2A-1. Thus, the inclination of the pressure contact surface 2A-1 of the substrate electrode 2A is due to the inclination of both sides 2a and 2b of the substrate 2, and the semiconductor electrode 3 and the substrate electrode 2A are inclined with respect to the surfaces of the semiconductor 1 and the substrate 2. It is not necessary to form in a special shape, and the inclination of both sides 2a and 2b of the substrate 2 is also realized by a pre-deformation utilizing the fact that the bending resistance is smaller and easier to bend than the central part, By performing the deformation due to the pressure contact of the semiconductor 1, it is possible to omit the labor of inclining both sides 2 a and 2 b of the substrate 2 in advance. In the illustrated example, both side portions 2a and 2b of the substrate 2 have a step 14 whose thickness is smaller than that of the central portion, so that the bending resistance is smaller than that of the central portion. Further, the step 14 also makes it easy to incline the two sides 2 a and 2 b by pressing the semiconductor 1 when the substrate 2 is supported by a flat support surface. However, the present invention is not limited to this, and the difference in other factors such as the material and the internal structure may be used. Further, the step 14 is provided on the support surface side so that both sides 2a and 2b are floated and can be easily inclined during pressure welding. It has become.

図11に示す例は、基板2は、半導体1の一辺部1aに有した半導体電極3と接合された基板電極2Aを有した一辺部2aが他辺部2b側よりも耐屈曲性が小さく、基板2の一辺部2aにある基板電極2Aは、基板2の一辺部2aの半導体1と基板2との間に形成される空間において外向きとなる圧接方向Vに直角な向きに対する傾斜により、傾斜した圧接面2A−1を有して半導体電極3と接合されている。この場合も、基板電極2Aの圧接面2A−1の傾斜は基板2の一辺部2aの傾斜によるもので、半導体電極3や基板電極2Aに半導体1や基板2の面に対して傾斜を持たせた特殊な形態に形成しなくてもよい上、基板2の一辺部2aの傾斜も予め成形しておいても実現するが、他辺部2b側よりも耐屈曲性が小さく屈曲しやすいことを利用した半導体1の一辺1a側での圧接による変形によるものとすることにより、基板2の一辺部2aを予め傾斜させておく手間も省略できる。図示例では基板2の一辺部2aが他辺部2b側の裏面に形成したフォトレジスト層6の厚さ分だけ厚さが小さくなる段差14を有したものであることと、かつフォトレジスト層6を有しないことにより、他辺部2b側よりも耐屈曲性が小さくなるものとなっている。また、段差14は基板2を平坦な支持面で支持したときに両辺部2a、2bを浮かせて半導体1の圧接により傾斜させやすくもする。しかし、これに限られることはなく、材質や内部構造など他の要因の違いを利用したものとしてよいし、また段差14は支持面側に設けて一辺部2aを浮かせられる。本例では、別の半導体1Dをも組み合わせ実装してメモリカード、特に小型なSDメモリカード(Secure Digital memory card)、さらに小さいミニSDメモリカードを形成しており、半導体1の特に残留内部応力に対して弱い一辺部1a側での半導体電極3、基板電極2A間の接合位置にて、傾斜した圧接面2A−1による残留内部応力を軽減するようにしている。ちなみに、SDメモリカードは通常、図の左右方向寸法である長さが14.9mm以上15.1mm以下、図の奥行方向寸法である幅が10.9mm以上11.1mm以下、図の上下方向寸法である厚さが0.9mm以上1.1mm以下である。基板2の厚さはFR−4相当のガラスエポキシ樹脂基板の場合、0.1mm、半導体1はメモリチップ、半導体1Dはコントロールチップであり、いずれも厚さは0.05mm以上0.3mm以下である。しかし、これらの寸法データは本実施の形態で示す各基板2や半導体1〜1Dにも対応する。   In the example shown in FIG. 11, the substrate 2 has less bending resistance than the other side 2b side, the one side 2a having the substrate electrode 2A joined to the semiconductor electrode 3 on the one side 1a of the semiconductor 1; The substrate electrode 2A on the one side 2a of the substrate 2 is inclined due to the inclination with respect to the direction perpendicular to the pressure contact direction V that is outward in the space formed between the semiconductor 1 and the substrate 2 on the one side 2a of the substrate 2. It has the press-contact surface 2A-1 and is joined to the semiconductor electrode 3. Also in this case, the inclination of the pressure contact surface 2A-1 of the substrate electrode 2A is due to the inclination of the one side 2a of the substrate 2, and the semiconductor electrode 3 and the substrate electrode 2A are inclined with respect to the surface of the semiconductor 1 and the substrate 2. It is not necessary to form in a special form, and the inclination of the one side 2a of the substrate 2 can be realized by pre-molding, but it has a lower bending resistance than the other side 2b and is easy to bend. By making the deformation by the pressure contact on the side 1a side of the semiconductor 1 used, it is possible to omit the labor of inclining the one side portion 2a of the substrate 2 in advance. In the illustrated example, one side 2a of the substrate 2 has a step 14 that decreases in thickness by the thickness of the photoresist layer 6 formed on the back surface on the other side 2b side, and the photoresist layer 6 By not having, the bending resistance becomes smaller than the other side 2b side. Further, the step 14 also makes it easy to incline the two sides 2 a and 2 b by pressing the semiconductor 1 when the substrate 2 is supported by a flat support surface. However, the present invention is not limited to this, and the difference in other factors such as the material and the internal structure may be used. Further, the step 14 is provided on the support surface side, and the one side 2a can be floated. In this example, another semiconductor 1D is also mounted in combination to form a memory card, particularly a small SD memory card (Secure Digital memory card), and a smaller mini SD memory card. On the other hand, the residual internal stress due to the inclined pressure contact surface 2A-1 is reduced at the bonding position between the semiconductor electrode 3 and the substrate electrode 2A on the weak side 1a side. Incidentally, an SD memory card usually has a length in the horizontal direction of the figure of 14.9 mm to 15.1 mm, a width of the depth dimension of the figure of 10.9 mm to 11.1 mm, and the vertical dimension of the figure. The thickness is 0.9 mm or more and 1.1 mm or less. In the case of a glass epoxy resin substrate equivalent to FR-4, the thickness of the substrate 2 is 0.1 mm, the semiconductor 1 is a memory chip, and the semiconductor 1D is a control chip, both of which have a thickness of 0.05 mm to 0.3 mm. is there. However, these dimension data also correspond to the respective substrates 2 and semiconductors 1 to 1D shown in the present embodiment.

図12に示す例では、基板2の裏面に、図11に示すフォトレジスト層6に代えてシール層8を設け段差14を形成した点が相違している。   The example shown in FIG. 12 is different in that a seal layer 8 is provided on the back surface of the substrate 2 in place of the photoresist layer 6 shown in FIG.

図10、図11、図12の各例において、段差14によって基板2に生じるデッドスペースを利用して一辺部2aの裏面に図13に示す例で代表しているように外部電極7を設けることによりメモリカードなどのさらなる薄型化が図れる。   10, 11, and 12, the external electrode 7 is provided on the back surface of the one side portion 2 a using the dead space generated in the substrate 2 due to the step 14 as represented in the example shown in FIG. 13. As a result, the memory card can be made thinner.

図14に示す例では、基板2を支持する支持面11aの、傾斜した圧接面2A−1を持った基板電極2Aに対応する位置に、基板2の変形を許容する凹部15を形成しておき、半導体1の圧接を伴い半導体電極3が電気的に接合されたとき、基板電極2Aを介し基板2が凹部15に沿って窪むように変形されたとき、基板電極2Aが基板2の一部と共に傾き傾斜した圧接面2A−1となって接合され、半導体1の基板電極2A、半導体電極3間の接合位置での残留内部応力が軽減されるようにしている。この場合も、予め変形させておけるが、半導体1の圧接時に変形されるようにすることで、予め変形させておく手間を省略することができる。   In the example shown in FIG. 14, a recess 15 that allows deformation of the substrate 2 is formed at a position corresponding to the substrate electrode 2 </ b> A having the inclined pressure contact surface 2 </ b> A- 1 on the support surface 11 a that supports the substrate 2. When the semiconductor electrode 3 is electrically joined with the pressure contact of the semiconductor 1 and the substrate 2 is deformed so as to be recessed along the recess 15 via the substrate electrode 2A, the substrate electrode 2A is inclined together with a part of the substrate 2 The inclined pressure contact surface 2A-1 is joined and the residual internal stress at the joining position between the substrate electrode 2A and the semiconductor electrode 3 of the semiconductor 1 is reduced. In this case as well, it can be deformed in advance, but by deforming at the time of pressure contact of the semiconductor 1, it is possible to omit the time and effort of deforming in advance.

図15に示す例でも、基板2のフォトレジスト層6やシール層8による段差14を利用して半導体1の圧接を伴う接合時に基板2の一辺部2aを傾斜させて、基板電極2Aに傾斜した圧接面2A−1を持たせて半導体1の一辺部の半導体電極3と接合させているが、本例では他の場合とは異なり、前記圧接のための加圧ヘッド10に半導体1の一辺1a側を傾斜させる傾斜凸部10aを設けておき、半導体1を加圧ヘッド10により加圧して基板2側に圧接させる過程で、傾斜凸部10aが半導体1の一辺側を図示のように傾斜するように屈曲変形させることで、半導体1の他の部分よりも基板2への押し付け量を高め、基板2の一辺部2aを、基板電極2Aを介し押動し傾斜させたものとしている。このような半導体1の屈曲変形は近時の薄型化によって可能となっており、例えばシリコン材で5°程度の傾斜への屈曲変形による内部応力は、半導体1の圧接により問題となる残留内部応力に比し軽微である。従って、半導体1の一部を屈曲させることにより基板2に屈曲変形をもたらし、基板電極2Aの基板2に平行な電極面を傾斜した圧接面2A−1として圧接力Fの圧接方向分力F1と圧接方向直角分力F2とに分解することは、半導体1を圧接による残留内部応力軽減に有効である。   Also in the example shown in FIG. 15, one side 2 a of the substrate 2 is inclined at the time of bonding accompanied by the pressure contact of the semiconductor 1 using the step 14 by the photoresist layer 6 or the sealing layer 8 of the substrate 2, and is inclined to the substrate electrode 2 </ b> A. Unlike the other cases, in this example, the pressure head 10 for the pressure contact is connected to the one side 1a of the semiconductor 1 while the pressure contact surface 2A-1 is provided and bonded to the semiconductor electrode 3 on one side of the semiconductor 1. An inclined convex portion 10a is provided to incline the side, and the inclined convex portion 10a inclines one side of the semiconductor 1 as shown in the process in which the semiconductor 1 is pressed by the pressure head 10 and pressed against the substrate 2 side. By bending and deforming in this way, the amount of pressing to the substrate 2 is increased more than other portions of the semiconductor 1, and one side 2a of the substrate 2 is pushed and inclined through the substrate electrode 2A. Such bending deformation of the semiconductor 1 is made possible by recent thinning. For example, the internal stress due to bending deformation of the silicon material to an inclination of about 5 ° is a residual internal stress that becomes a problem due to the pressure contact of the semiconductor 1. Compared to Therefore, bending part of the semiconductor 1 causes the substrate 2 to bend and deform, and the electrode surface parallel to the substrate 2 of the substrate electrode 2A is used as the pressure contact surface 2A-1 in the pressure direction F1 of the pressure force F. Disassembling the pressure component in the pressure direction perpendicular component F2 is effective in reducing the residual internal stress of the semiconductor 1 by pressure welding.

本発明は。基板に半導体を圧接を伴い電気的に接合して接着・封止材により接着・封止して実装する技術に実用でき、十分な接合の基に実装した半導体に所定の電気特性を保証でき、信頼性の高いものとなる。   The present invention. It can be put into practical use in the technology of bonding the semiconductor to the substrate with pressure contact, bonding and sealing with adhesive / sealing material, and guaranteeing the predetermined electrical characteristics to the semiconductor mounted on the basis of sufficient bonding, It will be highly reliable.

本発明の実施の形態に係る半導体装置の第1の例で、複数の基板電極の接合用の圧接面を同じ側に傾斜させた場合を示す断面図およびその一部の模式説明図である。In the first example of the semiconductor device according to the embodiment of the present invention, there are a cross-sectional view and a schematic explanatory diagram of a part of the case where the pressure contact surfaces for joining a plurality of substrate electrodes are inclined to the same side. 同半導体装置の第1の例の接着・封止材を変えた変形例に当たる第2の例を示す断面図である。It is sectional drawing which shows the 2nd example equivalent to the modification which changed the adhesion | attachment and sealing material of the 1st example of the same semiconductor device. 同半導体装置の第3の例で、基板電極、半導体電極の双方を傾斜させて導電性微片を介し接合する場合を示す一部の断面図である。In the third example of the semiconductor device, it is a partial cross-sectional view showing a case where both the substrate electrode and the semiconductor electrode are inclined and bonded via conductive fine pieces. 同半導体装置の第4の例で、複数の対向し合う基板電極の接合用の圧接面を前記対向し合う側に傾斜させた場合を示す断面図である。It is sectional drawing which shows the case where the press-contact surface for joining of the several board | substrate electrode which opposes is inclined to the said opposing side in the 4th example of the same semiconductor device. 同半導体装置の第5の例で、第4の例とは反対に複数の対向し合う基板電極の圧接面を前記対向し合う側とは反対の向きに傾斜させた場合を示す断面図である。In the fifth example of the semiconductor device, a cross-sectional view showing a case where the press contact surfaces of a plurality of opposing substrate electrodes are inclined in the direction opposite to the opposing side, as opposed to the fourth example. . 同半導体装置の第6の例で、複数の対向し合う半導体電極の接合用の圧接面を傾斜させ、かつその傾斜が前記対向し合う側に向くようにした場合を示した断面図である。It is sectional drawing which showed the case where the pressure-contact surface for joining of several semiconductor electrodes which oppose was inclined in the 6th example of the same semiconductor device, and the inclination was made to face the said opposing side. 同半導体装置の第7の例で、複数の対向し合う基板電極の接合用の圧接面を基板の反り形状によって前記対向し合う側と反対の向きに傾斜させた場合を示す断面図である。It is sectional drawing which shows the case where the press-contact surface for joining of several opposing board | substrate electrodes is inclined in the direction opposite to the said opposing side by the curvature shape of a board | substrate in the 7th example of the same semiconductor device. 同半導体装置の第8の例で、基板の表裏に半導体を実装してあり、基板の反り形状によって基板面が凸の側では複数の対向し合う基板電極の接合用の圧接面が前記対向し合う側と反対の向きに傾斜させ、基板面が凹の側では複数の対向し合う基板電極の接合用の圧接面が前記対向し合う側と反対の向きに傾斜させた場合を示す断面図である。In an eighth example of the semiconductor device, semiconductors are mounted on the front and back of the substrate, and the pressure contact surfaces for bonding a plurality of opposing substrate electrodes are opposed to each other on the convex side of the substrate due to the warped shape of the substrate. FIG. 6 is a cross-sectional view showing a case in which a pressure contact surface for joining a plurality of opposing substrate electrodes is inclined in a direction opposite to the opposing side when the substrate surface is inclined on the concave side. is there. 同半導体装置の第9の例で、基板の表裏に大きさの違う半導体を実装したときの基板の反り形状によって、基板面が凸の側では複数の対向し合う基板電極の接合用の圧接面が前記対向し合う側と反対の向きに傾斜させ、基板面が凹の側では複数の対向し合う基板電極の接合用の圧接面が前記対向し合う側と反対の向きに傾斜させた場合を示す断面図である。In the ninth example of the semiconductor device, pressure contact surfaces for joining a plurality of opposing substrate electrodes on the convex side of the substrate surface due to the warped shape of the substrate when semiconductors of different sizes are mounted on the front and back of the substrate Is inclined in the direction opposite to the opposing side, and the pressure contact surface for bonding a plurality of opposing substrate electrodes is inclined in the opposite direction to the opposing side on the concave substrate side. It is sectional drawing shown. 同半導体装置の第10の例で、半導体との接合を行う基板の両辺部が中央部よりも耐屈曲性が小さいのを利用した半導体接合時などの屈曲変形によって、両辺部上で中央部を挟んで対向し合う複数の基板電極の接合用の圧接面を前記対向し合う側と反対の向きに傾斜させた場合を示す断面図である。In the tenth example of the semiconductor device, the central part is formed on both sides by bending deformation such as in semiconductor joining using the fact that both sides of the substrate to be bonded to the semiconductor have lower bending resistance than the central part. It is sectional drawing which shows the case where the press-contact surface for joining of several board | substrate electrodes which oppose on both sides is inclined in the direction opposite to the said opposing side. 同半導体装置の第11の例で、半導体のメモリチップと半導体のコントロールチップとを基板に実装してメモリカードとしており、メモリチップの一辺部と接合を行う基板の一辺部がそれより増圧する段差を有してフォトレジスト層を設けた他辺部側よりも耐屈曲性が小さいことを利用したメモリチップ接合時などの屈曲変形によって、一辺部上の基板電極の接合用の圧接面をメモリチップおよび基板間の空間において外向きに傾斜させた場合を示す断面図である。In the eleventh example of the semiconductor device, a semiconductor memory chip and a semiconductor control chip are mounted on a substrate to form a memory card, and one side of the memory chip and one side of the substrate to be joined are stepped higher than that. The pressure contact surface for bonding substrate electrodes on one side is formed by bending deformation at the time of memory chip bonding utilizing the fact that the resistance to bending is smaller than that of the other side having a photoresist layer and having a photoresist layer. It is sectional drawing which shows the case where it inclines outward in the space between board | substrates. 同半導体装置の第12の例で、第11の例のフォトレジスト層に代えてシール層を設けた変形例とした場合を示す断面図である。It is sectional drawing which shows the case where it is set as the modification which provided the sealing layer instead of the photoresist layer of the 11th example in the 12th example of the same semiconductor device. 同半導体装置の第13の例で、第11、12の例の段差によりできるデッドスペースを利用して外部電極を設けた変形例とした場合を示す断面図である。It is sectional drawing which shows the case where it is set as the modification which provided the external electrode using the dead space formed by the level | step difference of the 11th, 12th example in the 13th example of the same semiconductor device. 同半導体装置の第14の例で、基板の半導体実装時における複数の対向する基板電極と半導体電極との各接合位置で生じる局部変形によって、各接合位置における基板電極の接合用の圧接面を前記対向する側の反対の側に傾斜させた場合を示す断面図である。In the fourteenth example of the semiconductor device, the pressure contact surface for bonding the substrate electrode at each bonding position is obtained by local deformation occurring at each bonding position between the plurality of opposing substrate electrodes and the semiconductor electrode when the substrate is mounted on the semiconductor. It is sectional drawing which shows the case where it makes it incline to the opposite side of the side which opposes. 同半導体装置の第15の例で、第11〜第13の例の基板の一辺部の屈曲変形に対する変形例であって、半導体を基板に圧接させる際に基板の一辺部に対応する一辺部を屈曲変形させて半導体電極、基板電極を介し基板の一辺部を積極的に押圧して屈曲変形させた場合を示す断面図である。The fifteenth example of the semiconductor device is a modification example of the bending deformation of one side of the substrate of the first to thirteenth examples, and the one side corresponding to the one side of the substrate is pressed when the semiconductor is pressed against the substrate. It is sectional drawing which shows the case where it bends and deform | transforms by positively pressing the one side part of a board | substrate via a semiconductor electrode and a board | substrate electrode. 基板に半導体を圧接して基板電極および半導体電極を電気的に接合させてそれを保持し、基板および半導体間を接着・封止材により接着・封止した従来の半導体装置とその圧接時に圧接力によって半導体に生じる残留内部応力の発生状態を模式的に示す断面図である。A conventional semiconductor device in which a semiconductor is press-contacted to a substrate, the substrate electrode and the semiconductor electrode are electrically bonded and held, and the substrate and the semiconductor are bonded / sealed with an adhesive / sealing material, and the pressure contact force at the time of the press-contact It is sectional drawing which shows typically the generation | occurrence | production state of the residual internal stress which arises in a semiconductor by. 半導体装置の接着・封止フィルムを用いた従来方式を説明する同フィルムの断面図、それを用いた実装の途中工程を示す断面図である。It is sectional drawing of the film explaining the conventional system using the adhesion | attachment and sealing film of a semiconductor device, and sectional drawing which shows the middle process of the mounting using it.

符号の説明Explanation of symbols

1、1B、1C、1D 半導体
1a 一辺部
2 基板
2a 一辺部
2b 他辺部
2A 基板電極
2A−1 傾斜した圧接面
3 半導体電極
3A 傾斜した圧接面
4 接着・封止材
L1 第1対向距離
L2 第2対向距離
1, 1B, 1C, 1D Semiconductor 1a One side 2 Substrate 2a One side 2b Other side 2A Substrate electrode 2A-1 Inclined pressure contact surface 3 Semiconductor electrode 3A Inclined pressure contact surface 4 Adhesive / sealing material L1 First opposing distance L2 Second facing distance

Claims (7)

半導体と、
基板と、
前記半導体に形成された半導体電極と、
前記半導体電極に接合された前記基板上の基板電極と、
前記半導体と前記基板との間に位置する接着・封止材と、
前記基板の前記半導体が位置する面と異なる面に位置するシール層とを有し、
前記基板のシール層がない部分を傾斜させ、前記傾斜させた傾斜面にて、前記基板電極と前記半導体電極とを接合したことを特徴とする半導体装置。
Semiconductors,
A substrate,
A semiconductor electrode formed on the semiconductor;
A substrate electrode on the substrate engaged against the semiconductor electrode,
An adhesive / sealing material positioned between the semiconductor and the substrate;
A seal layer located on a different surface from the surface on which the semiconductor of the substrate is located
A semiconductor device , wherein a portion of the substrate without a sealing layer is inclined, and the substrate electrode and the semiconductor electrode are bonded to each other at the inclined inclined surface .
前記半導体を前記傾斜面で屈曲させた請求項1記載の半導体装置。 The semiconductor device according to claim 1, wherein the semiconductor is bent at the inclined surface . 前記傾斜面は、前記基板の端である一辺の部分である請求項1または2に記載の半導体装置。 The inclined surface is a semiconductor device according to claim 1 or 2, wherein a portion of one side is an end of the substrate. 前記一辺の部分に外部電極を設けた請求項に記載の半導体装置。 The semiconductor device according to claim 3 , wherein an external electrode is provided on the one side portion . 前記シール層は、レジストである請求項1から4のいずれか1項に記載の半導体装置。 The semiconductor device according to claim 1, wherein the seal layer is a resist . 前記半導体は、メモリチップであり、さらに、前記基板のシール層がない部分にコントロールチップが前記基板に接合されている請求項1から5のいずれか1項に記載の半導体装置。 The semiconductor device according to claim 1, wherein the semiconductor is a memory chip, and a control chip is bonded to the substrate at a portion where the sealing layer of the substrate is not present . 半導体装置は、SDメモリカードである請求項1から6のいずれか1項に記載の半導体装置。 The semiconductor device according to claim 1, wherein the semiconductor device is an SD memory card .
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